Semiconductor memory device

Abstract

In a semiconductor memory device comprising memory cells in which first and second potentials correspond to the logic values "0" and "1", the first potential is closer to the second potential than the potential of unselected word lines, by 0.3 V or more. The pull-up transistor is of the N-type, and the pull-down transistor is of the P-type.

Description

FIG. 1 is a circuit diagram, as is shown in FIG. 1A. In this case, the sense circuitry operates at a high speed.

In the embodiment, the sense amplifier has a COS type flip-flop circuit. When the pull-down transistor at the side of the minus (ground) voltage supply is of the P-type instead of the N-type, the sense amplifier may consist of NMOS transistors only.

When a P-type transistor is used as the switching transistor in a memory cell, a memory device according to the invention can be realized by replacing the conductivity type of each transistors described above with the other conductivity type and also by replacing the connecting position of the voltage supply lines with each other. In this case, the positions of the power source and the ground in FIG. 1 are replaced with each other, and the power source generates a negative voltage. The potential of the word line ranges from 0 V to -5 V. When the potential of the word line is 0 V, the memory cell is unselected, and, when the potential is -5 V, the memory cell is selected. The potential of the bit line ranges from -1 V (:"0") to -4 V (:"1").

It is understood that various other modifications will be apparent to and can be readily made by those skilled in the art without departing from the scope and spirit of this invention. Accordingly, it is not intended that the scope of the claims appended hereto be limited to the description as set forth herein, but rather that the claims be construed as encompassing all the features of patentable novelty that reside in the present invention, including all features that would be treated as equivalents thereof by those skilled in the art to which this invention pertains.

Claims

1. A semiconductor device comprising:

a plurality of memory cells capable of being selected for use or remaining unselected, at least one unselected memory cell having a logical value of "0" and having a first signal voltage potential corresponding to a first logical value;

at least one selected memory cell having a logical value of "1" and having a second signal voltage potential corresponding to a second logical value;

a first set of reading and restoring word lines line connected to selected memory cells, said first set of word lines line having a signal voltage potential which is higher than said second signal voltage potential by a first predetermined value; and

a second set of word lines line connected to unselected memory cells, said second set of word lines line having a signal voltage potential which is higher lower than said first signal voltage potential by a second and different predetermined value.

2. A semiconductor memory device according to claim 1, wherein said second and different predetermined value is 0.3 V or more.

3. The semiconductor memory device of claim 1 comprising a sense circuit to which first and second bit lines are connected at first and second nodes, respectively, said sense circuit comprises:

a first MOS transistor of a first conductivity type connected between a first voltage line and a third node;

second and third MOS transistors of the first conductivity type, the source and drain of said second MOS transistor being connected between said first and third nodes, the source and drain of said third MOS transistor being connected between said second and third nodes;

a fourth MOS transistor of the first conductivity type connected between a second voltage line and a fourth node; and

fifth and six MOS transistors of a second conductivity type, the source and drain of said fifth MOS transistor being connected between said first and fourth nodes, the source and drain of said sixth MOS transistor being connected between said second and fourth nodes;

the gate of said second and fifth MOS transistors being connected to said second node, the gate of said third and sixth MOS transistors being connected to said first node. 4. The semiconductor memory device of claim 1 comprising a sense circuit to which first and second bit lines are connected at first and second nodes, respectively, said sense circuit comprises:

a first MOS transistor of a first conductivity type connected between a first voltage line and a third node;

second and third MOS transistors of a second conductivity type, the source and drain of said second MOS transistor being connected between said first and third nodes, the source and drain of said third MOS transistor being connected between said second and third nodes;

a fourth MOS transistor of the second conductivity type connected between a second voltage line and a fourth node; and

fifth and sixth MOS transistors of the first conductivity type, the source and drain of said fifth MOS transistor being connected between said first and fourth nodes, the source and drain of said sixth MOS transistor being connected between said second and fourth nodes;

the gate of said second and fifth MOS transistors being connected to said second node, the gate of said third and sixth MOS transistors being connected to said first node.