A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a system control processor interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. control circuitry is also provided for setting the a20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse keyboard interface (MKI) is provided. The MKI provides even quicker switching of the gate a20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.
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1. A computer system comprising:
a central processing unit (CPU) for processing data adapted to be coupled to one or more peripheral devices by way of a predetermined keyboard interface, said CPU having at least two modes of operation including a real mode of operation for accessing memory up to one megabyte, said mode of and a protected mode for accessing memory above one megabyte, said mode of operation adapted to be selected by one or more predetermined control signals, said CPU adapted to be reset by way of a predetermined reset signal; a memory for storing data, said memory having a preselected number of addressable storage locations larger than one megabyte, said storage locations being selectable by at least twenty-one address lines A0-a20, said memory and said CPU connected to a common bus; means for enabling said a20 address line for memory accesses over one megabyte in response to a hardware based gate a20 control signal; a system control processor (SCF) SCP for communicating with said CPU and adapted to generate the reset signal for resetting said CPU under predetermined conditions; and interfacing means interconnected between said CPU and said SCP for interfacing said CPU and said SCP for controlling communication between said CPU and said SCP and for emulating said predetermined keyboard interface, said interfacing means including predetermined hardware for enabling switching the mode of operation of said CPU from said real mode of operation to said protected mode of operation and for generating the hardware based gate a20 signal for enabling said CPU to access memory above one megabyte by automatically enabling said a20 address line in response to said hardware based gate a20 control signal, said interfacing means further including means for enabling either said SCP or said CPU to generate said reset signal.
2. A computer system as recited in
3. A computer system as recited in
4. A computer system as recited in
5. A computer system as recited in
6. A computer system as recited in
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This application is DRAWINGdrawingand SCPADO:7SDO:7this location using the SCP
| TABLE VIII |
| ______________________________________ |
| SCP MEMORY MAP I0000H |
| ______________________________________ |
| External RAM for Program/Data Storage. |
| 8000H |
| 32k bytes max. |
| MKI Feature: Enable/Disable generation of |
| 000FH |
| IBF for a CPU write of command `D1` and the data. |
| SCPAD0 = 1 => Enable |
| SCPAD0 = 0 => Disable |
| IR012: Enable/Disable IR012 |
| 000EH |
| SCPAD0 = 1 => Enable |
| SCAPD0 = 0 => Disable |
| Auxilliary Auxiliary Output Buffer: |
| 000DH |
| Write a byte to the output Buffer and set to Auxiliary |
| Output Buffer Full, and OBF bits of the Status Register. |
| Read back information from the chip flip-flops. |
| Gate A20 & Slow Reset: Enable/Disable |
| 000CH |
| automatic generation of the Gate A20 and slow reset |
| signals. |
| Gate A20: A Write to this Location forces |
| 000BH |
| the A20 signal high (active) |
| Gate A20: A Write to this Location forces |
| 000AH |
| the A20 signal low (inactive). A Read at this location |
| retruns returns the value of A20 in SCPAD1. |
| Slow Reset: A Write to this location |
| 0009H |
| forces the-RC signal high (inactive). |
| Slow Reset: A Write to this location |
| 0008H |
| forces the -RC signal low (active). A Read at this |
| Location returns the value of -RC in SCPAD0. |
| Status Register: The Status Register can |
| 0007H |
| be read back at this location. SCPAD<0:7>. |
| Output Buffer: The Output Buffer can be |
| 0006H |
| read back at this Location. SCPAD<0:7>. |
| IRQ1: Enable/Disable IRQ1. 0005H |
| SCPAD0 = 1 => Enable |
| SCPAD0 = 0 => Disable |
| Port 6: Write External Port #6 (6.0-6.7) |
| 0004H |
| Port 5: Read/Write External Port #5 (5.0-5.7) |
| 0003H |
| Port 4: Read/Write External Port #4 (4.0-4.7) |
| 0002H |
| Status Register: Write a byte to the |
| 0001H |
| Status Register Input Buffer: Read the byte out of the |
| Input Buffer. |
| Output Buffer: Write a byte to the |
| 0000H |
| Output Buffer. |
| Input Buffer: Read the byte out of the Input Buffer. |
| ______________________________________ |
Thirty-two kilobytes of external RAM 348 (FIG. 10) can be accessed by the SCP 26 between addresses 8000H-FFFFH. Since the SCP address bit SCPA 15 SCPA15 will only be high or a logical 1 for addresses 80000H and above, this bit SCPA 15 SCPA15 is used to determine whether the SCP 26 access is a MKI 300 access or a RAM 348 access. If external RAM 348 is not used, the bit SCPA [15] can be tied low thus allowing all external memory accesses by the SCP 26 to be to the MKI 300.
The address decode and RAM control logic 308 is illustrated in FIGS. 13 and 14. As previously mentioned, thirty-two kilobytes of external RAM 348 can be addressed by the SCP 26 at addresses 8000H-FFFFH for program storage. More particularly: the MKI 300 generates a RAM chip select signal (-RAMCS), a RAM output enable signal (-RAMOE) and a RAM address latch enable signal (RAMALE) for external RAM control. These signals along with SCP read and write signals (SCPRD, SCPWR) allow the SCP 26 to read and write to the RAM 348. Thus, as discussed above, the SCP address bit SCPA 15 determines whether the access is a RAM 348 access or a MKI 300 access. More particularly, the bit SCPA 15 is inverted by way of an inverter 350 and applied to a buffer 352 to generate the RAM chip select signal (-RAMCS) during a RAM 348 access. The RAM chip select signal (-RAMCS) is active low and will be active any time the address lines .Badd.8000H-FFF.Baddend. 8000H-FFF3FH are placed on the SCP 26 address data bus SCPAD [0:7]. The address on the SCP address data bus SCPAD [0:7] is latched by a RAM address latch enable signal (RAMALE). The RAM address latch enable signal (RAMALE) is generated by the MKI 300 and is derived from the SCP address latch enable signal (SCPALE) available from the SCP 26. More specifically, the SCP address latch enable signal (SCPALE) is applied to a buffer 354. The RAM address latch enable signal (RAMALE) is available at the output of the buffer 354. In order for the SCP 26 to write a byte to the external RAM 348, an SCP write signal (SCPWR) is brought low. The SCP 26 can read a byte from the RAM 348 by way of the RAM output enable signal (-RAMOE). More specifically, the RAM output enable signal (-RAMOE) is generated by the MKI 300 by ORing an SCP read signal (-SCPRD) with the RAM access control signal SCPA 15 by way of an OR gate 356. The output of the OR gate 356, which indicates a read by the SCP 26 of the RAM 348, is NANDed with a control signal (-PSEN) by way of a NAND gate 358. The signal PSEN relates to a program store enable and provides a strobe for accessing external memory stored in the RAM 348. Since the RAM output enable signal (-RAMOE) is active low, the output of the NAND gate 358 is applied to an inverter 360. The RAM output enable signal (-RAMOE) is available at the output of the inverter 360.
In addition to accessing the RAM 348, the SCP 26 can also access various external input/output ports (port P4, port P5 and port P6) as well as communicate with the CPU by way of an input buffer 362, an output buffer 364, a status buffer 366 and an auxiliary output buffer 368 through memory mapping. The SCP 26 can both read and write to ports P4 and P5 while port P6 is a write only port relative to the SCP 26. The output ports (P4, P5 and P6), as well as the input buffer 362, output buffer 364, status register 366 and an auxiliary output buffer 368 are located at addresses 0000H through 000FH as delineated in TABLE VIII. As previously mentioned, the SCP 26 address bit SCPA [15] is low for addresses in this range and is active high only for addresses 8000H and above, indicative of a RAM access. Thus, the bit SCPA 15 may be applied to a decoder 370 (FIG. 13) for decoding addresses between 0000H and 0000FH. More specifically, the lower eight bits of an SCP address are applied to latches 372 through 386 by way of the SCP internal address data bus SCPADIN [0:7]. The latches 372 to 386 are enabled by an SCP address latch enable signal (-SCPALE), which is active below and available at the output of an inverter 388. The signal (-SCPALE) is applied to an enable input (EN) of the latches 372-386. The latches 372-386 are reset by a signal (-RESET), available at the output of a buffer 391.
The outputs of the address latches 372 to 386 are applied to the 4×16 address decoder 370 by way of an internal address bus SPA [0:7]. More specifically, the upper nibble (e.g., SPA [7:4]) is NORed with the SCPA 15 by way of a NOR gate 389 signal to enable the address decoder 370 any time the SCP 26 is not accessing the RAM 348. For addresses 0000H through 000FH, the bits SPA [7:4] in the upper nibble will all be low. These bits, SPA [7:4] are applied to the NOR gate 389, which is used to enable the decoder 370. The lower nibble (e.g., SPA [3:0]) is applied to the address inputs A3, A2, A1, A0, respectively, of the address decoder 370. The output of the address decoder 370 is then used to generate read and write signals for the various input output ports (P4, P5 and P6) and as well as for the input buffer 362, output buffer 364 and status register 366 buffers. Additionally, the address decoder 370 generates address control signals a a000 [15:8] and a000 [5] as will be discussed below. More specifically, the address decoder 370 provides sixteen outputs SEL0-SEL15, which are all active low. The decoder 370 output signals are ORed with SCP write (-SCPWR) and SCP read (-SCPRD) read signals to generate read and write signals for the various input output ports as well as the input buffer 362, output buffer 364 and status register 366 by way of the OR gates 388 to 406. Moreover, since the input buffer 362 can be read at either address 0000H or address 0001H, the select outputs (-SEL0) and (-SEL1) are ANDed by way of an AND gate 408 and applied to the OR gate 398 to generate the input buffer read signal (-INBUFRD).
The address decoder 370 is illustrated in FIG. 14. The 4×16 decoder 370 includes four address inputs A2, A1 and A0 as well as an enable input (available at the output of the NOR gate 389) to provide sixteen outputs SEL0-SEL15. As previously discussed, the lower nibble of the internal address bus SPA [3:0] is applied to the address inputs A3, A2, A1 and A0. The enable input is connected to the output of the NOR gate 389 which indicates an address range between 0000H and 000FH. Sixteen select outputs are provided SEL0-SEL15 which are active low. The select outputs, (-SEL0) to (-SEL15), are available at the output of NAND gates 410 through 440.
The four by sixteen address decoder 370 also includes a buffer 442 and four inverters 444, 446, 448 and 450. The enable signal is applied to the input of the buffer 442. A buffer enable signal (BENABLE), available at the output of the buffer 442, is applied to the inputs of each of the NAND gates 410 through 440. The address inputs A3, A2, A1 and A0 are applied to various of the NAND gates 410 through 440 as well as to inverters 444, 446, 448 and 450 as shown in FIG, 14. The outputs of the NAND gates 410 through 440 are select inputs (-SEL0) to (-SEL15) which are used to form various read and write signals as well as address control signals as previously discussed.
Communication between the CPU and the SCP 26 is by way of an input buffer 362, the output buffer 364, a status register 366 and an auxiliary output buffer as illustrated in FIG. 15 and discussed below. The input buffer 362 is an eight bit register comprised of flip-flops 452, 454, 456, 458, 460, 462, 464 and 466. This eight bit register 362 is write only to the CPU and address 60H or 64H and is read only to the SCP 26. More specifically, the CPU system data bus (SD [7:0]), which is connected to the internal system data in bus SDIN [0:7] by way of pins 4, 5, 8, 9, 26, 27, 30 and 31, is applied to D inputs of the flip-flops 452, 454, 456, 458, 460, 462, 464 and 466 in order to enable the CPU to write to the input buffer 362. Data is clocked into the flip-flops 452, 454, 456, 458, 460, 462, 464 and 466 by an input buffer clock signal (-IBCLK). More specifically, the input buffer clock signal (-IBCLK) is applied to the clock (CP) inputs of the flip-flops 452, 454, 456, 458, 460, 462, 464 and 466. The input buffer clock signal (-IBCLK) is generated by ORing a CPU write signal (-IOW) with a system control processor chip select signal (-SCPCS), both active low, by way of an OR gate 468. These signals IO write (-IOW) and system control processor chip select (-SCPCS) are generated by the CPU whenever the CPU writes to the MKI 300. These signals are applied to pins 39 and 42 of the MKI 300.
An important aspect of the invention, as will be discussed below, relates to the availability of the MKI 300 to recognize a two byte sequence from the CPU for control of the Gate A20 signal without interrupting the SCP 26. This feature is available whenever the MKI 300 is placed in a MKI mode. When the MKI 300 is not in the MKI mode, the control of 30 the Gate A20 signal will be similar to the SCPI 28 which requires the SCP 26 to read the input buffer 362 and clear the input buffer full flag (IBF) for each of the bytes in the two byte sequence to control the Gate A20 signal. Except for control of the Gate A20 signal when the MKI feature is enabled as discussed above, any time the CPU writes to the input buffer, an input buffer full flag (IBF) is set and a command/data flag is set. The input buffer full flag (IBF) is provided by a pair of flip-flops 470 and 471. The input buffer clock signal (-IBCLK) is applied to the clock input (CP) of the flip-flop 470. An input buffer data signal INBUFDATA (FIG. 16) is applied to a D input of the flip-flop 470. As will be discussed below, the input buffer data signal (INBUFDATA) is under the control of a MKI enable signal (MKIEN) which only generates an input buffer data signal (INBUFDATA) when the MKI feature is disabled. The signal INBUFDATA indicates that the input buffer contains a byte which is either command or data. The input buffer data signal (INBUFDATA) is clocked into the input buffer full flag flip-flop 470 by the input buffer clock signal (-IBCLK). The output of the flip-flop 470 is applied to bit 1 of a status register output bus SRO [1] to indicate to the SCP 26 that a byte is contained in the input buffer 362. Once the system SCP 26 initiates a read of the input buffer 362 an input buffer output enable signal (-INBUFOE) is generated at the output of an OR gate 472. An input buffer read signal (-INBUFRD) is ORed with a reset signal by way of the OR gate 472 to generate the input buffer output enable signal (-INBUFOE). The input buffer output enable signal (-INBUFOE) is applied to an output enable input (OE) of the flip-flops 452-456 by way of inverters 474, 476, 478, 480, 482, 484, 486 and 488 to enable the outputs of the flip-flops 452 to 466 to be connected to the internal SCP address data output bus SCPADOUT [0:7], which, in turn, is applied to the SCP system data output bus SCPAD [0:7].
When the MKI feature is disabled, once the SCP 26 reads the data from the input register 362, the input buffer full flag (IBF) is cleared automatically by the MKI 300. More specifically, the input buffer output enable signal (-INBUFOE) is applied to a clock input of the flip-flop 471 whose D input is tied low. Thus, the input buffer output enable signal (-INBUFOE) clears the flip-flop 471 once the SCP 26 reads the byte from the status register 362. The Q output of the flip-flop 471 is applied to a clear input (CDN) of the flip-flop 470 to clear the input buffer full flag (IBF). In order to prevent the input buffer full flag (IBF) from being cleared prior to the SCP 26 reading the byte from the input buffer 362, the flip-flop 471 is preset by an input buffer clock signal (-IBCLK) which is applied to a preset (SDN) input of the flip-flop 490. This sets the flip-flop 471 to prevent the input buffer full flag (IBF) from being cleared until the SCP 26 reads the byte from the input register 362.
In addition to setting the input buffer flag (IBF), a command data flag (CMDATA) is also set whenever the CPU writes a byte to the input buffer 362. The command data flag (CMDATA) is used to set bit 3 of the status register 366 to indicate to the SCP 26 that the input register 362 contains either command or data. More specifically, an address bit SA2 from the CPU bus is used to decode whether the CPU wrote to address 60H or 64H. A write to 64H indicates a command while a write to 60H indicates data. The address bit SA2 will be high for 64H and low for 60H. This bit SA2 is applied to a D input of a flip-flop 492 which is used as a command data flag. This signal SA2 is clocked into the flip-flop 492 by the input buffer clock signal (-IBCLK) which is applied to the clock input (CP) of the flip-flop 492. The output of the flip-flop 492 indicates whether command or data was written by the CPU to the input buffer 362. This output is used to set bit 3 of the status register 366.
The output buffer 364 is an 8-bit register which includes the flip-flops 494 through 508. The output buffer 364 is read only to the CPU at address 60H and is written to by the SCP 26. The SCP 26 can also read the output buffer 364. The SCP internal address data bus SCPADIN [0:7] is applied to the D inputs of the flip-flops 494-508. The data on the bus SCPADIN [0:7] is clocked into the flip-flops 494, 508 by an output buffer clock signal (-OBUFCLK) which is applied to the clock inputs (CP) of the flip-flops 494 to 508. The output buffer clock signal (-OBUFCLK) is active low to enable the SCP 26 to write a byte to the output buffer 364 at address 0000H.
The flip-flops 494-508 also act as the Auxiliary Output Buffer when the SCP addresses 000DH. More specifically, an address decode signal (-00013) from the address decoder 370 is ORed with an SCP write signal (-SCPWR) by way of an OR gate 510 (FIG. 18). The output of the OR gate 510 indicates that the SCP 26 initiated a write to the address 000DH.
The flip-flops 494-508 are clocked by an output buffer clock signal (-OBUFCLK). More specifically, the output of the OR gate 510 is ANDed with an output buffer write signal (-OBUFWR) by way of an AND gate 512 which is active low any time the SCP writes to address 0000H. The output of the AND gate 512 is the signal output buffer clock signal (-OBUFCLK), which represents that the SCP 26 address either 0000H or 000DH.
Any time the SCP 26 writes to the output buffer 364, an output buffer full flag (OBF) is set in the status register 366. A pair of flip-flops 511 and 513 are used to set the output buffer full flag; bit 0 of the status register 366. The output buffer full flag (OBF) is set by the flip-flop 511. More particularly, an output buffer write signal (-OUTBUFWR) is applied to a clock input of the flip-flop 511. The D input of the flip-flop 511 is tied high. Thus, whenever the SCP 26 writes to the output buffer 364 the flip-flop 511 will be set indicating an output buffer full flag (OBF); which is tied to an internal status register bus bit SRO [0].
The MKI 300 also resets the output buffer full flag (OBF) whenever the CPU reads the byte in the output buffer 364. This is accomplished by the flip-flop 513. More specifically, the flip-flop 513 is set by the output buffer write signal (-OUTBUFWR) which is applied to the set input (SDN), The Q output of the flip-flop 513 is applied to a clear input (CDN) of the flip-flop 511. The D input of the flip-flop 513 is tied low. An enable data signal (-ENDATA) is applied to the clock input (CP) of the flip-flop 513. The enable data signal (-ENDATA) represents that the CPU has read the byte in the output buffer 364 at address 60H. More specifically an IO read signal (-IOR) which indicates that the CPU has initiated a read operation, is ORed with a CPU address signal A2 which is low for address 60H. These signals along with an SCPCS signal, which indicates that the CPU addressed either address 60H or 64H, are applied to an OR gate 514 along with a reset signal. The output of the OR gate 514 is applied to a buffer 516. The output of the buffer 516 is the enable data signal (-ENDATA) which indicates that the CPU has initiated a read to address 60H. This enable data signal (-ENDATA) is applied to the clock input (CP) of the flip-flop 513, whose D input is tied low in order to clear the flip-flop 513. Since the Q output of the flip-flop 513 is connected to the clear input (CDN) of the flip-flop 511, the flip-flop 511 can thus be cleared any time the CPU reads the byte from the output buffer 364.
The enable data signal (-ENDATA) is also used to control tristate devices 514 to 528, used to connect an internal output buffer bus OBO [0:7] to the Q output of the flip-flops 484 through 508 to the system data output bus SDOUT [0:7].
The SCP 26 can read the output of the output buffer 364 by way of tristate devices 537-551. More particularly, the Q outputs of the flip-flops 494-508 are tied to the internal SPADOUT [0:7] by way of the tristate devices 537-551. The tristate devices 537-551 are under the control of an output buffer read signal (-OUTBUFRD), a decode signal, available at the output of the OR gate 404 (FIG. 13), which indicates the SCP read address 0001H.
The status register 366 is an 8-bit register and includes the flip-flops 530, 532, 534 and 536. The status register 366 is read only to the CPU at address 64H and written to by the SCP 26. The SCP 26 can also read the status register 366 in order to determine the status of the output buffer full flag (OBF) and the command data flag (CMDATA). Five of the bits of the status register are written by the SCP 26 while three are generated by the MKI 300 (IBF, OBF) command data. The status register bit definition is provided in TABLE IX.
| TABLE IX |
| ______________________________________ |
| STATUS REGISTER BIT DEFINITION |
| ______________________________________ |
| Status Register Bit Definition: |
| Bit 7 Parity Error - Written by the SCP. |
| Bit 6 Receive Time-Out - Written by the SCP. |
| Bit 5 Transmit Time-Out - Written by the SCP when MKI |
| features are disabled. |
| Auxilliary Auxiliary Output Buffer Full - |
| Generated by the MKI when the MKI features are |
| enabled and the SCP writes to the Auxilliary |
| Auxiliary Output Buffer. |
| Bit 4 Inhibit Switch - Written by the SCP. |
| Bit 3 Command/Data - Generated by the MKI |
| This signal indicates whether the last byte written |
| by the CPU was a Command (written to address 64H) or |
| Data (written to address 60H). |
| Bit 2 System Flag - Written by the SCP. |
| Bit 1 Input Buffer Full - Generated by the MKI |
| This signal indicates when the CPU has written a |
| byte to the Input Buffer but the SCP has not yet |
| read the byte out of the latch. It can be used by |
| the CPU as a flag to indicate that the SCP is ready |
| to receive a byte. |
| Bit 0 Output Buffer Full - Generated by the MKI |
| This signal indicates when the SCP has written a |
| byte to the Output Buffer but the CPU has not yet |
| read the byte out of the latch. It can be used by |
| the SCP as a flag to indicate that the CPU is ready |
| to receive a byte. |
| ______________________________________ |
As noted in TABLE IX, the SCP 26 writes bits 2, 4, 6 and 7 to the status register 366 while bits 0, 1 and 3 are generated by the MKI 300. Bit 5 can either be written by the SCP or generated by the MKI depending on whether the MKI 300 is enabled. Accordingly, bits 2, 4, and 7 of the system control processor address data input bus SCPADIN [2, 4, 6, 7] are applied to the D input of the flip-flops 530, 532, 534 and 536. These bits are clocked into the flip-flops 530 through 536 by a status write signal (-STATUSWR). The status write signal (-STATUSWR) is a decoded signal from the address decoder 370 (FIG. 13) which indicates that the SCP is writing to the status register 366 at address 0001H. The Q output of the flip-flops 530, 532, 534 and 536 are applied to an internal status register output bus SRO [0:7]. As previously discussed, the input buffer full flag (IBF) from flip-flop 470 and the output buffer full flag (OBF) from the flip-flop 511 are applied to the status register output bus bits 0 and 1, respectively.
As indicated in TABLE IX, bit 5 is a dual function bit and is either written by the SCP 26 or generated by the MKI 300 depending upon whether the MKI feature is enabled. More specifically, when the MKI feature is disabled, the SCP 26 can write bit SRO[5] by way of bit SCPADIN [5], applied to D input of a flip-flop 537 (FIG. 15). This bit SCPADIN [5] is clocked into the flip-flop 537 by a status write signal (-STATUSWR). The status write signal (-STATUSWR) is a decode signal from the address decoder 370 and is active low whenever the SCP 26 writes to addressed address 0001H. The output of the flip-flop 537 is a status register bit 5 signal (SRB5), which is applied to an OR gate 539 (FIG. 18) to generate a status register output bit SRO [5], which, in turn, is applied to the internal status register bus SRO [0:7] (FIG. 15).
When the MKI feature is enabled the status register bit SRO [5] is generated by the MKI 300. More specifically, during such a condition, the status register bit SRO [5] is generated by a flip-flop 541 (FIG. 18), whose output is applied to the OR gate 539 to generate the bit SRO [5]as discussed above. A D input of the flip-flop 541 is tied high. The flip-flop 541 is clocked by the output of the OR gate 510 which indicates that the SCP 26 addressed the auxiliary output buffer by writing to address 000DH.
Since the status register 366 may be read by either the SCP 26 or the CPU, the status register output bus SRO [0:7] is connected to the system control processor address data output bus SCPADOUT [0:7] by way of tristate devices 538-552 and to the system data output bus SDOUT [0:7] by way of tristate devices 554-568. More particularly, the Q outputs of the flip-flops 530, 532, 4534 and 536 are applied to bits SRO [2, 4, 6, 7] respectively. The bits SRO [2, 4, 6, 7] are written by the SCP 26 as discussed above. The remainder of the bits (e.g., SRO [0, 1, 3, 5]) are generated by the MKI 300 as illustrated in TABLE IX. These bits SRO [0, 1, 3, 5] are available, as discussed below. More specifically, bit SRO [0] which indicates that the output buffer 364 is full, is available at the output of an OR gate 553 (FIG. 18). The OR gate 553 is a two input OR gate. One input is an output buffer full signal (OBF), available at the flip-flop 511 (FIG. 15). The output of the flip-flop 668 is applied to the other inputs which indicates that SCP wrote a byte to the output buffer 364. Bit SRO [5] is written by the SCP 26 when the MKI feature is disabled and generated by the MKI 300 when the MKI features are enabled. This bit SRO [5] is available at the output of an OR gate 555 (FIG. 15). The OR gate 555 is a two input OR gate. One input is a status register bit 5 signal (SRB 5), available at the output of the flip-flop 368 (FIG. 15) which indicates that the auxiliary output buffer full flag is set. This signal (SRB 5) is ORed with the output of a flip-flop 557 (FIG. 18) whose D input is tied high. The flip-flop 557 is clocked by the output of the OR gate 510 which indicates the SCP 26 addressed the auxiliary output buffer 368. The flip-flop 557 is cleared by an AND gate 557 which resets SRO [5] on system reset by an output buffer write signal (-OBUFWR), available at the output of an OR gate 400 (FIG. 13) which indicates that the SCP 26 initiated a write to the output buffer 364 at addressed 0000H. Bit SRO [3] is available at the output of the flip-flop 492, which indicates that a command/data byte was written by the CPU.
The tristate devices 538 to 552 are under the control of a status read signal (-STATUSRD) which is a decoded signal from the address decoder 370 which allows the SCP 26 to read the contents of the status register 66 at address 0007H, The tristate devices 554 to 568 are under the control of a status enable signal (STATEN). The status enable signal (STATEN) allows the CPU to read the contents of the status register 366 at address 64H. The status enable signal (-STATEN) is generated at the output of an OR gate 570, An SCP chip select signal (-SCPCS), which indicates that the CPU addressed either 60H or 64H, is applied to one input. An IO read signal (-IOR) is applied to another input along with an address decode signal which indicates that the address 64H was addressed, The output of the OR gate 570 as is applied to a buffer 572. The output of the buffer 572 is the enable data signal (-ENDATA).
The output buffer 364, status register 366, as well as the input buffer flag (IBF), output buffer flag (OBF), auxiliary output buffer flag (AOBF) and the command data flag (CMDATA) may all be reset by the CPU. More specifically, a reset signal (-RESET) available at the output of an inverter 74 is applied to the clear inputs (CDN) of the flip-flops 490, 512, 368 and 492 to reset the input buffer flag (IBF), output buffer flag (OBF), auxiliary output buffer flag (AOBF) and the command data flag (CMDATA), respectively. The reset signal (-RESET) is also applied to the clear input (CDN) of the flip-flops 494 through 508 to reset the output buffer 364 as well as to the clear input (CDN) of the flip-flops 530 through 536 to reset the status register (366) bits which are written by the SCP.
The Gate A20 signal is an active high output signal from the MKI 300 to allow the system to access memory above the 1 megabyte boundary. It can be set or cleared by both the CPU and the SCP 26. An important aspect of the invention relates to eliminating the need for an SCP interrupt for processing of the two byte sequence from the CPU to control the Gate A20 signal when the MKI 300 is enabled. Rather than interrupt the SCP 26 for the command byte D1 and the data byte, these bytes are decoded by the MKI 300 thus eliminating the need for processing by the SCP 26. By eliminating the need to interrupt the SCP 26 for the two byte sequence, the swithing switching of the Gate A20 signal is relatively faster with the SCPI 28.
The CPU can control the Gate A20 with a two byte sequence. The first byte is a command D1H written to the address 64H. The second byte is a data byte written to the address 60H. The MKI 300 will automatically set or clear the Gate A20 for the CPU unless this feature is disabled by the SCP 26, More specifically, the SCP 26 can disable the generation of the Gate A20 signal by the MKI 300 by writing to address A000CH. More specifically, bit SCPAD1, which is applied to the internal SCP address data bus SCPADIN .Badd.[8:7].Baddend..Badd.[0:7].Baddend., is used to control whether the automatic generation of the A20 signal is enabled or disabled. A "1" enables the feature, while a "0" disables the feature. The bit SCPADIN [1] is applied to a D input of a latch 576 (FIG. 13). A decoded address signal (-A000[12]), which indicates that the SCP has addressed 0000CH, is applied to one input of the OR gate 577. An SCP write signal (-SCPWR) is applied to the other input of the OR gate 577. The output of the OR gate 577 indicates that the SCP has written to address A000CH. If the bit SCPADIN [1] is a "1", an enable 20 signal (-ENA20) which is active low, will be available at the output of the latch 576. If the bit SCPADIN [1]is low the automatic generation of the Gate A20 signal will be disabled.
The command D1 is decoded by circuitry which includes a NOR gate 578, and two AND gates 580 and 582. The enable signal (-ENA20) is applied to the NOR gate 78 (FIG. 16). The system data bus SD [7:0], SD [7, 6, 4, 0] bits are applied to the AND gate 580 while the bits SD [5, 3, 2, 1] are applied to the NOR gate 578 along with the enable signal (-ENA20). The output of the NOR gate 578 as well as the output of the AND gate 580 is applied to a two input AND gate 582. The output of the AND gate 582 is a decode of the command D1.
The decoded D1 command signal from the AND gate 582 is applied to a command latch 584. This signal is clocked into the latch 584 by a command clock signal (-CMDCLK). The command clock signal (-CMDCLK) is available at the output of the OR gate 586. An SA2 signal is applied to one input of the OR gate 586. The SA2 signal indicates whether the CPU wrote to address 60H or 64H. The IB clock signal (-IBCLK) is applied to the other input of the OR gate 586. The IB clock signal (-IBCLK) indicates that the CPU initiated a write to the address 60H or 64H. The SA2 signal (-SA2) is available at the output of an inverter 586 (FIG. 15) which indicates that the CPU addressed 64H. The command clock signal (-CMDCLK) is applied to the clock input (CP) of the flip-flop 584 to latch the command signal D1 on the output. Circuitry, which includes a flip-flop 585 and AND gates 587 and 589 is used to reset the command latch 584. More specifically, the output of the AND gate 587 is applied to the clear input (CDN) of the command latch 584. The AND gate 587 is a three input AND gate. One input to the AND gate 587 is a signal, available at an output of an AND gate 608 which as discussed below, is active low during a reset and slow reset condition to reset the command latch during these conditions. The other input to the AND gate 587 is an output of an AND gate 589, which as will be discussed, indicates that the SCP 26 has taken control of the Gate A20 signal by writing to either address 000AH or 000BH. Lastly, a Q output of the flip-flop 585 is applied to the AND gate 587. The D input of the flip-flop 585 is tied low. The output of an OR gate 602 (discussed below) is applied to the clock input (CP) of the flip-flop 585 to clear the command latch 584 when a data byte is written by the CPU.
Bit 1 of the data byte, the second byte in the two byte sequence, determines the state of the Gate A20. The Gate A20 signal is set active if bit SDIN [1] is set and will be disabled if this bit is low. The MKI 300 will automatically set or clear the Gate A20 signal unless this feature is disabled by the SCP 26 at address 000CH. More specifically, the A20 Gate signal is available at the output of a latch 598. Bit 1 from the system data bus is applied by way of the system data internal bus SDIN [1] to the D input of the latch 598. Bit 1 is clocked into the latch by an A20 clock signal which is applied into the clock input (CP) of the latch 598. The A20 clock signal is available at the output of an OR gate 600. One input to the OR gate 600 is the output of an OR gate 602 which indicates that the CPU has written to either address 60H or 64H. More particularly, an SA2 signal is applied to one input of the OR gate 602. An IB clock signal (-IBCLK) is applied to the other input of the OR gate 602. The IB clock signal (-IBCLK) further indicates that the CPU has written to either 64H or 60H. The SA2 signal indicates that a command was written to 64H. The other input signal to the OR gate 600 is a (-COMMAND) signal from the latch 584 QN output. This allows the Gate A20 latch 598 to be set when the second data byte is written by the CPU.
The input buffer data signal (INBUFDATA) controls whether the input buffer full flag (IBF) is set when the CPU writes to the input buffer 364. As discussed below, the input buffer data signal (INBUFDATA) is under the control of a MKI enable signal (MKIEN). More specifically, when the MKI feature has been enabled, the input buffer data signal (INBUFDATA) will be inhibited such that the MKI 300 can process the two byte sequence from the CPU for the Gate A20 control without interrupting the SCP 26. When the MKI feature is disabled, the system processes the bytes, similar to SCPI 28, by setting an input buffer full flag (IBF) each time the CPU writes to the input buffer 364.
The input buffer data signal (INBUFDATA) is generated at the output of a NOR gate 588. The NOR gate 588 is a two input NOR gate. The output of an AND gate 590 is applied to one input while the output of another AND gate 592 is applied to the other input. When the MKI feature is disabled (e.g., MKIEN low), the outputs of the AND gates 590 and 592 will be low which, in turn, will enable the input buffer data signal (INBUFDATA). Thus, the input buffer flag (IBF) will be set each time the CPU writes to the MKI 300. When the MKI feature is enabled (MKIEN is set) one or the other of the AND gates 590, 592 will be high while the other is low causing the NOR gate 588 to be low. More specifically, a command byte D1 written by the CPU to address 64H will cause the output of the AND gate 592 to be high since the D1 input (from the AND gate 582), the SA2 input (indicating a CPU write to address 644) and the MKI enable signal (MKIEN) to the AND gate 592 will all be high during this condition. However, the (-SA2) input to the AND gate 590 will cause the output of the AND gate 590 to be low and, thus the output of the NOR gate 588 to be low, which, in turn, disables the input buffer flag (IBF). Similarly, when the data byte is written by the CPU, the AND gate 590 will be high and the AND gate 592 will be low, disabling the input buffer data signal (INBUFDATA).
The MKI enable signal is available at the output of a latch 594. This signal MKIEN is active high and is applied to the inputs of the AND gates 590 and 592. When the MKI enable signal is low this will disable the AND gates 590 and 592 such that the input buffer data signal will be active during the command/data two byte sequence.
The MKI enable signal MKIEN is controlled by the SCP 26. More specifically, the SCP 26 can write to address 000FH to either enable or disable the MKI enable latch 594. Bit SCPAD [0] of the SCP address data bus, which is applied to the internal SCP address data bus SCPADIN [0], controls whether the MKI 300 is enabled or disabled. If SCPADIN [0] is 1, the MKI enable (MKIEN) is set. When the SCP 26 writes a 0 to SCPADIN [0] the MKI feature is disabled. The SCPADIN [0] is applied to the D input of the latch 594. A decode signal, available at the output of an OR gate 596 is applied to the clock inputs (CP) of the address latch 594. A decode signal (-a00015) from the address decoder 370 applied to one input of the OR gate 596 along with an SCP write signal (-SCPWR). The output of the OR Gate 596 will indicate any time the SCP 26 initiates a write to the address 000FH.
The SCP 26 can also control the Gate A20 signal by writing to either address 000AH or 000BH. More particularly, an address decode signal (-A00010) from the address decoder 370 indicates that the SCP address A00AH address is applied to one input of a two input OR gate 604 along with an SCP write signal (-SCPWR). The output of the OR gate 604 is applied to a clear input (CDN) of the A20 latch 598 to force the Gate A20 signal low or inactive. The SCP can also force the Gate A20 signal high by writing to address A00BH. More specifically, a decoded address signal A000 [11] which indicates that the SCP 26 wrote to the address A00BH is applied to an OR gate 606 along with an SCP write signal (-SCPWR). The output of the OR gate 606 is applied to a preset input of the A20 latch 598 by way of an AND gate 606.
In order to initialize the MKI 300 during a reset or slow reset condition a reset (-RESET) is applied to one input of the AND gate 608 by way of a buffer 610. A slow reset signal (-RC), discussed below, is applied to the other input. The output of the OR gate 608 sets the Gate A20 signal (a20gate) high on reset and slow reset.
The SCP 26 can also read the status of the Gate A20 latch 548 by reading address A000AH. More particularly, the output of the Gate A20 latch 598 is applied to the system control processor address data output bus SCPADOUT [1] by way of a tristate device 611 to enable the SCP 26 to read the status of the Gate A20 signal. The tristate device 611 is under the control of an A20 read signal (-A20RD) which is available at the output of an OR gate 612. The OR gate 612 is a two input OR gate. One input is from the SCP read signal (-SCPRD). The other input is a decoded address signal (-A00010) from the address decoder 370 which indicates that the SCP wrote to address A000AH.
IRQ1 is an active high output signal that informs a CPU that the output buffer is full. It can be enabled by either the SCP or the CPU. The default on reset is disabled. When the MKI feature is enabled, the CPU can enable/disable the IRQ1 with a write output port command. More specifically, the write output port command is the two byte sequence by the CPU when the CPU writes a command D1 to the input buffer 362 at address 64H followed by a byte of data to the input buffer at address 60H. The data byte is used to control the CPU interrupt IRQ1 when the output buffer is full as well as control the setting of the Gate A20 signal. TABLE X indicates the bit definitions for the data byte.
| TABLE X |
| ______________________________________ |
| WRITE OUTPUT COMMAND DATA BIT DEFINITIONS |
| ______________________________________ |
| Bit 7 Keyboard data (output) |
| Bit 6 Keyboard clock (output) |
| Bit 5 Input Buffer Empty |
| Bit 4 Output Buffer Full |
| Bit 3 Reserved |
| Bit 2 Reserved |
| Bit 1 Gate A20 |
| Bit 0 System Reset |
| ______________________________________ |
The CPU interrupt IRQ1 is available at the output of an AND gate 613. One input to the AND gate 613 is an output buffer flag (OBF) available from the flip-flop 510 (FIG. 15). The other input to the AND gate 613 is an enable IRQ1 signal (ENIRQ1). The enable signal (ENIRQ1) is available at the output of the latch 614. As indicated in TABLE X, bit SDIN [4], which indicates that the output buffer is full, is used to control the enablement of the interrupt signal (IRQ1). This bit SDIN4 is applied to the D input of the latch 614 and is clocked into latch 614 by the output of an OR gate 616 applied to the clock (CP) input. One input to the OR gate 616 is from the QN output of the latch 594 which indicates that the MKI feature is disabled. This signal (-MKIEN) enables the interrupt IRQ1 when the MKI feature is disabled. The other input to the OR gate 616 is the output of the OR gate 600 which is used to clock the A20 signal.
The interrupt IRQ1 can also be controlled by the SCP 26. More specifically, the SCP can write to address 0005H to enable or disable IRQ interrupt. More particularly, a decode signal A0005 is applied to an OR gate 618 along with an SCP write signal (-SCPWR). The output of the OR gate 618 indicates that the SCP has written to address A005H. The output of the OR gate 618 is applied to the clock input of latches 620 and 622. The latch 620 is used to enable the IRQ1 interrupt while the latch 622 is used to disable it. More particularly, a QN output of the latch 620 is applied to a preset input of the latch 614 while the Q output of the latch 620 is applied to the clear (CDN) input of the latch 614 by way of an AND gate 624 wherein the output of the latch 614 is ANDed wigh with a reset signal which causes the latch 614 to be reset during a system reset by the CPU. An AND gate 625 is used to preset the latch 622 and clear the latch 620. The AND gate 625 is a two input AND gate. A reset signal (-RESET) is applied to one input to clear the interrupt IRQ1 during a reset condition. The other input to the AND gate 625 is the output of the OR gate 616 which clears the latch 620 when the command byte is written, as long as the MKI feature is enabled.
Bit SCPAD [0] is used to enable or disable the IRQ1 interrupt. This bit SCPAD [0] is applied to the D input of the latches 620 and 622 by way of the internal SCPA address data bus SCPADIN [0]. If SCPAD [0]equals 0 then the interrupt IRQ1 is enabled. Otherwise the interrupt is disabled.
The slow reset signal (-RC), illustrated in FIG. 17 is an active low output signal to reset the CPU. It can be set by the CPU or set and cleared by the SCP 26. It is cleared when the MKI 300 is reset by the reset pin.
The SCP 26 can gain control of slow reset through the memory map. A write to location 0008H forces the slow reset signal active while a write to address 0009H forces the slow reset signal inactive. More specifically, the decoded address signals A0008H and A0009H from the address decoder 370 are applied to OR gates 630 and 632 and ORed with an SCP write signal (-SCPWR). The output of the OR gate 630 is applied to a clock input of a flip-flop 634 whose D input is grounded. The Q output of the flip-flop 634 is applied to a clear input (CDN) of a flip-flop 636. The output of the flip-flop 636 is a slow reset signal (-RC). Thus, any time the SCP 26 writes to address A008H A0008H, the output of the flip-flop 634 will go low which in turn clears the flip-flop 636 to generate the active low slow reset signal (-RC).
An SCP 26 write to address 0009H forces the slow reset signal to go inactive. More specifically, the output of the OR gate 632 is ANDed with a system reset signal (-RESET) by way of the AND gate 638 which allows the SCP to clear the system reset signal and additionally allows the slow reset signal to be cleared on system reset. The output of the AND gate 638 is applied to a preset input (SDN) of the flip-flop 634 as well as to an AND gate 640. Thus, any time the SCP 26 writes to address 0009H or there is a reset signal from the CPU, the flip-flop 634 will be preset. This causes the QN output from the flip-flop 634 to be low which is ORed with an input buffer read signal in an OR gate 642. The output of the OR gate 642 is applied to the other input of the AND gate 640 whose output is applied to a preset input of the flip-flop 636.
The SCP 26 can also read the status of the slow reset signal by initiating a read to address 0008H. More particularly, an SCP read signal (-SCPRD) is ORed with a decoded address signal (-A0008) by way of the OR gate 642. The output of the OR gate forms a read RC operate enable signal 642. This control signal (-RDRCOE) is used to control a tristate device 644 which is connected to the Q output of the flip-flop 636 on one end and to the system control processor address data output bus bit SCPADOUT [0].
The CPU can also set the slow reset signal active with a signal command write. More particularly, reset is set active by the CPU when an even byte between FO and FE is written to address 64H. The circuitry which includes the NAND gate 646 and the inverter 648 decodes even bytes between FOH and FEH. More particularly, the internal system data bus internal bits SDIN [7:4] are applied to inputs of the NAND gate 646. These bits will all be high for the addresses FOH through FEH. Bit SDIN [0], which is low for even bytes between OF and FE as applied to the inverter 648 whose output in turn is applied to the NAND gate 646.
Two interlock signals are also applied to the NAND gate 646 to disable the slow reset (-RC) during certain situations. First, the SCP can disable the slow reset feature by writing to address 000CH. More particularly, the decoded address signal A00012, available at the output of an OR gate 576 (FIG. 13) which indicates an SCP write to address 000CH, is applied to a clock input of a latch 650 (FIG. 13). Bit 0 of the SCP internal address data bus is used to either enable or disable the slow reset. Thus, bit SPADIN0 SCADINO is applied to the D input of the latch 650. If bit SCPADIN [0] equals 1, the slow reset will be enabled while a 0 will disable the slow reset. The QN output of the latch 650 is an enable RC signal (ENRC) which is applied to one input of the AND gate 646 (FIG. 17) by way of an inverter 652 to either enable or disable the slow reset signal.
To accommodate an established firmware unlocking scheme to enable the slush, the automatic setting of the slow reset signal by the CPU write of a command F even is disabled for one command write after the command B8 is written by the CPU. The slush enable consists of a four byte sequence, the first two bytes being B8 and F8. The MKI 300 will thus disable the automatic generation of the slow reset signal for one command byte after it receives a command byte B8. The circuitry for decoding the command byte B8 includes the AND gate 654, the inverters 656, 658, 660, 662 and the latch 664. For the command byte B8, bits SDIn [6, 2, 1, 0] will be low. These bits are applied to the inverters 656, 658, 660 and 662. The output of the inverters 656, 658, 660 and 662 are applied to the AND gate 654. The bits SDIN [7, 5, 4, 3], which are high for the command signal B8, are also applied to the inputs of the AND gate 654. The output of the AND gate 654 represents a decoded B8 command signal which is applied to a D input of the latch 664. The command clock signal (CMDCLK) is used to clock the flip-flop 664. As previously discussed, this signal indicates that the CPU wrote to address 64H. Thus, the QN output of the latch 664 will indicate that the byte B8 was written to the address 64H by the CPU. This output is applied as a permissive to the NAND gate 646. The output of the NAND gate 646 is applied to a D input of a latch 636 while the command clock signal (-CMDCLK) is applied to the clock input CP to enable the CPU to control the slow reset signal unless this feature has been disabled by the SCP or the command byte B8 has been received by the system. After the SCP reads the byte from the input buffer the slow reset signal is cleared. The flip-flop 664 is also reset on system reset.
The MKI 300 allows a type PS/2 mouse to be interfaced with the SCP 26 by way of an auxiliary device connector (e.g., a 6-pin mini DIN connector). Data from the mouse is sent by the SCP 26 to the CPU by way of the output buffer 364. This data sets the output buffer full bit of the status register 366 just like normal data from the SCP 26 and additionally sets the auxiliary output buffer full flag (e.g., bit of the status register 366). When enabled, an IRQ12 interrupt is set by an auxiliary output full flag (MOBF). When the output buffer 364 is read by the CPU, output buffer full signal is cleared; however, the auxiliary output buffer full signal (MOBF) is left active until the SCP 26 writes a non-mouse byte to the output buffer 364.
The interrupt IRQ12, an interrupt to the CPU for type PS/2 mouse, is available at the output of an AND gate 666 (FIG. 19) (FIG. 18). This interrupt IRQ12 will be enabled unless it is disabled by the SCP or the MKI is disabled. More particularly, a mouse output buffer full flag (MOBF) is applied to one input of the AND gate 666. The mouse output buffer full flag (MOBF) is generated by circuitry which includes the flip-flop 668 and 670. Any time the SCP 26 writes to the auxiliary output buffer at address 000DH the flip-flop 670 will be set by way of the output of the OR gate 510. This signal is also applied to a clock input of the flip-flop 668 whose D input is tied high to generate the mouse output buffer full flag at the Q output of the flip-flop 668. After the CPU reads the status register 366, an enable data signal (-ENDATA) clears the mouse output buffer full flag (MOBF). More particularly, the enable data signal (-FNDATA) is applied to the clock input (CP) of the flip-flop 670. The D input is tied low. The Q output of the flip-flop 670 is applied to the clear input (CDN) of the flip-flop 668. Thus, as the CPU readsthe status register 366, the output of the flip-flop 670 will go low and, in turn, clear the mouse output buffer full flag which is tied to one input of the AND gate 666.
The SCP 26 can disable the interrupt IRQ12 by writing to address 000EH. Thus, a decoded output signal A000 [14], which indicates a SCP write to the address A000EH, is ORed with a SCP write signal by way of an OR gate 672. The output of the OR gate 672 is applied to a clock input (CP) of an enable latch 674. Bit 1 of the SCP address data bus is used to control whether the interrupt IRQ12 is enabled or disabled. More specifically, SCPAD [0] equal "1" will enable the interrupt, while SCPAD [0] equal "0" will disable the interrupt. Thus, the SCAPDIN SCAPADIN [0] is applied to the D input of the flip-flop 674. The Q output of this flip-flop 674 is applied to the AND gate 666 to either enable or disable the interrupt IRQ12, depending on the status of the bit SCPAD0. The flip-flop 674 is reset by system reset.
The circuitry also supports a suspend resume feature whereby certain data may be read back by the SCP 26 should the processing be suspended. The signal command, ENIRQ1, ENIRQ12, MOBF, AOBF and MKIEN are applied to tristate devices 676 through 686. Two unused tristate devices 688 to 690 are tied to ground. The output of these tristate devices 676-690 are applied to the system control processor address data output bus SCAPOUT SCPADOUT [0:7]. The tristate devices 676-690 are under the control of the signal enable flip-flop status (-ENFESTS). This signal (-ENFFSTS) is available at the output of an OR gate 692. A SCP read signal (-SCPRD) is ORed with a decoded address signal A000 [13] to enable these bits to be read any time the SCP reads to address 000DH.
Obviously, many modifications and variations of the present invention are possible in light of the above teachings. Thus, it is to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically designated above.
| ______________________________________ |
| APPENDIX |
| STATE EQUATIONS FOR STATE MACHINE |
| ILLUSTRATED IN FIG. 8 |
| ______________________________________ |
| COMMAND CHANGE 0 TO 1 |
| S0 + CMD = D1 OR |
| S2 + CMD = D1 |
| COMMAND CHANGE 1 TO 0 |
| S6 + INBUFRD OR |
| S5 + INBUFRD OR |
| RESET (NOTE MAYBE S4 + RESET) |
| OR |
| ACP CLR A20 = 0 OR |
| SCP SET A20 = 1 OR |
| S4 + CMD ≠ D1 OR |
| S7 + CMD ≠ D1 OR |
| RC RESET |
| A20 CHANGE 0 TO 1 |
| S4 + DATA = 1 OR |
| SCP SET A20 = 1 |
| A20 CHANGE 1 TO 0 |
| S7 + DATA = 0 OR |
| RESET OR |
| SCP CLR A20 ≠ 0 OR |
| RC RESET |
| DUMMY CHANGE 0 TO 1 |
| S2 + CMD = D1 OR |
| S4 + DATA = 0 |
| DUMMY CHANGE 1 TO 0 |
| S7 + CMD = D1 OR |
| S5 + INBUFRD OR |
| RESET OR |
| RC RESET OR |
| S7 + DATA = 1 |
| ______________________________________ |
Delisle, David J., Fakhruddin, Saifuddin, Kohtz, Robert A., Gauthier, Lloyd
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