Voltage storage circuits

Abstract

A voltage storage circuit, for use for example in an analogue-to-digital converter, includes an input switch element connected between an input node (IN) of the circuit and a first plate of a storage capacitor. The other plate of the capacitor is connected to a common terminal 3 of the circuit. A high-impedance amplifier element is connected to the first plate for providing at an output node (OUT) of the circuit an output voltage (V_o) dependent upon the first plate potential (V_c). The amplifier element has an FET input device whose gate electrode is connected to the first plate and whose source and drain electrode potentials are fixed in relation to the first plate potential (V_c). Such a voltage storage circuit avoids charge injection to/from the amplifier element, with consequential charging/discharging of the storage capacitor, which would otherwise result from operation of the amplifier element

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to voltage storage circuits for use, for example, in analog-to-digital converters for storing an applied analog value prior to conversion into its digital equivalent.

2. Description of the Prior Art

FIG. 1 of the accompanying drawings shows a previously-considered voltage storage circuit comprising an input switch element 1, a storage capacitor 2 and a high-impedance unity-gain amplifier element 3. Initially, with the switch element 1 in the closed position, an analog input voltage V_i applied between input terminals of the circuit is supplied to the storage capacitor 2 so that the potential difference between the plates of the storage capacitor tracks the input voltage V_i. At a predetermined moment in time t_switch the input switch element 1 is switched to the open position, with the result that the potential difference between the capacitor plates immediately prior to such switching is stored until such time as the input switch element 1 is closed again. During the period in which the switch element is in the open position the stored voltage is reproduced between output terminals of the circuit as an output voltage V_o, the amplifier element 3 serving to prevent loading of the storage capacitor by circuitry connected with the output terminals.

FIG. 2 shows an input portion of the amplifier element 3 in more detail. This input portion includes an FET input transistor 33 having a drain electrode connected to a positive supply line V_dd of the element, a source electrode connected by way of a current source 32 to a negative supply line V_ss of the element, and a gate electrode connected to one plate (the upper plate in FIG. 1) of the storage capacitor 2. It will be appreciated that the FET input transistor 33 is connected in the so-called source follower configuration.

Further circuitry, not shown in FIG. 2, is normally interposed between the source electrode of the FET input transistor 33 and an output of the element for buffering the source electrode potential to produce the output potential V_o.

In use of the amplifier element 3 of FIG. 2, the current source 32 causes a current to flow in the drain/source channel of the FET input transistor 33, with the result that the source electrode potential V_s thereof follows the gate electrode potential and hence the stored potential V_c of the upper plate of the storage capacitor 2. Thus, the input portion of the amplifier element 3 has a voltage gain of substantially unity, although in practice the source electrode potential V_s is always slightly less than the potential V_c of the upper plate of the storage capacitor 2.

Because the input portion employs an FET input transistor the gate current of which is very small, the input impedance of the element is very high. Thus, after the input switch element 1 of the voltage storage circuit of FIG. 1 has been opened, the storage capacitor is not discharged to a significant extent by the amplifier element 3.

The amplifier element 3 of FIG. 2 suffers, however, from a disadvantage arising from charge injection into its input portion from the storage capacitor 2 (or vice versa) when the potential of the upper plate V_c of the storage capacitor 2 is changed. Although after the input switch element 1 has been opened, no such change in the upper plate potential will normally result, as explained later in the present specification the upper plate potential V_c unavoidably changes at the moment t_switch of opening of the input switch element 1 due to charge injection at that moment by the input switch element 1 itself. Such charge injection by the input switch element 1 leads to a small, but at high precision significant, change in the stored voltage in the storage capacitor 2 and hence brings about a change in the potential V_c of the upper plate thereof at the moment the switch element is opened.

The reasons for charge injection at the amplifier element input portion, in response to changes in the upper plate potential of the storage capacitor 2, will now be explained. As shown in FIG. 2, the FET input transistor 33 unavoidably has small parasitic capacitances between its electrodes, there being a gate-source parasitic capacitance C_gs between the gate and source electrodes, a gate-drain parasitic capacitance C_gd between the gate and drain electrodes, and a drain-source parasitic capacitance C_ds between the drain and source electrodes. Whenever the potentials of these three electrodes change relative to one another, charge must flow into or out of the parasitic capacitances, and it is the combination of these charge flows which leads to charge injection to/from the amplifier element input portion.

In the FIG. 2 amplifier element, because the input transistor 33 is connected in the above-mentioned source follower configuration, the gate-source potential thereof is substantially constant, irrespective of the upper plate potential V_c of the storage capacitor 2, so that charge injection due to the gate-source parasitic capacitance C_gs can normally be neglected.

However, the gate potential and the drain-source potential of the input transistor 33, being V_dd -V_c and V_dd -V_s respectively, are not constant and vary in dependence upon the upper plate potential V_c. Thus, whenever V_c is changed, charge must flow into or out of the gate-drain parasitic capacitance C_gd and the drain-source parasitic capacitance C_ds, in either case causing charge to flow into or out of the input portion of the amplifier element.

When the input switch element is open, the charge that flows must either charge or discharge the storage capacitor 2, depending upon the direction of flow. Such charge or discharge unavoidably leads to an error in the stored voltage between the plates of the storage capacitor 2.

The effects of the parasitic capacitances of the input portion of the amplifier element are particularly severe when the capacitance of the storage capacitor 2 is not large relative to the capacitances of the parasitic capacitances themselves, which may be the case for example when it is desired to reduce acquisition time of the voltage storage circuit.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention there is provided a voltage storage circuit including:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, an input signal to be stored being applied between the said input and common terminals when the circuit is in use; and

in amplifier element, having an input connected to the said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between the said output and common terminals, dependent upon the voltage stored in the said storage capacitor, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the device and also having a control electrode to which a potential is applied to control the magnitude of current in the said current path, the said control electrode being connected to the said one plate, and the said first and second current-path electrodes being connected with potential tracking means such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in the said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of the said one plate.

With such a design of amplifier element, the potentials of the control and first and second current-path electrodes of the input device are all in substantially fixed relation to one another and to the one plate potential when the circuit is in use, so that the parasitic capacitances existing between those electrodes do not significantly affect operation of the circuit. This avoids charge injection to/from the amplifier element, with consequential charging/discharging of the storage capacitor, due to operation of the amplifier element connected to the said one plate of the storage capacitor. Thus, error in the stored voltage as a result of such charging/discharging is eliminated.

Preferably the potential tracking means include a current source, connected to the said first current-path electrode for causing the first current-path electrode potential to track the control electrode potential, and active follower means connected operatively between the said first and second current-path electrode for causing the second current-path electrode potential to track the first current-path electrode potential.

In such an arrangement the first current-path electrode is caused to track the one plate potential automatically, so that the active follower means can be connected operatively between the first and second current-path electrodes, i.e. exclusively on the output side of the input device, to achieve the required tracking of the second current-path electrode.

The said electronic input device is advantageously an FET input transistor such that the said control electrode is the gate electrode of the FET input transistor, the first current-path electrode is the source electrode of the FET input transistor, the said second current-path electrode is the drain electrode of the FET input transistor, and the said controllable current path is provided by the drain-source channel of the FET input transistor.

Such an FET input transistor provides the amplifier element with a high input impedance, so as to avoid discharge of the storage capacitor after the input switch element has been opened, the inevitable gate-source, gate-drain, and source-drain parasitic capacitances of the FET input transistor not affecting the circuit operation.

When the input device is an FET, the said active follower means may comprise a cascoding FET transistor connected with its drain-source channel in series with the drain-source channel of the FET input transistor so that the source electrode potential of the cascoding transistor tracks the gate electrode potential thereof and also comprise a bias generator connected operatively between the source electrode of the FET input transistor and the gate electrode of the cascading transistor for maintaining therebetween a substantially constant potential difference.

Such a cascoding arrangement is simple but effective, the series-connection of the cascoding FET transistor with the FET input transistor ensuring that the source electrode potential of the cascading transistor automatically tracks the gate electrode thereof.

The amplifier element is preferably made up of first and second substantially identical circuit portions, the first portion including the said input device and the said active follower means and the second portion including the said current source.

Such circuit symmetry can provide high stability and predictability in the operation of the amplifier element, particularly as regards the relationship between the input and output potentials of the amplifier element, and can be conveniently fabricated.

The said input switch element is preferably an electronic input switch element, operative in dependence upon the potential at a switching electrode thereof, the circuit further including switch driving means connected to cause the switching electrode potential to track the input terminal potential when the element is in its ON condition, thereby maintaining the switching electrode potential substantially fixed in relation to the input terminal potential, and operable to cause the switching electrode potential to change, relative to the input terminal potential, such that the element is changed from its ON condition to its OFF condition.

In such a circuit the control electrode potential is fixed in relation to the input term potential, so that the amount of charge injected in the electronic switch element at the moment of switching OFF is substantially independent of the level of the input signal. Thus, error in the stored voltage due to such charge injection is substantially constant, or at least linear, for different input signal voltages, and appropriate measures can therefore be taken to compensate for such error.

The said switching electrode potential is advantageously derived from the said output signal so that this potential can be obtained without loading or otherwise affecting the input signal.

Advantageously, the said switch driving means are connected operatively with the said output terminal and are operable, in dependence upon a switching signal received thereby, to apply to the said switching electrode either an ON potential, for maintaining the said input switch element in its ON condition, or an OFF potential, for maintaining the said input switch element in its OFF condition, the said ON and OFF potentials being each substantially fixed in relation to the said output terminal potential but differing from one another by a predetermined amount.

In this arrangement both the ON and OFF potentials are fixed relative to the input signal potential so that the charge injection by the input switch element is substantially constant irrespective of the input signal potential.

The voltage storage circuit may well have respective first and second biassing lines connected operatively to the said output terminal so as to be at potentials that are respectively fixed in relation to the output terminal potential, the second biassing line potential being equal to one of the said ON and OFF potentials and the potential difference between the said first and second biassing lines being greater than or equal to the said predetermined amount. In this case the said switch driving means may include a bootstrap capacitor one plate of which is connected to the said switching electrode for providing the said switching electrode potential and also include connecting means connected with both plates of the bootstrap capacitor and with the said biassing lines and switchable, when the switching electrode potential is to be changed from the said one of its ON and OFF potentials to the other of those potentials, from a charging configuration, serving to connect the said one plate of the bootstrap capacitor to the said second biassing line whilst connecting the other plate thereof to the said first biassing line, to a floating configuration serving to isolate the said one plate from the second biassing line whilst connecting the said other plate to the said second biassing line, thereby to cause the potential at the said one plate to be changed from the second biassing line potential to a potential differing therefrom by the said predetermined amount.

In such an arrangement one of the ON and OFF potentials can be outside the supply lines of the circuit, if necessary.

Alternatively, the voltage storage circuit may have respective first, second and third biassing lines connected operatively to the said output terminal so as to be at potentials that are respectively fixed in relation to the output terminal potential, the third biassing line potential being equal to one of the said ON and OFF potentials and the potential difference between the said first and second biassing lines being greater than or equal to the said predetermined amount. In this case the said switch driving means may include a bootstrap capacitor one plate of which is connected to the said switching electrode for providing the said switching electrode potential and also include connecting means connected with both plates of the bootstrap capacitor and with the said biassing lines and switchable, when the switching electrode potential is to be changed from the said one of its ON and OFF potentials to the other of those potentials, from a charging configuration, serving to connect the said one plate of the bootstrap capacitor to the said third biassing line whilst connecting the other plate thereof to the said first biassing line, to a floating configuration serving to isolate the said one plate from the third biassing line whilst connecting the said other plate to the said second biassing line, thereby to cause the potential at the said one plate to be changed from the third biassing line potential to a potential differing therefrom by the said predetermined amount.

In this example, the required change in the 31 56 and 56 57 and voltage adjustment means 58.

In each stage ST_i, the switch elements 51 to 56 54, 56 and 57 can be in either the above-mentioned input configuration (switch elements 51 to 54 in the ON condition whilst switch elements 55 56 and 56 57 are in the OFF condition) or in the output configuration (switch elements 55 56 and 57 57 in the ON condition whilst switch elements 51 to 54 are in the OFF condition).

As in the case of the voltage doubling circuitry 50 of FIG. 11, the switch elements 51 to 54, 56 and 57 of each stage ST_i are controlled by control signals φ₁ and φ₂. However, in the ADC of FIG. 12 control means 60' common to all the stages are provided for generating the first and second control signals of each stage and, when φ₁ is active the switch elements 51 to 54, 56 57 of the odd-numbered stages ST₁, ST₃, ST₅, . . . are maintained in the input configuration whilst the switch elements 51 to 54, 56 57 of the even-numbered stages ST₂, ST₄, ST₆, . . . are maintained in the output configuration, and vice versa when φ₂ is active.

Each voltage conversion stage ST_i also includes comparator means 70 connected to the first and second input nodes I₁ and I₂ of the stage for receiving the input voltage V_i applied to the stage and also connected to receive the above-mentioned comparison potential V_r /4. The comparator means 70 provide at the output thereof three-state logic digital data a (+1, 0, -1), serving as the digital output of the stage, in accordance with Table 2 above. The digital data of each stage is applied to data processing means 80 for processing to produce a digital output word. The digital data a is applied also to the voltage adjustment means 58 for controlling operation thereof.

The voltage adjustment means serve, when the switch elements 55 56 and 57 are ON, to apply between the respective common terminals COM₁ and COM₂ of the voltage storage circuits of the stage an offset voltage V_os selected, from one of three different possible voltages, by the digital data a produced by the comparator means. In the case in which a=+1 (corresponding to the case in which V_r /4≦V_i,) the selected offset voltage V_os =-V_r. When a=0 (corresponding to the case in which -V_r /4≦V_i <V_r /4) the selected offset voltage V_os= 0. When a=-1 (corresponding to the case in which V_i <-V_r /4) the selected offset voltage V_os =+V_r.

In operation of the ADC shown in FIG. 12, an analog input voltage V_i1 to be digitised is applied between the first and second input nodes I₁ and I₂ of the first voltage conversion stage ST₁. Initially, the control means 60' activates the control signal φ₁, so that the first voltage conversion stage ST₁ is maintained in the input configuration (switch elements 51 to 54 thereof ON). In this configuration the switch elements 55 and 56 and 57 are both maintained in the OFF condition, so that the voltage adjustment means 58 are isolated from the rest of the circuitry.

While φ₁ is active the comparator means 70 of the first stage ST₁ compare the applied input voltage V_i with the comparison potential V_r /4 and produce three-state logic digital data a in dependence upon the result of the comparison.

Before the end of the period during which φ₁ is active, the switching signal CK is applied by the control means 60' to each switch driving device 4,5 of the first stage ST₁ to cause the respective switch elements 1 of the voltage storage circuits VSC₁ and VSC₂ of the stage ST₁ to be switched OFF, with the result that the input voltage V_i1 the first stage ST₁ is stored in each of the respective storage capacitors 2 of those circuits.

The control means 60' then deactivates φ₁ and activates φ₂ to switch the first stage ST₁ to the output configuration. In this configuration, the switch elements 51 to 54 of the stage are in the OFF condition, and the switch elements 55 and 56 and 57 of the stage are in the ON condition. The voltage adjustment means 58 are therefore connected in series between the respective storage capacitors 2 of the voltage storage circuits VSC₁ and VSC₂, so that the selected offset voltage V_os (-V_r, 0, +V_r depending on the digital data a) is applied between the respective common terminals COM₁ and COM₂ of the voltage storage circuits VSC₁ and VSC₂. Thus, an analog conversion voltage V_c is produced between the first and second output nodes O₁, O₂ of the stage ST₁ which differs from double the stored input voltage V_i1 by the selected offset voltage V_os applied between the respective common terminals COM₁, COM₂ of the voltage storage circuits VSC₁ and VSC₂ by the voltage adjustment means 58 (i.e. V_c1 =2v_i1 +V_os).

Thus, in accordance with Table 2 above the conversion voltage V_cl produced by the voltage conversion stage ST₁ can be 2V_i1 -V_r, 2V_i1, or 2V_i1 +V_r, depending upon the result of the comparison between V_i1 and the comparison potential V_r /4.

As shown in FIG. 12, the voltage conversion stages of the ADC are connected in series, so that the second voltage conversion stage ST₂ receives as its input voltage V_i2 the analog conversion voltage V_cl produced by the first voltage conversion stage ST₁. As noted above, the switch elements 51 to 56 -54, 56, 57 of the second stage ST₂ are controlled φ₂ to be in the input configuration when the switch elements 51 to 56 -54, 56, 57 of the first stage ST₁ are in the output configuration, so that the second stage ST₂ can begin to perform its comparison operation on the conversion voltage V_cl produced by the first stage ST₁ without delay. The switching signal CK for the switch driving device 4,5 of the second stage ST₂ is accordingly generated while φ₂ is active (rather than while φ₁ is active as was the case with the switch driving device 4,5 the first conversion stage ST₁ ), so that the analogue conversion voltage V_cl of the first stage ST₁ is stored in the second stage ST₂. After the end of the period during which φ₂ is active, φ₁ is activated again, causing the second stage ST₂ to be switched to the output configuration. It therefore produces is analogue conversion voltage V_c2 in dependence upon the analogue conversion voltage V_c1 of the preceding (first) stage.

The analog conversion voltage V_c2 is applied to the input of the next stage ST₃, and is converted in turn (during the next period during which φ₁ is active) to an analogue conversion voltage V_c3. Successive voltage conversion operations are thus performed at each "swap" in the activation of the control signals φ₁ and φ₂. The periods t₁ and t₂ during which the control signals φ₁ and φ₂ are respectively active constitute first and second clock phases of the converter, the second phase commencing after the end of the first clock phase in each successive clock period of the converter.

Since the first stage ST₁ is switched back to the input configuration when the second stage ST₂ is switched to the output configuration (to convert the analog conversion voltage V_c1 just provided by the first stage into the analog conversion voltage V_c2) a new analogue input voltage can be received by the converter each time φ₁ is reactivated. In this way, the ADC can produce a new conversion result (a digital output word based on N three-state bits) in every clock period.

It is not essential that the comparator means 70 of a given stage directly compare the applied input voltage of the stage with the comparison potential. The comparison could be between the comparator comparison potential, on the one hand, and, on the other hand, the input voltage as stored in the voltage storage circuits, or an initial analogue conversion voltage provided by the stage prior to the comparison (the analogue conversion voltage subsequently being corrected).

In place of the N stages used in FIG. 12, it would alternatively be possible to use just two voltage conversion stages operating iteratively with each one alternatively sampling the output of the other. This arrangement would take one clock period (i.e. 2 clock phases) to produce every two bits of three-state logic digital data. Thus, to perform an N bit conversion, the arrangement would take N/2 clock periods, which is much slower than a converter employing N stages. The amount of circuitry required would however be decreased.

In a different aspect of the present invention, it is also possible to construct a three-state logic ADC employing just one voltage conversion stage operating iteratively, although in this case the voltage conversion stage must employ voltage storage circuits constructed differently from the voltage storage circuits in the conversion stages ST_i in the FIG. 12 ADC, as described below with reference to FIG. 13.

In FIG. 13 a voltage conversion stage 90 for use in a three-state logic ADC includes first and second modified voltage storage circuits VSC₁ ' and VSC₂ ' connected respectively to first and second input nodes I₁ and I₂ of the voltage conversion stage 90.

Each modified voltage storage circuit includes an input switch element 1, a unity-gain amplifier element 3 and bootstrapped switch driving device 4, 5 as described hereinbefore with reference to FIGS. 3 to 9(B). However, in place of the single capacitor 2 in the voltage storage circuit of FIG. 3, each modified voltage storage circuit includes two capacitors, labelled C₁ and C₃ in the case of the first modified voltage storage circuit VSC₁ ', and C₂ and C₄ in the case of the second modified voltage storage circuit VSC₂ '. The capacitors C₁ to C₄ are normally of the same capacitance, but this is not essential for correct operation of the voltage conversion stage 90.

Each modified voltage storage circuit also includes a number of switch elements 91 to 106, there being four switch elements associated with each capacitor C₁ to C₄. Thus, the switch elements 91, 92, 95 and 96 are associated with the capacitor C₁, the switch elements 101, 102, 105 and 106 are associated with the capacitor C₂, the switch elements 93, 94, 97 and 98 are associated with the capacitor C₃, and the switch elements 99, 100, 103 and 104 are associated with the capacitor C₄.

The switch elements 91 to 106 are turned on and off in accordance with control signals φ₁ and φ₂ produced by the bootstrapped switch driving means, as explained in more detail hereinafter.

Associated with each modified voltage storage circuit VSC₁ ' or VSC₂ ' is an input isolation switch element 46 connected in series with the input switch element 1 between that element and the relevant input node I₁ or I₂ of the voltage conversion stage 90, and a feedback switch element 48 connected between an output node of the modified voltage storage circuit (at the output terminal of the amplifier element 3) and the input side of the input switch element 1. The input isolation switch element 46 and feedback switch element 48 correspond to the switch elements of the same name and reference numeral in the voltage summation circuitry of FIG. 10, and serve the same purpose. The feedback switch elements 48 can alternatively be replaced by resistors.

Voltage adjustment means 58, generally similar to the voltage adjustment means 58 in FIG. 12, are connected between the first and second modified voltage storage circuits VSC₁ ' and VSC₂ '. Furthermore, comparator means 70, similar to the comparator means of each voltage conversion stage ST_i in FIG. 12, are connected between the respective output nodes of the modified voltage storage circuits.

The voltage adjustment means 58 includes a further plurality of switch elements 581 to 588. The six switch elements 582 to 584 and 586 to 588 are activated in pairs in dependence upon the logic level of the three-state data "bit" a_i produced by the comparator means. In this way, when a_i =-1 the switch elements 582 and 586 are activated and as a result an offset voltage V_os generated between the output terminals of the voltage adjustment means 58 is equal to +V_r, where V_r is a predetermined reference voltage; when a_i =0 the switch elements 583 and 587 are activated and the offset voltage V_os is zero; and when a_i =+1 the switch elements 584 and 588 are activated and the offset voltage V_os is equal to -V_r.

The activation of the other two switch elements 581 and 585 in the voltage adjustment means 58, which are connected respectively to the second and first input nodes I₂ and I₁ of the stage 90, will be explained below.

Control means 61, generally similar to the control means 60' in FIG. 12, are operative to generate not only master control signal φ₁M and φ₂M, but also respective further master control signals SAM_M and CON_M. The master control signals φ₁M, φ₂M SAM_M are applied to the bootstrapped switch driving means 4,5 of each modified voltage storage circuit. The bootstrapped switch driving means of each modified voltage storage circuit generate bootstrapped control signals φ₁, φ₂ and SAMPLE, in accordance with the corresponding master control signals φ₁M, φ₂M and SAM_M, for application to the switch elements of the modified voltage storage control signals tracking the output terminal potential of the amplifier element 3 in the modified voltage storage circuit. A further control signal CONVERT, used to activate the feedback switch element 48 associated with each modified voltage storage circuit, may be a bootstrapped control signal derived from the master signal CON_M, but can alternatively be provided directly by the master signal CON_M since it is not essential for the signal applied to the feedback switch elements 48 to be bootstrapped.

At the start of a conversion operation by the voltage conversion stage 90 of FIG. 13, an analogue input voltage to be converted into its digital equivalent is applied between the first and second input nodes I₁ and I₂ of the voltage conversion stage 90. To facilitate sampling of the applied analogue voltage, the control means 61 generates the master control signal SAM_M which activates the associated bootstrapped control signals SAMPLE in each modified voltage storage circuit to connect the input nodes I₁ and I₂ via the switch elements 1 and 46 to the respective inputs of the amplifier elements 3 in the modified voltage storage circuits. At this time, the CONVERT control signal is deactivated, so that the feedback switch elements 48 are in the off condition

The switch elements 581 and 585 in the voltage adjustment means 58 are also activated by the control signal SAMPLE, so that the output terminal potentials of the voltage adjustment means are equal respectively to the potentials of the second and first input nodes I₂ and I₁. The other switch elements 582 to 584 and 586 are maintained in the off condition at this time.

Assuming that during sampling of the input voltage the control signal φ₁ is active, the switch elements 91, 95, 101 and 105 will be in the on condition, so that the capacitor C₁ in the first modified voltage storage circuit VSC₁ ' has its top plate connected to the first input node I₁ and its bottom plate connected to the second input node I₂. Similarly the capacitor C₂ in the second modified voltage storage circuit VSC₂ ' has its top plate connected to the second input node I₂ and its bottom plate connected to the first input node I₁. Each capacitor C₁ and C₂ therefore stores the applied analogue input voltage, so as to achieve sampling of that input voltage.

Whilst the control signal φ₁ is active, the switch elements 94, 98, 100 and 104 are in the on condition, so that the capacitors C₃ and C₄ are connected in parallel with one another between the respective output terminals of the amplifier elements 3. Because the amplifier elements have unity gain, the sampled analogue input voltage is also stored in each of the capacitors C₃ and C₄ during φ₁.

The SAMPLE control signal is then deactivated, so as to terminate the sampling of the input voltage, the control signal φ₁ remaining active.

After the SAMPLE control signal is deactivated, the CONVERT control signal is activated for the remainder of a conversion operation. Because the input and output terminal potentials of the unity-gain amplifier element 3 are always equal, the input-side and output-side terminals of the input switch element 1 are maintained at the same potential, so that element 1 is maintained safely in the off condition, irrespective of subsequent changes in the potential of the associated input node I₁ or I₂.

The sampled input voltage which is held by the capacitors C₃ and C₄, is compared by the comparator means 70 with a predetermined comparison potential V_r /4 in the same way as in the FIG. 12 ADC. A first "bit" a₁ of three logic digital data (+1, 0, -1) is produced by the comparator means 70 in dependence upon the result of the comparison (see Table 1 above).

After the first data bit a₁ is obtained, a pair of the switch elements 582 to 584 and 586 to 588 in the voltage adjustment means 58 is activated according to the first data bit a₁. The voltage adjustment means 58 thus produces one of its predetermined offset voltages V_os (-V_r, 0, +V_r depending on the digital data bit a₁) between its output terminal. With the control signal φ₁ still active, the switch elements 91, 95, 101, and 105 are all still in the on condition, so that a first series connection now exists between the respective input terminals of the switch elements 3. This first series connection consists of the capacitor C₁, the voltage adjustment means 58 and the capacitor C₂. Thus, the voltage between the respective input terminals of the amplifier element 3 is a first conversion voltage V_c1 equal to twice the sampled analogue input voltage stored in the capacitors C₁ and C₂ plus the offset voltage V_os selected by the first data bit a₁. In this way, a voltage conversion operation, in accordance with Table 2 above, is performed.

The input terminal potentials of the amplifier elements 3 are buffered by the amplifier elements 3, so that the first conversion voltage V_c1 is reproduced between the respective output terminals of the amplifier elements 3.

The switch elements 94, 98, 100 and 104 are all still in the on condition, so that the capacitors C₃ and C₄ are connected in parallel with one another between the respective output terminals of the amplifier elements 3, and each store the first conversion voltage V_c1.

The first conversion voltage V_c1 is compared by the comparator means 70 with the comparison potential V_r /4, and a second data bit a₂ is produced in dependence upon the result of the comparison.

The control means then deactivates the control signal φ₁ and activates the control signal φ₂. At the same time, the second data bit a₂ is applied to the voltage adjustment means to select a new offset voltage V_os in accordance with that data bit a₂. With φ₂ active the switch elements 93, 97, 99 and 103 are in the on condition. As a result, the capacitors C₃ and C₄ are connected in series with the voltage adjustment means 58 to form a second series connection (C₃ -V_os -C₄), in place of the first series connection (C₁ -V_os -C₂) mentioned above, between the respective input terminals of the amplifier elements 3. The resulting new conversion voltage V_c2, produced between the respective output terminals of the amplifier elements 3, is therefore equal to twice the first conversion voltage V_c1 plus the new selected offset voltage V_os. With φ₂ active the switch elements 92, 96, 102 and 106 are in the on condition, so that this new conversion voltage V_c2 is stored in the capacitors C₁ and C₂ which are connected in parallel between the respective output terminals of the amplifier elements 3.

The new conversion voltage V_c2 is compared with the comparison potential V_r /4 in the comparator means 70 to produce the nest data bit a₃. The control signal φ₂ is then deactivated the control signal φ₁ is activated, and the data bit a₃ is applied to the voltage adjustment means to select a new offset voltage V_os. With φ₁ active the first series connection (C₁ -V_os -C₂) replace the second series connection (C₃ -V_os -C₄) between the amplifier element input terminals and the capacitors C₃ and C₄ store the resulting new conversion voltage V_c3.

Thereafter, the control signals φ₁ and φ₂ are activated alternatively, a new data bit a_i and new conversion voltage being produced during each successive control signal phase.

As described before with reference to FIG. 12, the data bits a_i are applied to data processing means 80 (not shown) of the ADC for processing to produce a digital output word representative of the originally-applied analogue voltage. It will be understood that the FIG. 13 voltage conversion stage requires N clock phases to produce a digital output word based on N three-state bits.

It will be appreciated that the switch elements 1, 48, 91, 92, 93 and 94 in the first modified voltage storage circuit VSC₁ ', and the corresponding switch elements 1, 48, 103, 104, 105 and 106 in the second modified voltage storage circuit VSC₂ ', each have no voltage across their two terminals when either φ₁ or φ₂ is active, since, for each amplifier element 3, the input terminal potential is equal to the output terminal potential.

The switch elements 91 to 94 and 103 to 106 connected to the capacitor top plates can switch without non-overlap (i.e. without delay after switch-off of, say, element 91 before element 92 can be switched on) since all of the four nodes to which these elements are connected (amplifier element input terminal, amplifier element output terminal, and the respective top plates of the two capacitors) have the same voltage before and after switching (i.e. before and after each control signal phase change from φ₁ to φ₂ or vice versa). This ability to switch the top plate switches 91 to 94 and 103 to 106 without nonoverlap simplifies the generation of the control signals.

It should be noted that the switches 95 to 102 connected to the capacitor bottom plates should be switched a predetermined short time after switching of the switch elements 91 to 94 and 103 to 106 connected to the capacitor top plates, in order to avoid charge injection effects. The predetermined short time should be minimised in view of the fact that during this time the input terminal of each amplifier element 3 is effectively coupled to the output terminal of the other amplifier element, so that positive feedback can occur. The effects of this positive feedback are not serious in view of the fact that the amplifier elements have unity gain, but none the less it is preferable to avoid leaving the voltage conversion stage 90 in this condition for longer than is absolutely necessary. Thus, as soon as the top plate switch elements 91 to 94 and 103 to 106 have settled, the bottom plate switch elements 95 to 102 are switched.

The switch elements 1 and 91 to 94 in the first modified voltage storage circuit VSC₁ ' should preferably be formed in one or more wells of the opposite conductivity type to that of the surrounding material of the substrate, the potential of the or each well being fixed in relation to the output terminal potential of the amplifier element 3 in the first modified voltage storage circuit. The same applies to the switch elements 1 and 103 to 106 in the second modified voltage storage circuit VSC₂ '. This arrangement of the switch elements enables parasitic capacitances in the modified voltage storage circuit to be bootstrapped out, in the same basic manner as described hereinbefore with reference to the voltage storage circuit of FIGS. 3 to 9.

In the FIG. 13 voltage conversion stage, the first voltage conversion operation is performed during the initial clock phase in which the analogue input voltage is sampled, immediately after sampling is complete. This speeds up operation of the converter, but does require the provision of extra switch elements (the elements 581 and 585 shown incorporated in the voltage adjustment means 58) to charge the capacitor bottom plates of the capacitors C₁ and C₂ to the input node potentials during sampling. It would be possible to omit these switch elements 581 and 585 and simply perform a comparison operation in the initial clock phase (to obtain a₁), the first voltage conversion operation being performed in the next clock phase.

A voltage conversion stage as described above with reference to FIG. 12 or 13 is applicable, with suitable modifications, to other analogue-to-digital converters that require voltage doubling and offsetting operations.

In order to minimise power consumption of an ADC employing a series of voltage conversion stages as described above with reference to FIG. 12, it is advantageous to "scale" successive stages. This will now be discussed in more detail with reference to FIG. 14.

In FIG. 14 the first three stages of an ADC as shown in FIG. 12 are represented schematically. The storage capacitors 2 in the first stage each have a capacitance C, the transistors in the amplifier element 3 are each of channel width W, and the current flowing through each of those transistors in the amplifier element 3 is I.

In the second stage, the storage capacitors 2 are each of capacitance kC, where 1/k is a predetermined scaling factor (k<1) the transistors in the amplifier elements 3 are each of width kW, and the current flowing through each transistor is kI. Similarly, in the third stage the capacitance is k² C, the transistor channel width k² W, and the transistor current k² I.

Thus each successive stage is scaled, at least insofar as these three parameters are concerned, by the scaling factor 1/k. As a result, the total current consumed in the device, expressed in relation to the current consumed by the first stage, is

1+k+k² +k³+ . . .

Each stage has a noise power at its own input of 1/k but, relative to the input terminal of the ADC, this is reduced by the product of the gains of the preceding stages. For example, the second stage noise power=1/k, the voltage gain of the preceding stages (in this case the voltage gain of the first stage)=2, and hence the noise power, relative to the input noise power, is 1/4k.

Thus, total noise power at the input for all the stages is ##EQU1##

When k=1/2, for example, total noise=1+1/2+1/4+1/8 . . . =2

Similarly substituting k=1/2 in the total current equation above, total current=1+1/2+174+1/8 . . . =2

For a constant total power all sizes must then be divided by the result of the power summation, i.e. input noise is multiplied by the same factor. ##EQU2## This is a minimum when m=1, i.e. k=1/2.

From the above analysis, it will be apparent that the optimum scaling factor for minimum, total power consumption of the ADC should be 2. This provides a minimum noise level for a given power consumption or a minimum power consumption level for a given noise level Thus, each stage should be substantially half the size of the preceding one In this case the total power consumption equals two times the power consumption of the first stage, and the total noise power equals two times the first stage noise power.

FIG. 15 shows the variation of total current and noise with the scaling factor 1/k in the case of a 16 stage ADC. As FIG. 15 shows, the noise minimum for a given power consumption and the power consumption minimum for a given noise level each occur when the scaling factor 1/k=2.

Although the analysis presented above suggests that scaling of the conversion stages should be applied to all stages of the ADC, in practice scaling of stages cannot continue to the final stage, since for a 16 stage series (17 bit ADC) this would mean that the last stage was 1/2¹6 =1/65536 times the size of the first stage.

At a particular stage in the series, when the stage size has become suitably small all the succeeding stages are made the same size, this increases the noise slightly but means that a huge range of sizes is not required.

For example, if scaling stops after six stages, the smallest stage size (used in the sixth and all successive stages) is 1/32 relative to the size of the first stage. In this case total power=

1+1/2+1/4+1/8+1/16+1/32+1/32+1/32 . . .

Once a minimum stage size is selected, a stage of such size can be designed as a "unit" stage that can be paralleled up (or "stretched" in layout) to form the bigger stages. For example, if the unit stage is of size 1/32 relate to the first stage:

first stage=32 parallel units

second stage=16 parallel units

third stage=8 parallel units

One possible layout on a chip of an ADC employing a unit stage of size 1/32 is shown in FIG. 16.

For a given minimum size of stage, the optimum scaling factor 1/k is still very close to 2, as will be clear from Table 3, which presents the optimum scaling factors for different smallest stage sizes in the case of a 15 stage ADC (16 bits).

Compared to the optimum noise power figure of 4.0 when scaling is not stopped, a smallest stage size of 1/32 results in a total power increase or noise increase of around 10% or 0.46 dB, whereas a minimum stage size of 1/16 increases the power or noise by around 25% or 0.99 dB. These two minimum stage sizes would appear to be good compromises.

TABLE 3
______________________________________
Smallest Stage
Minimum     Optimum
Size          overall noise
scaling factor
(first stage = 1)
(noise at k = 1/2)
(l/k)
______________________________________
small         4.0  (4.0)  2.0
1/256         4.03 (4.04) 1.99
1/128         4.08 (4.08) 1.99
1/64          4.19 (4.19) 1.97
1/32          4.44 (4.45) 1.92
1/16          4.97 (5.02) 1.83
1/8           6.05 (6.23) 1.68
______________________________________

Scaling such as that described above can usually be applied, in another aspect of the present invention, to any suitable kind of analogue-to-digital converter employing a series of voltage conversion stages. For example, it would be possible to apply scaling to the voltage conversion circuits described in EP-B-0214831 in a case in which a plurality of stages as described in that document were connected together as a series.

The current consumed by the ADC of FIG. 12 is directly proportional to the capacitance of the storage capacitors 2 and inversely proportional to conversion rate. This means that for higher resolution and higher conversion rates the power is of course increased. However, it is estimated that a 16 bit 10 Ms/s converter would consume less than 0.5 W. This suggests that by reducing the conversion rate to 1 Ms/s, the power could be reduced to 50 mW, or 5 mW at 100 ks/s.

For lower resolutions (for example 12 bits), the power and area decrease rapidly since the capacitance can be much smaller; a 12 bit 50 Ms/s converter is estimated to consume 200 mW including the power consumption of the digital logic circuitry required to process the digital data provided by the different conversion stages.

This represents a much improved power/speed trade-off relationship as compared with previously-considered converters. One major reason for this is that each stage m the series can be half the size and power of the previous stage, giving a total power for the converter which is approximately double that of the first stage. This also gives a big reduction in chip size: it is estimated that a 16 bit 10 Ms/s converter would occupy less than 10mm² in a suitable process.

In addition to the voltage doubling circuitry and comparator means, the digital logic circuitry for a N-bit output word ADC comprise (N-1)² D-type flip-flops and (N-1) full adders, all clocked at the conversion rate. For a 16-bit resolution this gives a basic cell count of about 2000, and a power consumption at 5 V and 10 MHz of about 25% of the estimated analogue power consumption at 16 bit resolution (for 15 bit resolution the analogue power consumption would be reduced by a factor of 4).

As noted above, the gain of each of the amplifier elements 3 of the voltage conversion stages of the ADC should be exactly unity. If they are not, apart from giving rise to a gain error in the transfer function, an additional gain error results because the parasitic capacitances will not be completely bootstrapped out Non-linearity resulting from these errors can be corrected for by adjusting the reference voltage V_r used by each stage slightly along the series of stages, for example, to correct for a 0.1% gain error, V_r may be reduced by 0.1% for each successive stage.

Alternatively, or in addition, the digital data processing means 80 receiving the digital data from each stage may carry out any required correction for voltage conversion errors in the analogue circuitry by adjusting the digital data of the successive stages fractionally.

In order to produce an ADC capable of high speed operation, it is essential that the operation of the switch elements and of the amplifier elements in the stages is sufficiently fast. The unity-gain amplifier elements 3 can be designed to be much faster than conventional operational amplifiers, and SPICE simulations have indicated that a settling time of 50 ns (corresponding to a conversion rate of 10 Ms/s) is practical to 16 bit accuracy in a suitable process. Using depletion mode NMOS buffers and sacrificing some resolution, settling times of 10 ns can be obtained to 12 bit accuracy. This suggests that ADCs based on the FIG. 12 design could be employed in applications such as HDTV.

Circuit noise is not a serious problem in the FIG. 12 ADC, because the noise due to the amplifier elements is effectively reduced by virtue of the doubling of the analogue input voltage before it reaches the amplifier elements. It is conceivable that the amplifier elements can be designed so that they contribute less noise than kT/C noise This kT/C noise is due to thermal noise which limits the accuracy of a given stored voltage sample in any switched capacitor circuit, and prevents very small capacitors from being used. It is estimated that for a 16 bit signal to noise ratio, storage capacitors of at least 10 pF are required in the fist stage, reducing by half in each subsequent stage.

For maximum performance, the FIG. 12 ADC is preferably produced by a p-well (n-substrate) CMOS process, desirably using depletion-mode devices.

It is difficult to obtain sufficiently large voltage swings even with a single 5 V power supply (lower voltage swings mean that lower noise levels are required in the circuitry making up the different stages), and this problem is exacerbated with still lower supply voltages such as 3.3 V.

However, none of the devices in the ADC are exposed to full supply voltage because they are connected in series; only the source/drain diodes are subjected to a higher voltage and even this is not as large as the supply voltage. The largest voltage (5 V) is produced across the well-substrate junction. In view of this, it may be advantageous to use split ±3 V (or ±3.3 V) supplies, with the digital circuits (of minimum Geometry) running from 0 V and +3 V, and the analogue circuits using ±3 V. This split-supply approach also has the major advantage that the input signals can swing either side of 0 V and so can be DC coupled. The digital power consumption is also reduced in accordance with the reduction in the effective digital logic supply voltage and this could give a significant reduction in total power consumption.

Smaller geometry processes can permit an increase in maximum clock rate though not if this is limited by analogue power consumption. The main advantage of split power supplies is therefore increased digital speed and reduced power consumption which would increase the maximum speed of operation of the ADC.

Claims

1. A voltage storage circuit comprising:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use; and

an amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate, said voltage storage circuit being formed on a single substrate, and said input switch element and said input device of the amplifier element being located within one or more wells of the conductivity type opposite to that of the surrounding material of said substrate; and

means for causing each well potential to track the potential of said one plate.

2. A voltage storage circuit as claimed in claim 1, wherein the potential tracking device includes a current source, connected to the said first current-path electrode for causing the first current-path electrode potential to track the control electrode potential, and active follower means connected operatively between the said first and second current-path electrodes for causing the second current-path electrode potential to track the first current-path electrode potential.

3. A voltage storage circuit as claimed in claim 2, wherein the said electronic input device is an FET input transistor and the said control electrode is the gate electrode of the FET input transistor, the first current-path electrode is the source electrode of the FET input transistor, the said second current-path electrode is the drain electrode of the FET input transistor, and the said controllable current path is provided by the drain-source channel of the FET input transistor.

4. A voltage storage circuit as claimed in claim 3, wherein the said active follower means comprise a cascoding FET transistor connected with its drain-source channel in series with the drain-source channel of the said FET input transistor so that the source electrode potential of the cascoding transistor tracks the gate electrode potential thereof and also comprise a bias generator connected operatively between the source electrode of the FET input transistor and the gate electrode of the cascoding transistor for maintaining therebetween a substantially constant potential difference.

5. A voltage storage circuit as claimed in claim 2, wherein the said amplifier element is made up of first and second substantially identical circuit portions, the first portion including the said input device and the said active follower means and the second portion including the said current source.

6. A voltage storage circuit as claimed in claim 1, wherein the said input switch element is an electronic input switch element, operative in dependence upon the potential at a switching electrode thereof, the circuit further including switch driving means connected to cause the switching electrode potential to track the input terminal potential when the element is in its ON condition, thereby maintaining the switching electrode potential substantially fixed in relation to the input terminal potential, and operable to cause the switching electrode potential to change, relative to the input terminal potential such that the element is changed from its ON condition to its OFF condition.

7. A voltage storage circuit as claimed in claim 6, wherein the said switching electrode potential is derived from the said output signal.

8. A voltage storage circuit as claimed in claim 7, wherein the said switch driving means are connected operatively with the said output terminal and are operable, in dependence upon a switching signal received thereby, to apply to the said switching electrode either an ON potential, for maintaining the said input switch element in its ON condition, or an OFF potential, for maintaining the said input switch element in its OFF condition, the said ON and OFF potentials being each substantially fixed in relation to the said output terminal potential but differing from one another by a predetermined amount.

9. A voltage storage circuit as claimed in claim 8, having respective first and second biassing lines connected operatively to the said output terminal so as to be at potentials that are respectively fixed in relation to the output terminal potential, the second biassing line potential being equal to one of the said ON and OFF potentials and the potential difference between the said first and second biassing lines being greater than or equal to the said predetermined amount, wherein the said switch driving means include a bootstrap capacitor one plate of which is connected to the said switching electrode for providing the said switching electrode potential and also include connecting means connected with both plates of the bootstrap capacitor and with the said biassing lines and switchable, when the switching electrode potential is to be changed from the said one of its ON and OFF potentials to the other of those potentials, from a charging configuration, serving to connect the said one plate of the bootstrap capacitor to the said second biassing line whilst connecting the other plate thereof to the said first biassing line, to a floating configuration serving to isolate the said one plate from the second biasing line whilst connecting the said other plate to the said second biassing line, thereby to cause the potential at the said one plate to be changed from the second biassing line potential to a potential differing therefrom by the aid predetermined amount.

10. A voltage storage circuit as claimed in claim 8, having respective first, second and third biasing lines connected operatively to the said output terminal so as to be at potentials that are respectively fixed in ration to the output tern potential, the third biassing line potential being equal to one of the said ON and OFF potentials and the potential difference between the said first and second biassing lines being greater than or equal to the said predetermined amount, wherein the said switch driving means include a bootstrap capacitor one plate of which is connected to the said switching electrode for providing the said switching electrode potential and also include connecting means connected with both plates of the bootstrap capacitor and with the said biassing lines and switchable, when the switching electrode potential is to be changed from the said one of its ON and OFF potentials to the other of those potentials, from a changing configuration, serving to connect the said one plate of the bootstrap capacitor to the said third biassing line whilst connecting the other plate thereof to the said first biassing line, to a floating configuration serving to isolate the said one plate from the third biassing line whilst connecting the said other plate to the said second biassing line, thereby to cause the potential at the said one plate to be changed from the third biassing line potential to a potential differing therefrom by the said predetermined amount.

11. A voltage storage circuit as claimed in claim 8, wherein the said electronic input switch element is a MOSFET transistor and one of the said ON and OFF potentials is substantially the same as the said output terminal potential. 12. A voltage storage circuit as claimed in claim 1, formed on a single substrate, wherein the said input switch element and the said input device of the amplifier element are located within one or more wells of the conductivity type opposite to that of the surrounding material of said substrate, there being means for causing the or each well

potential to track the potential of the said one plate.13. A voltage storage circuit as claimed in claim 12 1, wherein the

said storage capacitor is also located within such a well. 14. A voltage storage circuit as claimed in claim 12 1, having one or more conductive shields extending over the area of the or each well, and also having means for causing the or each shield potential to track

the potential of the said one plate. 15. A voltage storage circuit as claimed in claim 12 2, wherein the said amplifier element is made up of first and second substantially identical circuit portions, the first portion including the said input device and the said active follower means and the second portion including the said current source, and wherein the said first portion of the amplifier element is located within the said one or more wells, and the said second portion of the amplifier element is formed within one or more further wells, each of the conductivity type opposite to that of the surrounding areas of the substrate, the or each further well potential being substantially fixed in

relation to the potential of a supply line of the circuit. 16. A voltage storage circuit as claimed in claim 6, further including comprising:

an electronic input switch element, operative in dependence upon the potential at a switching electrode thereof;

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of said electronic input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use;

switch driving means connected to cause the switching electrode potential to track the input terminal potential when the element is in its ON condition, thereby maintaining the switching electrode potential substantially fixed in relation to the input terminal potential, and operable to cause the switching electrode to change, relative to the input terminal potential, such that the element is changed from its ON condition to its OFF condition;

an amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate; and

input potential maintaining means, interposed between the said input terminal and the input side of the said input switch element, for maintaining the input-side potential of the input switch element, after the element is changed to the OFF condition, substantially fixed in relation to the potential of the said one plate of the storage capacitor.

7. A voltage storage circuit as claimed in claim 16, wherein the said input potential maintaining means comprise a further switch element connected in series with the said input switch element and operable, after the said input switch element has been changed to the OFF condition, to

isolate the input side of that element from the said input terminal. 18. A voltage storage circuit as claimed in claim 17, wherein the said input potential maintaining means further comprise an auxiliary capacitor connected between the input side of the said input switch element and the

said other plate of the said storage capacitor. 19. A voltage storage circuit as claimed in claim 17, wherein the said input potential maintaining means further comprise a feedback switch element connected between the said amplifier element and the input side of the said input switch element and operable, while the input side of that element is so isolated, to apply thereto a potential derived from the potential of the

said one plate of the storage capacitor. 20. A voltage storage circuit as claimed in claim 1, wherein the said amplifier element has a gain of

substantially unity. 21. voltage summation circuitry comprising:

first, second and third input nodes to which first, second and third potentials are respectively applied when the circuitry is in use;

a voltage storage circuit including:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use; and

an a unity-gain amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor such that the output terminal potential is substantially equal to the potential of said one plate when the circuit is in use, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate, said amplifier element having a gain of substantially unity;

an output node connected with the output terminal of the voltage storage circuit; and

switching means connected with said input nodes and with said voltage storage circuit and switchable, after the input switch element of the voltage storage circuit has been changed to the OFF condition, from an input configuration to an output configuration, said input configuration serving to connect said first and second input nodes to said input and common terminals respectively of the voltage storage circuit, thereby to permit storage of the potential difference between said first and second potentials in the storage capacitor of the voltage storage circuit, and said output configuration serving to connect the common terminal of the voltage storage circuit to the third input node, thereby to produce at said output node an output potential which is substantially equal to the sum of the third potential and the stored difference between the first and

second potentials. 22. voltage summation circuitry comprising:

first, second, third, fourth, fifth and sixth input nodes, a first pair of input voltages being applied to said first and second input nodes, a second pair of input voltages being applied to said third and fourth input nodes, and a third pair of input voltages being applied to said fifth and sixth input nodes, when the circuitry is in use;

first and second voltage storage circuits, each of said first and second voltage storage circuits including:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use; and

an a unity-gain amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor such that the output terminal potential is substantially equal to the potential of said one plate when the circuit is in use, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate, said amplifier element having a gain of substantially unity;

first and second output nodes connected with the respective output terminals of said first and second voltage storage circuits; and

switching means connected with said input nodes and with said voltage storage circuits and switchable, after the respective input switch elements of the first and second voltage storage circuits have been changed to the OFF condition, from an input configuration to an output configuration, said input configuration serving to connect said first and second input nodes to said input and common terminals respectively of said first voltage storage circuit, and also to connect said third and fourth input nodes to said input and common terminals respectively of said second voltage storage circuit, thereby to permit storage, in said storage capacitor of the first voltage storage circuit, of a first potential difference between the two input voltages of said first pair and to permit storage, in said storage capacitor of the second voltage storage circuit, of a second potential difference between the two input voltages of said second pair, and said output configuration serving to connect the respective common terminals of the first and second voltage storage circuits to the fifth and sixth input nodes respectively, thereby to produce between said first and second output nodes a pair of output voltages the potential difference between which is substantially equal to the sum of the potential difference between the two input voltages of said third pair and the difference between the stored first

and second potential differences. 23. voltage doubling circuitry comprising:

first and second input nodes between which an input voltage to be doubled is applied when the circuitry is in use;

first and second voltage storage circuits, each of said first and second voltage storage circuits including:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use; and

an a unity-gain amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor such that the output terminal potential is substantially equal to the potential of said one plate when the circuit is in use, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the, control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate, said amplifier element having a gain of substantially unity;

first and second output nodes connected respectively with the respective output terminals of the first and second voltage storage circuits; and

switching means connected with said input nodes and with said voltage storage circuits and switchable, after the respective input switch elements of the first and second voltage storage circuits have been changed to the OFF condition, from an input configuration to an output configuration, said input configuration serving to connect said first input node to both said input terminal of said first voltage storage circuit and said common terminal of said second voltage storage circuit, and also to connect said second input node to both said input terminal of said second voltage storage circuit and said common terminal of said first voltage storage circuit, thereby to cause each of the respective storage capacitors of said voltage storage circuits to be charged to said input voltage, and said output configuration serving to connect the respective common terminals of the first and second voltage storage circuits together so that said storage capacitors are connected in series with one another between the respective amplifier-element inputs of said first and second output nodes voltage storage circuits, thereby to produce between those said first and second output nodes an output voltage which is substantially

double said input voltage. 24. A voltage conversion stage comprising:

voltage doubling circuitry including:

first and second input nodes between which an input voltage to be doubled is applied when the circuitry is in use;

first and second voltage storage circuits, each of said first and second voltage storage circuits including:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use; and

an a unity-gain amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor such that the output terminal potential is substantially equal to the potential of said one plate when the circuit is in use, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate, said amplifier element having a gain of substantially unity;

first and second output nodes connected respectively with the respective output terminals of the first and second voltage storage circuits; and

switching means connected with said input nodes and with said voltage storage circuits and switchable, after the respective input switch elements of the first and second voltage storage circuits have been changed to the OFF condition, from an input configuration to an output configuration, said input configuration serving to connect said first input node to both said input terminal of said first voltage storage circuit and said common terminal of said second voltage storage circuit, and also to connect said second input node to both said input terminal of said second voltage storage circuit and said common terminal of said first voltage storage circuit, thereby to cause each of the respective storage capacitors of said voltage storage circuits to be charged to said input voltage, and said output configuration serving to connect the respective common terminals of the first and second voltage storage circuits together so that said storage capacitors are connected in series with one another between the respective amplifier element inputs of said first and second output nodes voltage storage circuits, thereby to produce between those said first and second output nodes an output voltage which is substantially double said input voltage;

comparator means connected for receiving a working voltage equal to or derived from said input voltage and also connected for receiving a comparison potential and operable to perform a comparison between that working voltage and said comparison potential and to provide digital data indicative of the result of the comparison; and

voltage adjustment means connected between the respective common terminals of said first and second voltage storage circuits and operable, after said switching means have been switched from said input configuration to said output configuration, to apply between those terminals an offset voltage having a value selected, by said digital data, from a plurality of preset possible values, thereby to produce between said output nodes an analogue conversion voltage which differs from double said input voltage by the

selected offset voltage. 25. A voltage conversion stage as claimed in claim 24, wherein the said comparator means perform the said comparison whilst the switching means of the voltage storage circuits are in the said

input configuration. 26. A voltage conversion stage as claimed in claim 24, wherein the said comparator means are connected to the said first and second input nodes, so that the said input voltage is the said working voltage, and provide first such digital data if the said input voltage is less than or equal to minus the said comparison potential, and provide second such digital data if the said comparison potential is less than or equal to the said input voltage, and provide third such digital data in all other cases, and wherein the offset voltage selected by the said second digital data is -V_ref, where +V_ref is the offset voltage selected by the said first digital data, and the offset voltage selected by the said third digital data is zero; the said comparison potential

being substantially equal to V_ref /4. 27. An analogue-to-digital converter comprising:

a series of N stages, each of said N stages being a voltage conversion stage including:

voltage doubling circuitry including:

first and second input nodes between which an input voltage to be doubled is applied when the circuitry is in use;

first and second voltage storage circuits each of said first and second voltage storage circuits including:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use; and

an a unity-gain amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor such that the output terminal potential is substantially equal to the potential of said one plate when the circuit is use, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate, said amplifier element having a gain of substantially unity;

first and second output nodes connected respectively with the respective output terminals of the first and second voltage storage circuits; and

switching means connected with said input nodes and with said voltage storage circuits and switchable, after the respective input switch elements of the first and second voltage storage circuits have been changed to the OFF condition, from an input configuration to an output configuration, said input configuration serving to connect said first input node to both said input terminal of said first voltage storage circuit and said common terminal of said second voltage storage circuit, and also to connect said second input node to both said input terminal of said second voltage storage circuit and said common terminal of said first voltage storage circuit, thereby to cause each of the respective storage capacitors of said voltage storage circuits to be charged to said input voltage, and said output configuration serving to connect the respective common terminals of the first and second voltage storage circuits together so that said storage capacitors are connected in series with one another between the respective amplifier element inputs of said first and second output nodes voltage storage circuits, thereby to produce between those said first and second output nodes an output voltage which is substantially double said input voltage;

comparator means connected for receiving a working voltage equal to or derived from said input voltage and also connected for receiving a comparison potential and operable to perform a comparison between that working voltage and said comparison potential and to provide digital data indicative of the result of the comparison; and

voltage adjustment means connected between the respective common terminals of said first and second voltage storage circuits and operable, after said switching means have been switched from said input configuration to said output configuration, to apply between those terminals an offset voltage having a value selected, by said digital data, from a plurality of preset possible values, thereby to produce between said output nodes an analogue conversion voltage which differs from double said input voltage by the selected offset voltage, an analogue voltage to be digitised being applied between said first and second input nodes of the first stage of the series, and said first and second input nodes of each successive stage being connected to said first and second output nodes respectively of the immediately-preceding stage;

control means operable to cause the switching means of each of said stages in succession to be switched from said input configuration to said output configuration, such switching being controlled to occur in each of the stages, except for the first stage, at a time when the switching means of the immediately-preceding stage is in the output configuration so that prior to such switching the stage being switched receives as its input voltage the analogue conversion voltage produced by that immediately-preceding stage and so produces its analogue conversion voltage in dependence thereupon after such switching; and

data processing means connected for receiving the said digital data provided by said N stages and operative to derive therefrom a digital output word, comprising N+1 bits, representative of the applied analogue

voltage. 28. An analogue-to-digital converter as claimed in claim 27, operative alternately in first and second clock phases, wherein the said control means operate in the said first clock phase to maintain the respective switching means of the odd-numbered stages of the series in the input configuration whilst maintaining the respective switching means of the even-numbered stages in the said output configuration but operate in the said second clock phase to maintain the respective switching means of the even-numbered stages in the said input configuration whilst maintaining the respective switching means of the odd-numbered stages in

the output configuration. 29. An analogue-to-digital converter as claimed in claim 27, wherein for at least one pair of adjacent stages of the series, the respective storage capacitors of the said first and second voltage storage circuits in the second stage of the pair are smaller in capacitance than the comparable storage capacitors in the first stage of

the pair. 30. An analogue-to-digital converter as claimed in claim 29, wherein the storage capacitance ratio of the two stages of one or each

such pair is approximately 2:1. 31. An analogue-to-digital converter as claimed in claim 27, wherein for at least one pair of adjacent stages of the series, the respective amplifier element input devices of the said first and second voltage storage circuits in the second stage of the pair are smaller in width than the comparable input devices in the first stage

of the pair. 32. An analogue-to-digital converter as claimed in claim 31, wherein the input device width ratio of the two stages of one or each such

pair is approximately 2:1. 33. An analogue-to-digital converter as claimed in claim 27, wherein for at least one pair of adjacent stages of the series, the respective currents in the controllable current paths of the amplifier element input devices of the said first and second voltage storage circuits in the second stage of the pair are smaller than the

comparable currents in the first stage of the pair. 34. An analogue-to-digital converter as claimed in claim 33, wherein the current ratio of the two stages of one or each such pair is approximately 2:1.

An analogue-to-digital converter as claimed in claim 27, wherein in each of the second to nth stages of the converter, where 2≦n≦N, each of the respective storage capacitors of the said first and second voltage storage circuits of the stage has a capacitance that is reduced, relative to the capacitance of the comparable storage capacitor of the immediately-preceding stage, by a first scaling factor

that is constant throughout those second to nth stages. 36. An analogue-to-digital converter as claimed in claim 35, wherein the said

first scaling factor is approximately 2. 37. An analogue-to-digital converter as claimed in claim 27, wherein in each of the second to nth stages of the converter, where 2≦n≦N, the amplifier element input device of each voltage storage circuit of the stage is of a channel width that is reduced, relative to the channel width of the comparable amplifier element input device of the immediately-preceding stage, by a second scaling factor that is constant throughout those second to nth

stages. 38. An analogue-to-digital converter as claimed in claim 37,

wherein the said second scaling factor is approximately 2. 39. An analogue-to-digital converter as claimed in claim 27, wherein in each of the second to nth stages of the converter, where 2≦n≦N, the current in each of the said controllable current paths of the amplifier element input devices of the stage is controlled to be reduced, relative to the current in the comparable controllable current path of the immediately-preceding stage, by a third scaling factor that is constant

throughout those second to nth stages. 40. An analogue-to-digital converter as claimed in claim 39, wherein the said third scaling factor is

approximately 2. 41. An analogue-to-digital converter as claimed in claim 27, wherein, for at least one pair of adjacent stages of the series, at least one of the said preset possible values of the offset voltage in the second stage of the pair is adjusted fractionally as compared with the corresponding preset possible value of the offset voltage in the first

stage of the pair. 42. An analogue-to-digital converter as claimed in claim 27, wherein the said data processing means are operable to fractionally adjust the digital data provided by the respective comparator means of successive stages of the series so as to facilitate correction of

voltage conversion errors in those successive stages. 43. An analogue-to-digital converter comprising:

first and second stages, each of said stages being a voltage conversion stage including:

voltage doubling circuitry including:

first and second input nodes between which an input voltage to be doubled is applied when the circuitry is in use;

first and second voltage storage circuits, each of said first and second voltage storage circuits including:

a storage capacitor, one plate of which is connected to an input terminal of the circuit by way of an input switch element and the other plate of which is connected to a common terminal of the circuit, to store an input signal being applied between said input and common terminals when the circuit is in use; and

an a unity-gain amplifier element, having an input connected to said one plate and an output connected to an output terminal of the circuit, for providing an output signal, between said output and common terminals, dependent upon the voltage stored in said storage capacitor such that the output terminal potential is substantially equal to the potential of said one plate when the circuit is in use, which amplifier element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the electronic input device and also having a control electrode to which a potential is applied to control the magnitude of current in said controllable current path, said control electrode being connected to said one plate, and said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of said one plate, said amplifier element having a gain of substantially unity;

first and second output nodes connected respectively with the respective output terminals of the first and second voltage storage circuits; and

switching means connected with said input nodes and with said voltage storage circuits and switchable, after the respective input switch elements of the first and second voltage storage circuits have been changed to the OFF condition, from an input configuration to an output configuration, said input configuration serving to connect said first input node to both said input terminal of said first voltage storage circuit and said common terminal of said second voltage storage circuit, and also to connect said second input node to both said input terminal of said second voltage storage circuit and said common terminal of said first voltage storage circuit, thereby to cause each of the respective storage capacitors of said voltage storage circuits to be charged to said input voltage, and said output configuration serving to connect the respective common terminals of the first and second voltage storage circuits together so that said storage capacitors are connected in series with one another between the respective amplifier element inputs of said first and second output nodes voltage storage circuits, thereby to produce between those said first and second output nodes an output voltage which is substantially double said input voltage;

comparator means connected for receiving a working voltage equal to or derived from said input voltage and also connected for receiving a comparison potential and operable to perform a comparison between that working voltage and said comparison potential and to provide digital data indicative of the result of the comparison; and

voltage adjustment means connected between the respective common terminals of said first and second voltage storage circuits and operable, after said switching means have been switched from said input configuration to said output configuration, to apply between those terminals an offset voltage having a value selected, by said digital data, from a plurality of preset possible values, thereby to produce between said output nodes an analogue conversion voltage which differs from double said input voltage by the selected offset voltage,

said first and second stages being connected together such that said first and second output nodes of the first stage are connected to said first and second input nodes respectively of the second stage and said first and second output nodes of said second stage are connected to said first and second input nodes respectively of the first such stage, an analogue voltage to be digitised being applied, at the start of an iterative conversion operation of the converter, between said first and second input nodes of said first stage;

control means operable to cause the switching means of the first and second stages to be switched alternately, starting with the first stage, from said input configuration to said output configuration, such switching being controlled to occur in one stage at a time when the switching means of the other stage are in the output configuration so that prior to such switching the one stage being switched receives as its input voltage the analogue conversion voltage produced by the other stage and so produces its analogue conversion voltage in dependence thereupon after such switching; and

data processing means connected for receiving said digital data provided alternately by the first and second stages during the course of said iterative conversion operation and operative to derive therefrom a digital

output word representative of the applied analogue voltage. 44. An analogue-to-digital converter, operable alternately in first and second clock phases, including:

first and second input nodes between which an analogue input voltage to be digitised can be applied when the converter is in use;

first and second voltage storage circuits, each including respective first and second storage capacitors and a unity-gain amplifier element having respective input and output terminals, which element includes an electronic input device having a controllable current path provided between respective first and second current-path electrodes of the device and also having a control electrode to which a potential is applied to control the magnitude of current in the said current path, the said control electrode being connected to the said input terminal of the amplifier element, and the said first and second current-path electrodes being connected with a potential tracking device such that both the first current-path electrode potential and the second current-path electrode potential track the control electrode potential, whilst current flows in the said controllable current path, so that the respective potentials of the first and second current-path electrodes are kept substantially fixed in relation to the potential of the said input terminal;

input sampling means operable during an initial one of the clock phases to connect the said input terminal of the first voltage storage circuit to the said first input node and to connect the said input terminal of the second voltage storage circuit to the said second input node;

first and second output nodes connected respectively with the amplifier element output terminals of the said first and second voltage storage circuits;

comparator means connected to the said first and second output nodes and also connected for receiving a comparison potential and operable in each clock phase to perform a comparison between the potential difference between the first and second output nodes and the said comparison potential and to provide digital data indicative of the result of the comparison;

voltage adjustment means having a pair of connection terminals and operable in each clock phase to apply between those terminals an offset voltage having a value selected, by the said digital data provided by the said comparator means in the immediately-preceding clock phase, from a plurality of preset possible values;

switching means operable in the first clock phase to connect the two first storage capacitors and the said connection terminals in series between the respective input terminals of the amplifier elements, whilst connecting the said second storage capacitors in parallel with one another between the first and second output nodes, and operable in the second clock phase to connect the two second storage capacitors and the said connection terminals in series between the respective input terminals of the amplifier elements, whilst connecting the said first storage capacitors in parallel with one another between the first and second output nodes; and

data processing means connected for receiving the said digital data provided by the said comparator means over a predetermined number of the said clock phases and operative to derive therefrom a digital output word

representative of the applied analogue input voltage. 45. An analogue-to-digital converter including a plurality of mutually-similar voltage conversion stages connected in series so that the output of one stage provides an input to the next stage, each stage including a storage capacitor selectively connectible to the input of the stage for storing an input voltage of the stage and also including an amplifier element connected or selectively connectible between the storage capacitor and the output of the stage for delivering an output voltage of the stage which is dependent on the stored input voltage, wherein in at least one stage, other than the first stage, of the series the storage capacitor capacitance is smaller than the storage capacitor capacitance of the immediately-preceding stage and/or the width of an input transistor of the amplifier element is smaller than the width of the input transistor of the amplifier element of the immediately-preceding stage. 46. A voltage storage circuit as claimed in claim 16, wherein the potential tracking device includes a current source, connected to the said first current-path electrode for causing the first current-path electrode potential to track the control electrode potential, and active follower means connected operatively between the said first and second current-path electrodes for causing the second current-path electrode potential to track the first current-path electrode potential. 47. A voltage storage circuit as claimed in claim 46, wherein the said electronic input device is an FET input transistor and the said control electrode is the gate electrode of the FET input transistor, the first current-path electrode is the source electrode of the FET input transistor, the said second current-path electrode is the drain electrode of the FET input transistor, and the said controllable current path is provided by the drain-source channel of the FET input transistor. 48. A voltage storage circuit as claimed in claim 47, wherein the said active follower means comprise a cascoding FET transistor connected with its drain-source channel in series with the drain-source channel of the said FET input transistor so that the source electrode potential of the cascoding transistor tracks the gate electrode potential thereof and also comprise a bias generator connected operatively between the source electrode of the FET input transistor and the gate electrode of the cascoding transistor for maintaining therebetween a substantially constant potential difference. 49. A voltage storage circuit as claimed in claim 46, wherein the said amplifier element is made up of first and second substantially identical circuit portions, the first portion including the said input device and the said active follower means and the second portion including the said current source. 50. A voltage storage circuit as claimed in claim 16, wherein the said switching electrode potential is derived from the said output signal. 51. A voltage storage circuit as claimed in claim 50, wherein the said switch driving means are connected operatively with the said output terminal and are operable, in dependence upon a switching signal received thereby, to apply to the said switching electrode either an ON potential, for maintaining the said input switch element in its ON condition, or an OFF potential, for maintaining the said input switch element in its OFF condition, the said ON and OFF potentials being each substantially fixed in relation to the said output terminal potential but differing from one another by a predetermined amount.

52. A voltage storage circuit as claimed in claim 51, having respective first and second biassing lines connected operatively to the said output terminal so as to be at potentials that are respectively fixed in relation to the output terminal potential, the second biassing line potential being equal to one of the said ON and OFF potentials and the potential difference between the said first and second biassing lines being greater than or equal to the said predetermined amount, wherein the said switch driving means include a bootstrap capacitor one plate of which is connected to the said switching electrode for providing the said switching electrode potential and also include connecting means connected with both plates of the bootstrap capacitor and with the said biassing lines and switchable, when the switching electrode potential is to be changed from the said one of its ON and OFF potentials to the other of those potentials, from a charging configuration, serving to connect the said one plate of the bootstrap capacitor to the said second biassing line whilst connecting the other plate thereof to the said first biassing line, to a floating configuration serving to isolate the said one plate from the second biassing line whilst connecting the said other plate to the said second biassing line, thereby to cause the potential at the said one plate to be changed from the second biassing line potential to a potential differing therefrom by the said predetermined amount. 53. A voltage storage circuit as claimed in claim 51, having respective first, second and third biassing lines connected operatively to the said output terminal so as to be at potentials that are respectively fixed in relation to the output terminal potential, the third biassing line potential being equal to one of the said ON and OFF potentials and the potential difference between the said first and second biassing lines being greater than or equal to the said predetermined amount, wherein the said switch driving means include a bootstrap capacitor one plate of which is connected to the said switching electrode for providing the said switching electrode potential and also include connecting means connected with both plates of the bootstrap capacitor and with the said biassing lines and switchable, when the switching electrode potential is to be changed from the said one of its ON and OFF potentials to the other of those potentials, from a charging configuration, serving to connect the said one plate of the bootstrap capacitor to the said third biassing line whilst connecting the other plate thereof to the said first biassing line, to a floating configuration serving to isolate the said one plate from the third biassing line whilst connecting the said other plate to the said second biassing line, thereby to cause the potential at the said one plate to be changed from the third biassing line potential to a potential differing therefrom by the said predetermined amount. 54. A voltage storage circuit as claimed in claim 51, wherein the said electronic input switch element is a MOSFET transistor and one of the said ON and OFF potentials is substantially the same as the said output terminal potential. 55. A voltage storage circuit as claimed in claim 16, wherein the said amplifier element has a gain of substantially unity. 56. An analogue-to-digital converter as claimed in claim 45, having N such stages, wherein in each of the second to nth stages of the converter, where 2≦n≦N, the storage capacitor of the stage has a capacitance that is reduced, relative to the capacitance of the comparable storage capacitor of the immediately-preceding stage, by a first scaling factor that is constant throughout those second to nth stages. 57. An analogue-to-digital converter as claimed in claim 56, wherein the voltage gain of each stage is 2 and said first scaling factor is approximately 2.

58. An analogue-to-digital converter as claimed in claim 45, having N such stages, wherein in each of the second to nth stages of the converter, where 2≦n≦N, the amplifier element input transistor of the stage is of a channel width that is reduced, relative to the channel width of the comparable amplifier element input transistor of the immediately-preceding stage, by a second scaling factor that is constant throughout those second to nth stages. 59. An analogue-to-digital converter as claimed in claim 58, wherein the voltage gain of each stage is 2 and said second scaling factor is approximately 2. 60. An analogue-to-digital converter as claimed in claim 45, wherein said amplifier element of each stage has current control means connected to said input transistor for causing a controlled working current to flow therethrough when the converter is in use, the current control means being such that the magnitude of the controlled working current for said one stage is smaller than that for the immediately-preceding stage of the series. 61. An analogue-to-digital converter as claimed in claim 60, having N such stages, wherein in each of the second to nth stages of the converter, where 2≦n≦N, said controlled working current for the stage is reduced, relative to said controlled working current in the immediately-preceding stage, by a third scaling factor that is constant throughout those second to nth stages. 62. An analogue-to-digital converter as claimed in claim 61, wherein the voltage gain of each stage is 2 and said third scaling factor is approximately 2. 63. An analogue-to-digital converter as claimed in claim 45, wherein each stage includes:

comparator means operable to compare said input voltage of the stage with a predetermined comparison potential and to produce a digital data signal having a first value if the result of the comparison is that the input voltage is greater than or equal to the comparison potential, a second value if the result of the comparison is that the input voltage is less than minus the comparison potential, and a third value in all other cases; and

conversion voltage generating means, connected to said comparator means for receiving therefrom said digital data signal produced thereby, and including said storage capacitor and said amplifier element of the stage, for determining said output voltage of the stage in dependence upon the value of the received digital data signal such that the output voltage is twice the input voltage less a predetermined reference potential when the digital data signal has said first value, and is twice the input voltage plus said predetermined reference potential when the digital data signal has the second value, and is twice the input voltage when the digital data signal has the third value;

the converter further comprising data processing means connected for receiving the respective digital data signals produced by the comparator means of the stages and operable to process those signals to produce a digital output word representative of the input voltage of the first stage. 64. An analogue-to-digital converter as claimed in claim 44, wherein:

each said storage capacitor has a first plate which is the plate thereof that is connectable, by said switching means, to said input terminal of the amplifier element in the voltage storage circuit to which that storage capacitor belongs; and

for each said voltage storage circuit:

a switch element of the input sampling means that is connected to the amplifier element input terminal, and switch elements of said switching means that are connected to said first plates of the storage capacitors, are formed in one or more wells of the opposite conductivity type to that of the surrounding material of a substrate in which the voltage storage circuit concerned is formed, there being means for causing the or each well potential to be substantially fixed in relation to the output terminal potential of the amplifier element in the voltage storage circuit concerned. 65. An analogue-to-digital converter as claimed in claim 44, wherein said input sampling means include, for each said voltage storage circuit:

an electronic input switch element, operative in dependence upon the potential at a switching electrode thereof, the voltage storage circuit concerned further including switch driving means connected to cause the switching electrode potential to track the input terminal potential when the element is in its ON condition, thereby maintaining the switching electrode potential substantially fixed in relation to the input terminal potential, and operable to cause the switching electrode potential to change, relative to the input terminal potential, such that the element is changed from its ON condition to its OFF condition; and

input potential maintaining means, interposed between said input terminal and the input side of said input switch element, for maintaining the input-side potential of said electronic input switch element, after the element is changed to the OFF condition, substantially fixed in relation to the potential of said input terminal. 66. An analogue-to-digital converter as claimed in claim 65, wherein said input potential maintaining means comprise, for each voltage storage circuit, a further switch element connected in series with said input switch element and operable, after said input switch element has been changed to the OFF condition, to isolate the input side of that element from said input terminal. 67. An analogue-to-digital converter as claimed in claim 65, wherein said input potential maintaining means further comprise, for each voltage storage circuit, a feedback switch element connected between said amplifier element and the input side of said input switch element and operable, while the input side of that element is isolated, to apply thereto a potential derived from the potential of said input terminal.