A saddled and wrapped stack capacitor dram and a method thereof are provided. The dram of the invention includes three factors in increasing the effective area for a capacitor. One is a storage poly layer comprising a first poly layer and a second poly layer, which is formed thick in a region over a field oxide layer through two steps; another is a spacer which is formed through an etchback technique for an oxide layer coated on another oxide layer being patterened to selectively remove the storage poly layer, and the spacer maximizes the size of the storage poly; another is an undercut which is formed in boundary regions on an upper oxide layer, on which a plat plate poly material is coated and wrapped.
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9. A semiconductor memory device, comprising:
a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon; a first capacitive electrode layer formed on said insulating layer, said first capacitive electrode layer having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion; a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said dielectric layer and said insulating layer.
1. A stacked capacitor dram formed on a substrate comprising a plurality of memory cells on said substrate, each of said cells comprising a charge transfer transistor and a stacked capacitor, said stacked capacitor comprising a laminated insulating layer having a plurality of laminae disposed on a portion of the substrate, said insulating layer terminating in a side edge, a storage polysilicon layer for said capacitor including a first portion disposed on said insulating layer and a second portion extending beyond the side edge thereof, said second portion extending to and overlying a gate of said charge transfer transistor, said first portion having a greater thickness than said second portion, said polysilicon layer terminating in a side edge, and including a conductive layer separated from said polysilicon layer by a dielectric layer, said conductive and dielectric layers extending over an upper surface of said polysilicon layer, along said side edge thereof, and beneath a section of said first portion of said polysilicon layer, an edge of a first, uppermost lamina of said insulating layer being disposed beneath and inwardly of said side edge of said polysilicon layer thereby providing a space between a bottom surface portion of said polysilicon layer thereby providing a space between a bottom surface portion of said polysilicon layer and a surface portion of a second lamina of said insulating layer beneath said uppermost lamina, and said space being filled with the portions of said conductive and dielectric layers extending beneath said polysilicon layer whereby said conductive and dielectric layers do not surround said storage polysilicon layer.
2. A stacked capacitor as in
3. The dram according to
4. The dram according to
5. The dram according to
6. The dram according to
7. The dram according to
8. The dram according to
10. The semiconductor device of
electrode. 16. A semiconductor memory device, comprising: a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon, wherein said insulating layer is a laminated insulating layer comprising a plurality of laminae; a first capacitive electrode layer formed on said insulating layer, said first capacitive electrode layer having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion; a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said dielectric layer and said insulating layer. 17. A stacked capacitor as in claim 16, wherein said insulating layer comprises upper, center and lower lamina. 18. A stacked capacitor as in claim 17, wherein an insulating material of said center lamina is different than an insulating material of said upper lamina. 19. A stacked capacitor as in claim 18, wherein said insulating material of said center lamina is nitride and said insulating material of said upper lamina is oxide. 20. A stacked capacitor as in claim 19, wherein said insulating material of said lower lamina is oxide. 21. A stacked capacitor as in claim 19, wherein said comprising a conductive member disposed beneath said first capacitive electrode layer, and wherein said center lamina of said insulating layer insulates a portion of said second capacitive electrode layer extending beneath said first capacitive electrode layer from said second capacitive electrode layer. 22. A stacked capacitor as in claim 9, wherein said partial lower surface defines an undercut extending over said gate electrode. 23. A stacked capacitor as in claim 9, wherein said partial lower surface defines an undercut extending over a word line. 24. A stacked capacitor as in claim 9, having at least one of a partial lower surface defining a first undercut extending over said gate electrode, and a partial lower surface defining a second undercut extending over a word line. 25. A stacked capacitor as in claim 9, having a partial lower surface defining a first undercut extending over said gate electrode, and a partial lower surface defining a second undercut extending over a word line. 26. A semiconductor memory device, comprising: a semiconductor substrate having a gate electrode formed thereon with said gate electrode having an insulating layer formed thereon; a first capacitive electrode layer having a first portion formed on said insulating layer and a second portion having an edge portion spaced apart from said insulating layer thereby exposing a partial lower surface of said first capacitive electrode layer at said edge portion; a dielectric layer formed on said first capacitive electrode layer, said dielectric layer wrapping around and under said edge portion and substantially along said partial lower surface of said first capacitive electrode layer; and a second capacitive electrode layer formed on said dielectric layer, said second capacitive layer wrapping around and under said edge portion, whereby said second capacitive electrode layer extends between said dielectric layer and said insulating layer. 27. A stacked capacitor as in claim 26, wherein said first portion of said first capacitive electrode layer is substantially uniform in thickness. 28. A stacked capacitor as in claim 26, wherein said second portion of said first capacitive electrode layer is substantially uniform in thickness. 29. A stacked capacitor as in claim 28, said first portion having a greater thickness than said second portion. 30. A stacked capacitor dram formed on a substrate comprising a plurality of memory cells on said substrate, each of said cells comprising a charge transfer transistor and a stacked capacitor, said stacked capacitor comprising: a laminated insulating layer terminating in a side edge; a storage polysilicon layer for said capacitor including a first portion disposed on said insulating layer and a second portion extending beyond the side edge thereof, said second portion extending to and overlying a gate of said charge transfer transistor, said polysilicon layer terminating in a side edge, and including a conductive layer separated from said polysilicon layer by a dielectric layer, said conductive and dielectric layers extending over an upper surface of said polysilicon layer, along said side edge thereof, and beneath a section of said polysilicon layer, an edge of said insulating layer being disposed beneath and inwardly of said side edge of said polysilicon layer thereby providing a space between a bottom surface portion of said polysilicon layer and a top surface portion of said insulating layer, and said space being filled with the portions of said conductive and dielectric layers extending beneath said polysilicon layer whereby said conductive and dielectric layers do not surround said storage polysilicon layer. 31. A stacked capacitor as in claim 30, said laminated insulating layer comprising a plurality of laminae. 32. A stacked capacitor as in claim 31, wherein said insulating layer comprises upper, center and lower lamina. 3. A stacked capacitor as in
said space between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defining a first undercut overlying a word line, and said space between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defining a second undercut overlying the gate of said charge
transfer transistor. 40. A stacked capacitor as in claim 30, having said space between the bottom surface portion of said first portion of said polysilicon layer and the top surface portion of said insulating layer, defining a first undercut overlying a word line, and said space between the bottom surface portion of said second portion of said polysilicon layer and the top surface portion of said insulating layer, defining a second undercut overlying the gate of said charge transfer transistor. 41. A stacked capacitor as in claim 30, wherein said first portion of said polysilicon layer is substantially uniform in thickness. 42. A stacked capacitor as in claim 41, wherein said second portion of said polysilicon layer is substantially uniform in thickness. 43. A stacked capacitor as in claim 42, said first portion having a greater thickness than said second portion. |
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This invention relates to DRAM(Dynamic Random Access Memory) cells and a method for manufacturing them, and more particularly to a stacked capacitor DRAM cell which can obtain a high-capacitance without the increment of capacitor area in a semiconductor device. Recently, in the field of DRAM technology, the effort of minimizing the chip size has been completed, while the capacitance value needed for each cell has been maintained. According to such a an n-type well 3 are formed on a p-type substrate 1.
Hereinafter, the preferred embodiment of this invention will now be described by setting the p-well on the basis of describing the embodiment. For the n-well, only the type of impurities is changed.
Impurities of p-type are injected into a region of the p-type well 2 which will be a field region in the well 2, and then a field oxide layer 4 is grown. From this resultant, a channel stop region of p+ -type is formed (FIG. 5B).
As shown in FIG. 5C, a gate oxide layer 4' is grown on regions to be active regions by way of a conventional way, and impurities are injected in order to control a threshold voltage of a transistor. A poly layer 5 is then deposited over the substrate, and a gate poly oxide layer 6 is grown on the poly layer. The layers 4', 5 and 6 are selectively etched out employing a conventional photo-lithographic technique, and the layer 5 results in a gate poly layer.
FIG. 5D shows an oxide spacer 7 which is formed in the sidewall of the poly-silicon layer 5. Ion impurities of n-type are then injected into the p-well so as to form the regions which come to be a source S and a drain D of a transistor.
Thereafter, as shown in FIG. 5E, an oxide layer 8 (the lower oxide layer), a nitride layer 9 and an oxide layer 10 are formed in sequence. The layers 8,9,10 are formed by the method of Chemical Vapor Deposition, and the thickness of each layer is about 1000 Å. A first poly-silicon layer 11 is then coated with the thickness of about 3000 Å.
The layers 8,9 and 10 play the role of the inter-poly (laminated) insulating layer between the gate poly layer 5 and the first poly layer 11. The first poly layer may be formed with the poly doped initially with the n+ -type impurities, or n+ -type impurities may be doped after depositing the non-doped poly-silicon.
Referring now to FIG. 5F, the first poly layer 11 is selectively etched out, employing a saddle mask, except the poly-silicon coated over the upper surface side of the field oxide layer 4. During this process, the saddle mask causes the etched surface of the storage poly layer to be very rough so that this condition makes the effective area for the capacitor increase in a large scale. That is, the increment of the surface area with the curved surface states increases the quantity of the storage poly with respect to the another deposition of a poly-silicon layer.
Buried contacts 12 are then formed and the buried contact leads the source to be connected with a second poly which will be an electrode of a capacitor. The order of forming the first poly layer and the contact can be carried out reversely.
After that, as shown in FIG. 5G, the second poly layer 11' is deposited with about 2500 Å thickness over the entire surface of the p-well, and an oxide layer 14 is coated by the thickness of about 1500-3000 Å, by way of CVD technique, on the second poly layer. As above indicated, owing to the rough, etched surface of the poly layer 11, the upper surface of the portion of the second poly layer 11' overlying the first poly layer 11 is also rough.
FIG. 5H shows the next step. The reference numeral 13 is a poly storage layer consisting of the first and second poly layer 11 and 11', and hereinafter the first and second poly-silicon layer (laminate) 11, 11' will be represented as the poly storage layer and a single hatching.
Employing a photoresist mask, the oxide layer 14 is selectively etched out per unit of a cell. In this etching process, the etching pattern of the oxide layer 14 is restricted by the resolution capability of the photoresist. Accordingly, the size of the etching pattern must be at least equal or large than the resolution capability. According to the present invention an oxide spacer is employed in order to maximize the capacitance. After forming the etching pattern of the storage poly, an oxide layer is coated on the oxide layer 14. The oxide spacer 15 is then formed through the etch back technique. The size of the spacer is determined with the magnitude of the storage layer to be remained, that is, with the capacitance of a capacitor according to a device characteristic.
In FIG. 5I, the exposed storage poly layer 13 is removed by employing the remaining oxide layer 14 and oxide spacer 15 as a mask. This etching process exposes the portions of the oxide layer 10 below the removed storage layer. Subsequently, using the isotropic technique the oxide layers 10, 14 are removed. The isotropic etching makes the oxide layer 10 (the uppermost lamina of the laminated insulating layer 8-9-10) have undercut surfaces because the boundary portions of the oxide layer 10 is etched out into apertures by the isotropic properties. Therefore, the exposed portions of the storage poly are increased, and the storage capability for charges is also increased.
The degrees of the undercut depend on the magnitude of capacitance to be obtained, and these are controlled by the difference of the thickness between the oxide layer 10 and 14. If the layer 14 is thicker than the layer 10, the degrees of the etching in the layer 10 may increase. The removal of the layer 10, 14 may be carried out separately.
The protection by the nitride layer 9 (the lamina exposed by the undercutting of the layer 10) for the oxide layer 8 prevents the short between the gate poly layer 5 and a plate poly layer 17 represented in FIG. 5J from occurring.
Referring now to FIG. 5J, a dielectric layer 16 for a capacitor is formed along the entire exposed surface of the storage poly layer 13. The plate poly layer 17 is then deposited over the p-well by about 1500 Å, and then the plate poly layer 17 is selectively removed as shown in FIG. 5J.
Then a plate poly oxide layer 18 is grown by oxidizing the plate layer 17 so as to have the thickness of about 1000 Å.
As shown in FIG. 5K, the BPSG(Boron Phosphorus Silicate Glass) 19 is deposited on the plate poly oxide layer 18 by the low temperature oxidation technique. A BPSG flow is then carried out for the planarization of the surface. Employing a mask, a bit line contact is formed and a policide layer 20 is filled therein.
After the above processes, in FIG. 5L, the BPSG 21 is coated and the glass 21 is flowed. A contact for metal line is then formed using a mask and a metal layer is deposited. The coated metal layer is selectively removed employing a mask.
The DRAM cell fabricated through the above-mentioned processes has a wide effective area for the capacitor as shown be in FIG. 2 and FIG. 3, because the storage poly-silicon for capacitor is formed with an enough thickness over the field oxide layer 4, as well as the exposed area of the storage poly layer 13 is increased by causing providing the undercut just below the boundary region of the storage layer to bring about; so that the effective area of the capacitor results in wide area. Furthermore, with the employment of the oxide spacer, the magnitude of capacitance is increased and controlled with the dimensions of the oxide spacer.
The effects of the DRAM cell manufactured according to the present invention are as follows.
Since the storage poly layer to be the capacitor electrode is formed not only thick in the region over the field oxide layer but also shallowly in the contact region of the bit line, the effective area of the capacitor increases and the topology of the bit line contact area is improved.
When the storage poly is removed, the gap between the remaining storage poly layer is narrow as much as possible by using the oxide spacer, so that the remaining area of the storage poly layer is wide and the effective area of the capacitor is increased once more.
The third factor which increases the capacitor area is the undercut phenomenon which breaks down in the region just below the boundary region of the storage poly layer.
Accordingly, since the effective area for the capacitor is enormously increased through the above-mentioned three factors according to the invention, the area of the DRAM decreases, and this result makes the manufacturing of the VLSI possible.
This invention is in no way limited to the example described hereinabove. Various modifications of the disclosed embodiment, as well as other embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
Chung, Tae-Young, Chin, Dae-je
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