Sense circuit for reading data stored in nonvolatile memory cells

Abstract

A sense circuit for reading eprom and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC_max. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a circuit for reading the information stored in ROM and EPROM type memories according to a differential sensing mode and, in particular to an improved circuit for generating an offsetting current for discriminating between the currents which flow through a certain cell of the memory array which has been selectively addressed for reading and a virgin reference cell, according to a current offset sensing mode.

Among semiconductor nonvolatile memories, EPROM memories represent one of the most advanced field of integration in silicon. Starting from nowadays common 1 megabit devices, new devices with a capacity of up to 4 megabit have been presented lately and new ambitious goals are announced.

Together with an ever increasing packing density, the memory market requires improved performances in terms of access time, write time and power consumption. The reduction of the size of the devices poses serious problems to the achievement of these aims. In particular, the access time during a reading phase is penalized by a consequent reduction of the actual current through the memory cell and an increased influence of parasitic electric factors of the integrated structure of the cells. For these reasons, the circuits used for reading the information stored in the cells must possess an enhanced precision and reliability.

The article entitled "L'amplilicatore di Lettura nei Dispositivi di Memoria EPROM" by G. Compardo, M. Dallabora and D. Novosel, published on the journal "Alta Frequenza" Vol. LVII--No. 6--July-August 1988, contains a comprehensive review of the different sense circuits which are commonly used. The relevant content of this article is intended to be incorporated herein by express reference thereto.

Basically, the architecture of a differential type sense circuit are by far more precise and less sensitive to the effects of "process spread", temperature and supply voltage variations, by treating them essentially as common mode contributions. On the other hand, there are theanyone current unbalance row of memory cells of the array which is selected for reading, during a transient.

Normally, the reference column line, REFERENCE BITLINE, serves a certain number of column lines, MATRIX BITLINE, of the array and to these is adjacently formed on the silicon chip so as to make as similar as possible the voltages present on the gate of the reference cell and on the gate of a selected cell of the array also during transients, the latter having a nonnegligeable duration because of the RC value of a row of the array. This topographic closeness between these lines further enhances a maximum geometrical identity of the relative reference cells and array cells.

With reference to the circuit shown in FIG. 5, n1, n3, n4 and n5 are cells (transistors) electrically equivalent to anyone memory cell of the memory array programmed in an ON-condition. According to this first preferred embodiment, the circuit is provided also with two compensation transistors n2 and n6, which are functionally unnecessary, but serve advantageously as compensating elements when the array cells, programmed in an-OFF condition (written cells) are not in a perfectly cut-off condition, but which in practice begin to conduct a certain current, in the order microampers, beyond a certain level of the driving voltage applied thereto. This condition is "replicated", by analogy, also by said transistors (cells) n2 and n6, which are electrically equivalent to any other memory cell of the array programmed in an OFF-condition, thus obtaining as a result a perfect compensation of the current which may be conducted by written memory cells and which would disturb the process of unbalancing the currents which is performed by the circuit of the invention, thus introducing a certain limitation toward the maximum value of the driving voltage (VCC_max) by "bending" the current characteristic of the reference branch of the circuit toward the current characteristic of a written (OFF) cell until crossing it. As shown, n1, n2 and n6 are driven by said supplementary array row, DUMMY ROW, and are topologically near, on the silicon chip, to the reference column line: REFERENCE BITLINE and to the respective array column lines: MATRIX BITLINE. This means that during a transient the voltages on the gates of the reference cell and of the array cell (not shown in FIG. 5), as well as on the gates of the transistors n1, n2 and n6, are very similar and may be considered equal to each other.

By supposing initially to neglect the contribution given by the optional compensation transistors n2 and n6 and by observing that, by assuming that all the cells (array, reference and n1) are in a saturation condition, the current of the cell n1 is equal in any instant to the current flowing through any selected ON-programmed cell of the array, because these currents depend exclusively on the respective gate voltages, which are equal in both cells also during a transient. The current I_on generated by the cell n1, which is identical to the current flowing through the selected cell of the array which must be read, is mirrored by the current mirror formed by the transistors p1 and p2 into the right hand branch of the mirror and it is divided into two identical semi-currents by means of the n-channel current mirror formed by the transistors n3, n4 and n5, all having the same size, and it is further delivered to the column line of the array side (MATRIX BITLINE). By defining the so-obtained current: I_offset ; and having neglected for the moment the contribution of the cell n2, the following relation holds:

I_on =2*I_offset.

The effect of unbalancing the currents of the two input branches (MATRIX BITLINE and REFERENCE BITLINE, respectively) of the differential sense circuit so obtained, is from both a static and a dynamic point of view, substantially similar to the effect obtained in a load-unbalance current-unbalance type, sense circuit, where the size of the load of the reference side is twice the size of the load of the array side, thus producing an operating characteristic similar to the one depicted in FIG. 2. The unbalancing circuit is, on the other hand, exempt of the drawbacks of a load-unbalance conventional current-unbalance circuit. Any limitation toward the maximum value of the driving voltage (VCC_max) is effectively eliminated by means of the optional compensation transistors n2 and n6, which are, as already said, equivalent to a programmed array cell, i.e. have a high threshold, as a cell in an OFF-condition, and they are driven by the supplementary row DUMMY ROW, of the array as the cell n1. The drain of the transistor n6 is connected to the reference column line: REFERENCE BITLINE, while the eventual current contribution of the transistor (cell) n2, which is substantially connected in common with the first transistor n1, and which will essentially be identical to the current eventually carried by a written memory cell (OFF-programmed cell) of the array, will be summed with the current generated by n1, thus producing a sum current (I_on +I_off) of the currents generated by n1 and n2, respectively.

The result is easily analyzed as follows: ##EQU2##

The dynamic characteristics of operation of the current generating circuit of FIG. 5 are shown in the diagram of FIG. 6 and the static characteristics of operation of the circuit shown in the diagram of FIG. 7 make evident the advantages which are achieved by the circuit of the invention, in comparison either with a load-unbalance-type current-unbalance type architecture of the sense circuit, represented by the wide range of the operating voltage, substantially unlimited toward the VCC_max, or the current-offset-type circuits of prior art architecture, represented by the freedom from error in the transient response, which entails a smaller access time of the memory array.

In accordance with an alternative embodiment of the invention, the current generating circuit for the sense circuit of the invention may also be realized in the form shown in the diagram of FIG. 8. The diagram is similar to that of FIG. 5, and therein the current contribution given by the cell n2 at the moment of generating the unbalancing current lacks completely. As already seen before, the effect which is obtained in terms of offsetting the currents in the two branches: MATRIX BITLINE and REFERENCE BITLINE, may be considered similar to the effect occurring in a loadcurrent-unbalancetype sense circuit. Although, if the effect of the cell n6', connected as shown in the figure to the REFERENCE BITLINE, is considered too, and assuming the transistors n3, n4 and n5 also electrically equivalent to array cells, programmed in an ON-condition, it is evident that upon an increase of the VCC, the gate voltage of the transistor n6' will assume a value sufficiently high to drive a current on the reference column line, REFERENCE BITLINE, having an intensity, which though lower than that of an eventual current carried by an array cell, programmed in an OFF-condition (written cell) during reading, is sufficient to shift toward a higher voltage the point wherein the reference current I_ref characteristic crosses the current I_off of an array cell, programmed in an OFFcondition (written cell), thus increasing the VCC_max limit of operation of the circuit.

In the diagram of FIG. 9 the dynamic characteristics of the circuit of FIG. 8 are depicted, which clearly appear even further improved in comparison with the dynamic characteristics of the circuit of FIG. 5, as will be remarked later.

In the diagram of FIG. 10, the static operation characteristics of a reading circuit employing the current generating circuit of FIG. 8 are depicted. The mentioned increased limit of the operation range toward VCC_max may be recognized by the fact that the reference current I_ref curve no longer crosses the I_off I_matoff current curve of an OFF-programmed cell, notwithstanding that the voltage VCC become larger than 10 V.

The current generating circuit according to the FIG. 8 embodiment, does not provide a static operation performance comparable to that of the circuit made in accordance with the FIG. 5 embodiment which, as shown before, has no limitation toward VCC by virtue of the contribution of transistors n2 and n6. The circuit of FIG. 8 is nevertheless simpler to implement because the required supplementary row, DUMMY ROW, drives a single transistor instead of three transistors and therefore has a reduced capacitive load, positively reflecting upon the dynamic response of the current generating circuit. In fact, by comparing the dynamic characteristics of FIG. 6 and 9, it may be observed that, for the circuit of FIG. 8, the characteristic curves of the reference current I_ref and of the current I_on of an ON-programmed cell, diverge more rapidly during a transient than those of the circuit of FIG. 5.

Claims

1. A sense circuit for reading eprom and/or ROM type memory cells, programmable in an ON-condition or in an OFF-condition, organized in an array of columns and rows of cells, selectively addressable through row lines and bit lines, employing a differential amplifier for discriminating the conductivity of a selected array cell from the conductivity of a reference cell in an ON-condition, functionally connected in series to a first branch and to a second branch, respectively, of an input circuit of said differential amplifier, between a supply rail and ground, and offsetting means, capable of causing a discriminating unbalancing between the values of the currents flowing through said two branches of the input circuit of the differential amplifier, between the supply rail and ground,

characterized by the fact that said offsetting means is an offsetting current generating circuit formed by

at least a first transistor (n1) having electrical characteristics equivalent to the electrical characteristics of anyone cell of said memory cells programmed in an ON-condition, and having a gate to which a driving voltage essentially identical to the voltage applied to a gate of a selected array cell to be read is applied for generating a first current (I_on) substantially identical to the current flowing through a selected array cell which is programmed in an ONcondition ON condition;

a first current mirror capable of mirroring said first generated current (I_on) in an output branch of said first mirror;

a second current mirror, connected to said output branch of said first current mirror and capable of splitting said first current (I_on) into two identical semicurrents, one of which (_offset I_offset ) is forced through said first branch of said input circuit of said differential amplifier comprising said selected array cell to be read thus causing said discriminating current unbalance;

said driving voltage of said first transistor being provided by means of a supplementary row of cells, which supplementary row is decoded at every reading and which replicates, during transients, the electrical behaviour of the row of the array which includes said selected cell to be read.

2. A sense circuit for reading eprom and/or ROM type memory cells, programmable in an ON-condition or in an OFF-condition, organized in an array of columns and rows of cells, selectively addressable through row lines and bit lines, employing a differential amplifier for discriminating the conductivity of a selected array cell from the conductivity of a reference cell in an ON-condition, functionally connected in series to a first branch and to a second branch, respectively, of an input circuit of said differential amplifier, between a supply rail and ground, and offsetting means capable of causing a discriminating unbalancing between the values of the currents flowing through said two branches of the input circuit of the differential amplifier, between the supply rail and ground,

characterized by the fact that said offsetting means is an offsetting current generating circuit formed by at least a first transistor (n1) having electrical characteristics equivalent to the electrical characteristics of anyone cell of said memory cells programmed in an ON-condition, and having a gate to which a driving voltage essentially identical to the voltage applied to a gate of a selected array cell to be read is applied for generating a first current (I_on) substantially identical to the current flowing through a selected array cell which is programmed in an ONcondition ON condition;

a second transistor (n2) having electrical characteristics equivalent to the electrical characteristics of anyone of said memory cells programmed in an OFF-condition, connected substantially in parallel with said first transistor (n1) for generating an additional current (I_off) which is substantially identical to the current flowing through a selected array cell programmed in an OFF-condition;

a first current mirror capable of mirroring a sum current (I_on +I_off) of said currents generated by said first and said second transistors in an output branch of said first mirror;

a second current mirror, connected to said output branch of said first mirror and capable of splitting said sum current into two identical semicurrents, one of which (I_offset) is forced through said first branch of said input circuit of said differential amplifier which includes said selected array cell to be read, thus determining said discriminating current unbalance;

a third transistor (n6), having the same characteristics of said second transistor (n2), connected into said second branch of said input circuit including said reference cell and having a gate to which a driving voltage essentially identical to the voltage which is applied to the gate of said selected cell to be read is applied for forcing a current identical to said additional current (I_off) through said second branch of said input circuit including said reference cell;

said driving voltage of said first, second and third transistors, being provided by a supplementary row of cells which is decoded at every reading and which replicates, during transients, the electrical behaviour of the row of the array which contains said selected cell to be read;

the reading conditions of a memory cell programmed in an ON-condition and of a memory cell programmed in an OFFcondition being represented, respectively, by the disequalities between the currents which flow through said second branch containing said reference cell (I_ref) and said first branch containing said cell to be read (I_mat): I_ref <I_mat and I_ref >I_mat, respectively, and which are detected by means of said differential amplifier, being satisfied both by the univocal condition: I_on >I_off, which is intrinsically true.

3. A sense circuit for reading eprom and/or ROM type memory cells, programmable in an ON-condition or in an OFF-condition, organized in an array of columns and rows of cells, selectively addressable through row lines and bit lines, employing a differential amplifier for discriminating the conductivity of selected array cell from the conductivity of a reference cell in an ON-condition, functionally connected in series to a first branch and to a second branch, respectively, of an input circuit of said differential amplifier, between a supply rail and ground, and offsetting means capable of causing a discriminating unbalancing between the values of the currents flowing through said two branches of the input circuit of the differential amplifier, between the supply rail and ground,

characterized by the fact that said offsetting means is an offsetting current generating circuit formed by

at least a first transistor (n1) having electrical characteristics equivalent to the electrical characteristics of anyone cell of said memory cells programmed in an ON-condition, and having a gate to which a driving voltage essentially identical to the voltage applied to a gate of a selected array cell to be read is applied for generating a first current (I_on) substantially identical to the current flowing through a selected array cell which is programmed in an ON-condition;

a first current mirror capable of mirroring said first generated current (I_on) in an output branch of said first mirror;

a second current mirror, connected to said output branch of said first current mirror and capable of splitting said first current (I_on) into two identical semicurrents, one of which (I_offset) is forced through said first branch of said input circuit of said differential amplifier comprising said selected array cell to be read thus causing said discriminating current unbalance;

a second transistor (n6'), having electric characteristics equivalent to the characteristics of anyone cell of said memory cells programmed in an OFF-condition, connected into said second branch of said input circuit which contains said reference cell and having a gate to which a driving voltage of a fractionary value in respect to the voltage of said supply rail, is applied for forcing a current (I_off I'_offset ) of fractionary value in respect to the current which flows through a selected array memory cell programmed in an OFF-condition, condition, through said second branch of said input circuit which contains said reference cell;

said driving voltage of said first transistor being essentially identical to the voltage applied to the gate of the selected array cell to be read and being provided by a supplementary row of cells, which is decoded at every reading and which replicates during transients, the electrical behaviour of the row of the array which contains said selected cell to be read.

4. A read circuit for determining the state of a matrix nonvolatile memory cell, which, in response to a read signal, generates a read current equal to an on current if programmed in an on state and equal to an off current that is less than said on current if programmed in an off state comprising:

a matrix line coupled to said memory cell and operable to conduct a unidirectional matrix current that equals the sum of said read current and an offset current;

a reference line operable to conduct a reference current that is greater than said offset current;

a reference circuit coupled to said reference line and operable to generate said reference current in response to said read signal;

an offset circuit coupled to said matrix line and operable to generate said offset current in response to said read signal; and

a differential amplifier coupled between said matrix and reference lines and operable to compare said matrix current with said reference current. 5. The read circuit of claim 4 wherein said reference

current is substantially equal to said on current. 6. The read circuit of claim 4 wherein said reference current substantially equals the sum of said on and off currents. 7. The read circuit of claim 4 wherein said reference current substantially equals the sum of said on current and a fraction of said off current. 8. The read circuit of claim 4 wherein said offset current equals a fraction of said on current. 9. The read circuit of claim 4 wherein said offset current substantially equals one half of said on current. 10. The read circuit of claim 4 wherein said offset current equals a fraction of the sum of said on and off

currents. 11. The read circuit of claim 4 wherein said offset current substantially equals one half of the sum of said on and off currents. 12. The read circuit of claim 4 wherein said offset circuit comprises a dummy row of nonvolatile memory cells that are operatively coupled to receive said read signal. 13. A method for reading a nonvolatile memory cell, comprising:

generating in response to a read signal a matrix current that equals the combination of a read current and an offset current;

generating in response to said read signal a reference current, which, during a transient period following activation of said nonvolatile memory cell, is less than or equal to said matrix current when said cell is in an on state, and which is greater than or equal to said matrix current when said cell is in an off state; and

comparing said matrix current to said reference current. 14. The method of claim 13 wherein said reference current is substantially

equal to the on current of said memory cell. 15. The method of claim 13 wherein said reference current is substantially equal to the sum of the on and off currents of said memory cell. 16. The method of claim 13 wherein said reference current is substantially equal to the sum of the on current and a fraction of the off current of said memory cell. 17. The method of claim 13 wherein said offset current is equal to a fraction of the on current of said memory cell. 18. The method of claim 13 wherein said offset current is substantially equal to one half of the on current of said memory cell. 19. The method of claim 13 wherein said offset current is equal to a fraction of the sum of the on and off currents of said memory cell. 20. The method of claim 13 wherein said offset current is substantially equal to one half of the sum of the on and off currents of said memory cell. 21. The method of claim 13 wherein said generating a matrix current comprises coupling said read signal to a row of nonvolatile memory cells that are similar to said memory cell to generate said offset current.

22. A circuit for reading a matrix nonvolatile memory cell having an input coupled to a word line, which is coupled to an address decoder, and having an output, comprising:

an offset drive line that is at substantially a same potential as said word line during a transient period of a read of said cell;

a reference drive line;

a matrix line coupled to said memory-cell output;

a reference line;

a differential amplifier having a first input coupled to said matrix line and a second input coupled to said reference line;

a reference-current generator having an input coupled to said reference drive line and an output coupled to said reference line; and

an offset-current generator having an input coupled to said offset drive

line and an output coupled to said matrix line. 23. The circuit of claim 22 wherein said reference drive line is at substantially

said same potential during said read of said cell. 24. The circuit of claim 22 wherein said reference-current generator comprises a first reference nonvolatile memory cell programmed in an on state and having an input and an output respectively coupled to said reference-current generator input and output. 25. The circuit of claim 24 wherein said reference-current generator further comprises a second reference nonvolatile memory cell programmed in an off state and having an output coupled to said output of said reference-current generator. 26. The circuit of claim 25 wherein said second reference nonvolatile memory cell comprises an input coupled to said input of said reference-current generator. 27. The circuit of claim 25 wherein said second reference nonvolatile memory cell comprises an input coupled to said offset drive line. 28. The circuit of claim 25 wherein said second reference nonvolatile memory cell comprises an input that is coupled to said offset-current generator. 29. The circuit of claim 22 wherein said offset-current generator comprises a dummy row of nonvolatile memory cells each having an input coupled to said offset drive line. 30. The circuit of claim 22 wherein said offset-current generator comprises:

an input current generator having an input coupled to said input of said offset-current generator and having an output;

a current mirror having an input coupled to said output of said input-current generator and having an output; and

a current divider having an input coupled to said output of said current mirror and an output coupled to said output of said offset-current generator. 31. The circuit of claim 30 wherein said input current generator comprises a first nonvolatile memory cell programmed in an on state and having an input and an output respectively coupled to said

input and output of said input current generator. 32. The circuit of claim 31 wherein said input current generator further comprises a second nonvolatile memory cell programmed in an off state and having an input and an output respectively coupled to said input and output of said input current generator. 33. The circuit of claim 30 wherein said current divider comprises:

first and second diode-connected nonvolatile memory cells programmed in an on state and coupled in parallel to said input of said current divider; and

a third nonvolatile memory cell having an input and output respectively coupled to said input and output of said current divider. 34. The circuit of claim 30 wherein said reference-current generator further comprises a reference nonvolatile memory cell programmed in an off state and having an input coupled to said output of said current mirror and having an output coupled to said reference line.