Data stream converter with increased grey levels

Abstract

The present invention relates to An apparatus for converting cathode ray tube (CRT) data to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame four panel refresh frames. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.

Description

This is a continuation of application Ser. No. 07/778,799, filed on Oct. 17, 1991, now abandoned.

FIELD OF THE INVENTION

The present invention relates to an apparatus for converting cathode ray tube (CRT) data streams to multi-segment data streams and, more particularly, includes a frame buffer system for displaying data on a dual panel display, which comprises upper and lower panels. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates four panel refresh frames for the dual panel display (1U, 2U, 2L, 3L), (3U, 4U, 4L, 5L) and (5U, 6U, 6L, 7L) respectively. Next there are lines showing the buffer output (c), the control signal (d) and the data residing in upper and lower panels at different points in time (e and f).

Initially, in this embodiment when the control signal is high, the first one-half frame of CRT format data C1U is provided to the frame buffer system 100 (FIG. 4) and current upper panel refresh frame 1U is provided to the upper panel via multiplexer 108 and the next upper panel refresh frame 2U is provided to the frame buffer 112.

When the control signal goes low, the delayed upper panel refresh panel 2U is provided to the upper panel via multiplexer 108. Also, the second one-half of CRT format data C1L is provided to the frame buffer system 100 and current lower panel refresh frame 2L is provided to the lower panel via multiplexer 110 and the next lower panel refresh frame 3L is provided to the frame buffer 112.

Next, when the control signal goes high, the delayed lower panel refresh frame 3L is provided to the lower panel via multiplexer 110. Also, the third one-half of CRT format data C2U is provided to the frame buffer system 100 and current upper panel refresh frame 3U is provided to the upper panel via multiplexer 108 and the next upper panel refresh frame 4U is provided to the frame buffer 112.

When the control signal goes low, the delayed upper panel refresh frame 4U is provided to the upper panel via multiplexer 108. Also, the fourth one-half of CRT format data C2L is provided to the frame buffer system 100 and current lower panel refresh frame 4L is provided to the lower panel via multiplexer 110 and the next lower panel refresh frame 5L is provided to the frame buffer 112.

This process is repeated as shown to provide two unique panel refresh frames from each CRT frame. In so doing, the repeating panel refresh frames for each CRT frame known in the prior art are eliminated. Therefore, on panels where gray levels are generated by changing display patterns from frame to frame, it is now possible to have as many gray level patterns as panel display frame rate will allow. It is well understood in the graphics area that the more gray levels obtained, the more desirable the graphics system. Hence, through the use of the two gray level blocks in conjunction with the controllable multiplexer, a frame buffer architecture has been disclosed that is a significant improvement over those previously known.

It should be understood that although the specific embodiment of the gray level generation block algorithm is described in the before-mentioned co-pending patent application, the algorithms associated with such gray level generation blocks 102 and 104 can be of a wide variety and their use would be within the spirit and scope of the present invention. It is also well understood that although two blocks 102 and 104 are utilized to generate the gray level patterns, the patterns can be generated by any number of blocks.

Hence, numerous and various other arrangements can be readily devised in accordance with these principles by one of ordinary skill in the art without departing from the spirit and scope of the present invention, and is limited only by the following claims.

Claims

1. A frame buffer system for displaying data on a dual panel display, the dual panel display including an upper panel and a lower panel, the frame buffer system for receiving a cathode ray tube (CRT) data frame having an upper half and a lower half, the frame buffer system for displaying current upper and lower panel refresh frames and next upper and lower panel refresh frames generated from the CRT data frame, the frame buffer system comprising:

first means for generating a gray level pattern from the CRT data frame for the current upper and lower panel refresh frames;

second means for generating a gray level pattern from the CRT data frame for the next upper and lower panel refresh frames;

means coupled to the first generating means for providing the current upper panel refresh frame to the upper panel, responsive to a first state of a control signal and for providing the current lower panel refresh frame to the lower panel responsive to a second state of a control signal;

means for delaying the next upper and lower panel refresh frame frames; and

means coupled to the second generating means and the delaying means for providing the delayed next lower panel refresh frame to the lower panel responsive to the first state of a control signal and for providing the delayed next upper panel refresh frame to the upper panel responsive to the second state of a control signal.

2. The frame buffer system of claim 1 in which the current panel refresh frame providing means comprises a first multiplexer and the delayed next panel refresh frame providing means comprises a second multiplexer.

3. The frame buffer system of claim 1 in which includes:

means for controlling the first and second providing means current panel refresh frame providing means and the delayed next panel refresh frame providing means.

4. The frame buffer system of claim 1, in which the delaying means comprises a half-frame buffer.

5. The frame buffer system of claim 1 in which the first generating means and the second generating means generate the current panel refresh frame and the next panel refresh frame simultaneously.

6. A half frame buffer system for displaying data on a dual panel display, the dual panel display including an upper panel and a lower panel, the half frame buffer system for receiving a cathode ray tube (CRT) data frame and the half frame buffer system for displaying a current upper and lower panel refresh frames and next upper and lower panel refresh frames generated from the CRT data frame, the half frame buffer system comprising:

a first means for generating gray level patterns from the CRT data frame for the current upper and lower panel refresh frames;

a second means for generating gray level patterns from the CRT data frame for the next upper and lower panel refresh frame;

a half frame buffer coupled to the second means for delaying the next upper and lower panel refresh frame frames;

a first multiplexer coupled to the first means for providing the current upper panel refresh frame to the upper panel responsive to a first state of a control signal and for providing the current lower panel refresh frame to the lower panel responsive to a second state of the control signal during the lower half of the CRT data frame; and

a second multiplexer means coupled to the half frame buffer for providing the delayed next upper lower panel refresh frame to the lower panel responsive to the first state of the first control signal and for providing the delayed next lower upper panel refresh frame to the lower upper panel responsive to a the second state of the control signal during the lower half of the CRT data frame.