The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology topography of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
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20. A process for providing a conductor on a non-planar substrate comprising:
forming a layer of conductive material on said non-planar substrate such that the height of said layer of conductive material extends above the topography of said non-planar substrate; planarizing said conductive material layer; forming a layer of at least partially reflective material over said planarized conductive material layer; and patterning said planarized conductive material layer.
43. A process for providing a conductor on a non-planar substrate comprising:
forming a substantially planar layer of conductive material on said non-planar substrate such that the height of said substantially planar layer of conductive material extends above the topography of said non-planar substrate; forming a layer of at least partially reflective material over said substantially planar conductive material layer; and patterning said substantially planar conductive material layer.
30. A process for providing a transistor gate on a non-planar substrate, said process comprising the steps of:
forming a layer of conductive material on said non-planar substrate such that the height of said layer of conductive material extends above the topography of said non-planar substrate; planarizing said conductive material layer; forming a layer of at least partially reflective material over said planarized conductive material layer; and patterning said planarized conductive material layer.
51. A process for providing a transistor gate on a non-planar substrate, said process comprising the steps of:
forming a substantially planar layer of conductive material on said non-planar substrate such that the height of said substantially planar layer of conductive material extends above the topography of said non-planar substrate; forming a layer of at least partially reflective material over said substantially planar conductive material layer; and patterning said substantially planar conductive material layer.
1. A process for providing a planarized conductor on a non-planar starting substrate, said process comprising the steps of:
forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said planarized conductive material layer extends above the topology topography of said neighboring isolation regions; forming a layer of reflective material superjacent and coextensive said planarized conductive material layer; and patterning said planarized conductive material layer thereby forming said planarized conductor.
9. A process for providing a planarized transistor gate on a non-planar starting substrate, said process comprising the steps of:
forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said planarized conductive material layer extends above the topology topography of said neighboring isolation regions; forming a layer of reflective material superjacent and coextensive said planarized conductive material layer; and patterning said planarized conductive material layer thereby forming said thereby forming said planarized transistor gate.
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This invention relates to gates(e.g., a conductive material) is formed overlying thick oxide regions 32 and thin oxide film 33. In this example, thick oxide region extends regions 32 extend approximately 2000Å 2000 ANG above the substrate's surface. Therefore, polysilicon 34 must be thick enough whereby its thickness extends substantially above the 2000Å 2000 ANG height of the thick oxide regions 32. In this case, after planarization of polysilicon 34, 1000Å 1000 ANG of polysilicon 34 remains remain to overlie thick oxide regions 32. Thus, the overall thickness of the polysilicon 34 (e.g., a conductive material layer) after planarization is about 3000 Å. Next a layer of reflective material 35, such as silicide (i.e. tungsten silicide, titanium silicide, etc.) or metal is formed over planarized polysilicon 34. The higher the capability that the reflective material 35 has to reflect the photolithographic light during subsequent patterning of planarized conductive strips, the less susceptible are the patterned conductive strips to reflective notching. The planarization of the conductively doped polysilicon 34 (e.g., a conductive material) can be achieved by abrasion, such as chemical mechanical polishing.
Referring now to FIG. 4 4A, planarized polysilicon 34 and silicide 35 are patterned to form planarized conductive strips 41 that will serve as (planarized) control gates to a MOS transistor.
As an alternative to FIGS. 3 and 4a, FIG. 4b show 4A, FIG. 4B shows planarized conductive strips 42 that is are formed out of polysilicon only.
As another alternative to FIGS. 3 and 4a, FIG. 4c show 4A, FIG. 4C shows planarized conductive strips 43 that are formed out of polysilicon 34, silicide 35 and a partially reflective insulator 37 (such as nitride).
FIG. 5 shows a second embodiment depicting the use of the process steps of the present invention wherein a thick oxide is patterned and etched to form thick blocks of isolation oxide 52 that is are spaced apart by a thin gate oxide 51 that results from the etching of thick oxide 52. To form gate oxide 51, the thick oxide is etched to bare silicon and then a thin gate oxide is thermally grown on silicon 31. The process steps than then follow those discussed in FIGS. 3 and 4 and to form resultant planarized conductive strips 53 that will serve as (planarized) control gates to a MOS transistor.
FIG. 6 is a flow diagram depicting the general process steps of the present invention described above wherein; Step A : Step 1 comprises forming a planarized conductive layer over an a non-planar substrate; Alternate Step B Step 1.1 comprises forming a second conductive layer on the planarized conductive layer of Step A Step 1; and Step C Step 3 comprises patterned patterning the conductive layers of Steps A and C Steps 1 and 3 to form a planarized conductor.
From the process steps described in the two embodiments above, one skilled in the art could utilize these steps to form planarized conductive strips on an a non-planarized surface wherein the conductive strips comprise various conductive materials including multiple doped polysilicon layers, metal layers and any combination thereof.
Therefore, it is to be understood that although the present invention has been described with reference to several embodiments, various modifications, known to those skilled in the art, may be made to the structure and process steps presented herein without departing from the invention as recited in the several claims appended hereto.
Doan, Trung T., Dennison, Charles H.
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