A multilevel cascade voltage source inverter having separate dc sources is described herein. This inverter is applicable to high voltage, high power applications such as flexible AC transmission systems (FACTS) including static VAR generation (SVG), power line conditioning, series compensation, phase shifting and voltage balancing and fuel cell and photovoltaic utility interface systems. The M-level inverter consists of at least one phase wherein each phase has a plurality of full bridge inverters equipped with an independent dc source. This inverter develops a near sinusoidal approximation voltage waveform with only one switching per cycle as the number of levels, M, is increased. The inverter may have either single-phase or multi-phase embodiments connected in either wye or delta configurations.
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24. A multiple dc voltage source inverter for connecting to an AC power system, comprising:
at least one cascade inverter phase including a plurality of full bridge inverters connected in a series relationship; a control means connected in an operable relationship with each of said full bridge inverters to detect a period and a reference signal associated with the AC power system and to alternate activation and deactivation of each of said full bridge inverters in response to the reference signal to create a nearly sinusoidal voltage waveform approximation having substantially the same period as the AC power system and having a desired phase shift defined with respect to the phase reference signal; and a smoothing inductor connected in series between the cascade inverter phase and the AC power system.
16. A method for inverting a plurality of dc voltage signals to approximate a sinusiodal sinusoidal voltage waveform comprising the following steps:
a. detecting the dc voltage levels of a plurality of dc voltage sources; b. averaging said dc voltage levels; c. comparing said average with a reference dc voltage; d. generating a first error signal from said comparison of said average with a reference dc voltage; e. comparing said average with said detected dc voltage levels; f. generating a second error signal from said comparison of said average with said detected dc voltage levels; g. generating a phase shift offset signal from said second error signal; h. generating an average phase shift signal from said first error signal; i. summing said phase shift offset signal and said average phase shift signal; j. detecting an AC line voltage having a period; k. generating a phase reference signal directly related to said period of said AC line voltage; l. generating a plurality of firing reference signals for a plurality of full bridge inverters using said phase reference signal and said sum of said phase shift offset signal and said average phase shift signal; m. determining a modulation index; n. providing a reference table for said modulation index; o. generating a plurality of firing angle signals for said plurality of full bridge inverters using said firing reference signal and said reference table;
whereby, the alternate activation of a plurality of gate turn-off devices in said full bridge inverters may be controlled to construct an output voltage waveform having a sinusoidal approximation for use by an AC load. 1. A multiple dc voltage source inverter for connecting to an AC power system, comprising:
a. a plurality of full bridge inverters having a primary node and a secondary node, each of said full bridge inverters having a positive node and a negative node, each of said full bridge inverters having a voltage supporting device electrically connected in a parallel relationship between said positive node and said negative node; b. at least one cascade inverter phase, each cascade inverter phase having a plurality of said full bridge inverters, each cascade inverter phase having a consistent number of said full bridge inverters with respect to each phase, each of said full bridge inverters in each cascade inverter phase interconnected in a series relationship with said secondary node of one of said full bridge inverters connected to said primary node of another full bridge inverter, said series interconnection defining a first full bridge inverter and a last full bridge inverter, each phase having an input node at said primary node of said first full bridge inverter and an output node at said secondary node of said last full bridge inverter; c. a control means connected in an operable relationship with each of said full bridge inverters to emit a square wave signal for a prescribed period therefrom; whereby, detect a period and a reference signal associated with the AC power system and to alternate activation and deactivation of each of said full bridge inverters in response to the reference signal to create a nearly sinusoidal voltage waveform approximation is generated by the controlled, alternate activation and deactivation of said full bridge inverters by said control means having substantially the same period as the AC power system and having a desired phase shift defined with respect to the reference signal.
9. A multiple dc voltage source inverter for connecting to an AC power system having a plurality of phases, comprising:
a. a plurality of full bridge inverters having a primary node and a secondary node, each of said full bridge inverters having a positive node and a negative node, each of said full bridge inverters having a voltage supporting device electrically connected in a parallel relationship between said positive node and said negative node; b. a plurality of cascade inverter phases, each of said cascade inverter phases corresponding to one of the phases of the AC power system and having a plurality of said full bridge inverters, each of said cascade inverter phases having a consistent number of said full bridge inverters with respect to each phase, each of said full bridge inverters in each cascade inverter phase interconnected in a series relationship with said secondary node of one of said full bridge inverters connected to said primary node of another full bridge inverter, said series interconnection defining a first full bridge inverter and a last full bridge inverter, each of said phases having an input node at said primary node of said first full bridge inverter and an output node at said secondary node of said last full bridge inverter; c. a common node defined by the electrical interconnection of said output nodes of each of said cascade inverter phases; and d. a control means connected in an operable relationship with each of said full bridge inverters to emit a square wave signal for a prescribed period therefrom;
whereby, cascade inverter phase to detect a period and a phase reference signal associated with a corresponding phase of the AC power system and to alternate activation and deactivation of each of the full bridge inverters of the cascade inverter phase in response to the phase reference signal to create a nearly sinusoidal voltage waveform approximation is generated by the controlled, alternate activation and deactivation of said full bridge inverters by said control means having substantially the same period as the corresponding phase of the AC power system and having a desired phase shift defined with respect to the phase reference signal. 2. A multiple dc voltage source inverter for connecting to an AC power system as described in
3. A multiple dc voltage source inverter for connecting to an AC power system as described in
4. A multiple dc voltage source inverter for connecting to an AC power system as described in
5. A multiple dc voltage source inverter for connecting to an AC power system as described in
6. A multiple dc voltage source inverter for connecting to an AC power system as described in
7. A multiple dc voltage source inverter for connecting to an AC power system as described in
8. A multiple dc voltage source inverter for connecting to an AC power system as described in
10. A multiple dc voltage source inverter for connecting to an AC power system as described in
11. A multiple dc voltage source inverter for connecting to an AC power system as described in
12. A multiple dc voltage source inverter for connecting to an AC power system as described in
13. A multiple dc voltage source inverter for connecting to an AC power system as described in
14. A multiple dc voltage source inverter for connecting to an AC power system as described in
15. A multiple dc voltage source inverter for connecting to a AC power system as described in
17. The multiple dc voltage source inverter of
the phase shift is selected to generate a desired level of positive or negative reactive power delivered to the AC power system while generating sufficient real power to offset losses incurred within the full bridge inverters.
18. The multiple dc voltage source inverter of
19. The multiple dc voltage source inverter of
the phase shift is selected to perform a flexible AC transmission operation selected from the group including static VAR generation, power line conditioning, series compensation, phase shifting, voltage balancing, and generator interfacing.
20. The multiple dc voltage source inverter of
21. The multiple dc voltage source inverter of
the phase shift for each cascade inverter phase is selected to generate a desired level of positive or negative reactive power delivered to the corresponding phase of the AC power system while generating sufficient real power to offset losses incurred within the cascade inverter phase.
22. The multiple dc voltage source inverter of
23. The multiple dc voltage source inverter of
the phase shift for each cascade inverter phase is selected to perform a flexible AC transmission operation selected from the group including static VAR generation, power line conditioning, series compensation, phase shifting, voltage balancing, and generator interfacing.
25. The multiple dc voltage source inverter of
a first control loop for controlling the power flow to the cascade inverter phase; and a second feed-back control loop for offsetting the power flow to each of the full bridge inverters of the cascade inverter phase.
26. The multiple dc voltage source inverter of
a switching pattern table containing switching timing data for generating the nearly sinusoidal voltage waveform approximation in response to a reference output voltage signal and a desired phase angle; means for calculating the reference output voltage signal; a phase detector for determining the reference signal; and means for determining the desired phase angle in response to the reference signal and a feedback signal produced by the first and second control loops.
27. The multiple dc voltage source inverter of
the AC power system includes three phases; the cascade inverter includes three phases, one cascade inverter phase corresponding to each phase of the AC power system; the cascade inverter includes three smoothing inductors, one smoothing inductor connected in series between each cascade inverter phase and each phase of the AC power system; and the control means includes for each cascade inverter phase, a first control loop for controlling the power flow to the cascade inverter phase, a second feed-back control loop for offsetting the power flow to each of the full bridge inverters of the cascade inverter phase, a switching pattern table containing switching timing data for generating the nearly sinusoidal voltage waveform approximation in response to a reference output voltage signal and a desired phase angle for the cascade inverter phase, means for calculating the reference output voltage signal for the cascade inverter phase, a phase detector for determining a phase reference signal associated with a corresponding phase of the AC system, and means for determining the desired phase angle for the cascade inverter phase in response to the phase reference signal and a feedback signal produced by the first and second control loops for the cascade inverter phase. 28. The multiple dc voltage source inverter of
each of said full bridge inverters includes a primary node and a secondary node, each of said full bridge inverters includes a positive node and a negative node, each of said full bridge inverters includes a voltage supporting device electrically connected in a parallel relationship between said positive node and said negative node; and each cascade inverter phase includes a plurality of said full bridge inverters, each cascade inverter phase having a consistent number of said full bridge inverters with respect to each phase, each of said full bridge inverters in each cascade inverter phase interconnected in a series relationship with said secondary node of one of said full bridge inverters connected to said primary node of another full bridge inverter, said series interconnection defining a first full bridge inverter and a last full bridge inverter, each phase having an input node at said primary node of said first full bridge inverter and an output node at said secondary node of said last full bridge inverter.
29. The multiple dc voltage source inverter of
the phase shift for each cascade inverter phase is selected to generate a desired level of positive or negative reactive power delivered to the corresponding phase of the AC power system while generating sufficient real power to offset losses incurred within the cascade inverter phase.
30. The multiple dc voltage source inverter of
the phase shift for each cascade inverter phase is selected to perform a flexible AC transmission operation selected from the group including static VAR generation, power line conditioning, series compensation, phase shifting, voltage balancing, and generator interfacing.
31. The multiple dc voltage source inverter of
32. The multiple dc voltage source inverter of
33. The multiple dc voltage source inverter of
34. The multiple dc voltage source inverter of
35. The multiple dc voltage source inverter of
36. The multiple dc voltage source inverter of
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This invention was made with Government support under contract DE-AC05-84OR21400 awarded by the U.S. Department of Energy to Lockheed Martin Energy Systems, Inc. and the Government has certain rights in this invention.
This application is a RE of 08/527,995, filed on Sep. 14, 1995, now U.S. Pat. No. 5,642,275.
The present invention relates to a multilevel voltage source inverter with separate DC sources, and more particularly to a multilevel voltage source inverter with separate DC sources including an apparatus and a method for use in flexible AC transmission system (FACTS) applications such as compensating reactive power and voltage balancing.
With long distance electrical power transmission and load growth, active control of reactive power (VAR) is indispensable with regard to stabilizing power systems and maintaining supply voltages. Static VAR generators (SVGs) using voltage-source inverters have been widely accepted as the next generation of reactive power controllers for power systems replacing conventional VAR compensators such as Thyristor Switched Capacitors (TSCs) and Thyristor Controlled Reactors (TCRs).
Delivering power from a power generating station to the ultimate power consumers over long transmission lines can be very costly for an electric utility. The electric utility passes on these costs to the ultimate consumers as higher electricity bills. Inductive and capacitive losses affect a reactive component of power which is measured in volt-ampere-reactive (VAR) units. These reactive power (VAR) losses may be compensated using a static VAR compensator to more economically transmit thereby reducing overall electricity bills as well as stabilizing the supplied voltage to the end user.
The state of the art VAR compensating approach uses transformer coupling voltage source inverters. A transformer coupling voltage source inverter comprising eight six-pulse converters connected in either a zig-zag, wye or delta configuration has a 48-pulse or a 48-step staircase inverter output voltage waveform which dramatically reduces harmonics. The major problem of using this transformer coupling approach resides in the transformer as a function of harmonic neutralizing magnetics. The transformer with the inherent harmonic neutralizing magnetics deficiency:
(a) is the most expensive equipment in the system;
(b) produces approximately 50% of the total system losses;
(c) occupies approximately 40% of the system layout; and
(d) causes difficulties in system control due to DC magnetizing and surge overvoltage problems resulting from saturation of the transformers on the transient state.
In recent years, a relatively new type of inverter, a multilevel voltage source inverter, has attracted the attention of many researchers. The transformerless multilevel inverter can reach high voltage and minimize induced harmonics as a function of inverter structure.
A multilevel, referred to as M-level, diode clamped inverter can reach high performance without the benefit of transformers. This inverter does, however, require the implementation of additional clamping diodes. The number of diodes required is equal to (M-1)*(M-2)*3 for an M-level inverter. For example, if M=51, for direct connection to a 69 kV power system, then the number of required clamping diodes will be 7350. These clamping diodes not only increase the cost of the system but also cause packaging/layout problems and introduce parasitic inductances into the system. Thus, for practicality, the number of levels of a conventional multilevel diode clamped inverter is typically limited to seven or nine levels.
A relatively new inverter structure, the multilevel flying capacitor inverter has the capability to solve the voltage balance problems and aforementioned problems associated with the multilevel diode clamped inverters. The required number of flying capacitors for an M-level inverter, provided that the voltage rating of each capacitor used is the same as the main power switches is determined by the formula, (M-1)*(M-2)*3/2+(M-1). Using the assumption of having capacitors with the same voltage rating, an M-level diode clamped inverter requires only (M-1) capacitors. Therefore, the flying capacitor inverter requires capacitors of substantial size compared with the conventional inverter. In addition, control is very complicated and higher switching frequency is required to balance the voltages between each capacitor in the inverter.
A multilevel cascade inverter with separate DC sources for reactive power compensation in AC power systems which is directed toward overcoming and is not susceptible to the above limitations and disadvantages is described herein. The multilevel voltage source inverter having separate DC sources eliminates the excessively large number of transformers required by conventional multipulse inverters, clamping diodes required by multilevel diode-clamped inverters and flying capacitors required by multilevel flying-capacitor inverters. The multilevel voltage source inverter having separate DC sources also has the following features:
(a) the multilevel voltage source inverter having separate DC sources is more suitable to high voltage, high power applications than conventional inverters;
(b) the multilevel voltage source inverter having separate DC sources generates a multistep staircase voltage waveform with the switching of each device only once per line cycle, thus reaching a nearly sinusoidal output voltage approximation by increasing the number of voltage levels;
(c) since the multilevel voltage source inverter having separate DC sources consists of cascade connections of a plurality of single-phase full bridge inverters fed with a separate DC source, neither voltage balancing nor voltage matching of switching devices is required; and
(d) system packaging and layout is streamlined due to the simplicity and symmetry of structure as well as the minimization of component count.
Thus, a need for a multilevel cascade voltage source inverter with separate DC sources for reactive power compensation in AC power systems is clearly evident.
Accordingly, it is an object of the present invention to provide a new and improved multilevel cascade voltage source inverter and more specifically a multilevel cascade voltage source inverter for connecting to an AC high voltage, high power system.
It is another object to provide a wye configured multilevel voltage source inverter for FACTS applications such as VAR compensation and voltage balancing of AC power systems.
It is another object to provide a delta configured multilevel voltage source inverter for FACTS applications such as VAR compensation and voltage balancing of AC power systems.
It is another object to provide a multilevel voltage source inverter for connecting to an AC high voltage, high power system for a variety of applications such as fuel cells, photovoltaic utility interface systems.
It is another object to provide a method for controlling the multilevel voltage source inverter to supply a sinusoidal approximation power waveform to an AC high voltage, high power system for a variety of applications from a plurality of DC voltage sources.
Further and other objects of the present invention will become apparent from the description contained herein.
In accordance with one aspect of the present invention, a multiple voltage source inverter for connecting to an AC power system comprising a plurality of full bridge inverters having a primary node and a secondary node, each of the full bridge inverters having a positive node and a negative node, each of the full bridge inverters having a voltage supporting device electrically connected in a parallel relationship between the positive node and the negative node; at least one cascade inverter phase, each of the cascade inverter phases having a plurality of the full bridge inverters, each of the cascade inverter phases having a consistent number of the full bridge inverters with respect to each phase, each of the full bridge inverters in each cascade inverter phase interconnected in a series relationship with the secondary node of one of the full bridge inverters connected to the primary node of another full bridge inverter, the series interconnection defining a first full bridge inverter and a last full bridge inverter, each of the phases having an input node at the primary node of the first full bridge inverter and an output node at the secondary node of the last full bridge inverter; a control means connected in an operable relationship with each of the full bridge inverters to emit a square wave signal for a prescribed period therefrom; whereby, a nearly sinusoidal voltage waveform approximation is generated by the controlled, alternate activation and deactivation of the full bridge inverters by the control means.
The control principle can be explained with the assistance of FIGS. 7a and 7b. In FIG. 7a, vs is the source voltage, iC is the current flowing into the inverter and vC is the inverter output voltage. If vC is controlled so that vC lags vs by αC, then the total real power flowing into the inverter, Pi, is: ##EQU5##
where XLc is the inductance of the interface inductor LC. Since the devices, e.g. capacitors, diodes, etc., used in the construction of the multilevel cascade inverter 410 are not ideal and therefore have varying tolerances, each DC capacitor voltage can not be exactly balanced using the outer loop only. Referring to FIGS. 7a and 7b, if FBI unit I output voltage, vCi, is as shown by trace 520, then the average charge into the DC capacitor over each half cycle, the second shaded area 530, will nearly equal zero. However, if vCi is shifted ahead by ΔαCi as shown by trace 540, the charge shown in area 550 can be expressed as: ##EQU6##
which is proportional to ΔαCi when ΔαCi is small. Therefore, each FBI unit DC capacitor voltage can be actively controlled by slightly shifting the switching pattern. In the case for high voltage, high power applications, total power loss for the multilevel cascade inverter 410 is typically less than one percent.
The control principle can be explained with the assistance of FIGS. 7a and 7b. In FIG. 7a, V2 is the source voltage, iC is the current flowing into the inverter, and VC is the inverter output voltage. If VC is controlled so that VC lags V2 by ∝C, then the total real power flowing into the inverter, Pi is: ##EQU7##
where XLc is the inductance of the interface inductor LC. Since the devices, e.g., capacitors, diodes, etc., used in the construction of the multilevel cascade inverter 410 are not ideal and therefore have varying tolerances, each DC capacitor voltage can not be exactly balanced using the outer loop only. Referring to FIGS. 7a and 7b, if FBI unit I output voltage, VC1 is as shown by trace 520, then the average charge into the DC capacitor over each half cycle, the second shaded area 530, will nearly equal zero. However, if VCi is shifted ahead by ΔαCi as shown by trace 540, the charge shown in area 550 can be expressed as: ##EQU8##
which is proportional to ΔαCi when ΔαCi is small. Therefore, each FBI unit DC capacitor voltage can be actively controlled by slightly shifting the switching pattern. In the case for high voltage, high power applications, total power loss for the multilevel cascade inverter 410 is typically less than one percent.
The method used to control the automatic switching of the FBIs may be best described with reference to FIG. 6. First, the voltage supporting device DC voltage levels, VCi, are detected, summed and then averaged. The average DC voltage level is then compared with a system reference DC voltage, Vdc *. Using a proportional integrator, an average phase shift signal, αC, is generated from a first error signal describing the comparison between the average DC voltage level and the system reference DC voltage, Vdc *. The average DC voltage level is also compared with the respective detected DC voltage levels, VCi. Using a proportional integrator, a phase shift offset signal, ΔαCi, is generated from a second error signal describing the comparison between the average DC voltage level and the respective detected DC voltage levels, VCi. The phase shift offset signal, ΔαCi, and said average phase shift signal, αC, are then summed. An AC line voltage, VS, having a period is detected from which a phase reference signal, α0, directly related to the period of the AC line voltage, VS, is developed by comparison with the sum of the phase shift offset signal signal ΔαCi, and said average phase shift signal, αC. Multiple firing reference signals, αCi, for the FBIs are generated by comparing the phase reference signal, α0, and the sum of phase shift offset signal, ΔαCi, and the average phase shift signal, αC. A modulation index, MI, may be selected by the user for which a corresponding reference table is provided. Firing angle signals are generated for the FBIs using the firing reference signal in view of the reference table for the given modulation index, MI, whereby, the alternate activation of a plurality of gate turn-off devices in the FBIs may be controlled to construct an output voltage waveform having a sinusoidal approximation for use by an AC load.
Since each phase of the multilevel cascade inverter described herein has independent DC capacitors, the required capacitance calculation of each FBI unit DC capacitor is straightforward. With reference to FIG. 3, the required capacitance, Ci, can be expressed as: ##EQU9##
where I is the current rating of the inverter, ε is the given regulation factor of the DC voltage and θi is the switching timing angle of FBI unit I as shown in FIG. 3. Note that:
I=ISVG (Eq. 8)
for the wye connected embodiment and: ##EQU10##
for the delta connected embodiment. The total required capacitance for a three-phase M-level converter, C, may be expressed as ##EQU11##
As previously discussed, θi is calculated for each MI value. To generate ±QVAR reactive power, MI would change between MImin and MImax, wherein the SVG produces +QVAR when MI=MImax and produces -QVAR for MI=MImin. For MI=MImax, θi becomes minimum and for MI=MImin, θi becomes maximum. Therefore, θilat MI=MImax may be used in equation 6 to calculate the required capacitance to maintain the DC voltage ripple below the given regulation, ε, for all loads.
A SVG system as shown in FIG. 6 having an 11-level wye-connected cascade inverter with 5 FBI units per phase was constructed having the system parameters shown in Table 1. The switching timing angles, θi, wherein i=1, 2. 3, 4, 5), shown in Table 2, were specifically calculated for minimizing voltage harmonics, below the 25th order, and stored in the switching pattern table 415 shown in FIG. 6.
| TABLE 1 |
| System Parameters of Experimental Prototype |
| System Parameter Value |
| Source Voltage Rating, Vs 240 V |
| VAR Rating, QVAR ±1 kVAR |
| Current Rating, I 2.4 A |
| DC Voltage, Vdc 40 V |
| DC Voltage Regulation, ε ±5% |
| Interface Inductance, LC 20% (32 mH) |
| Source Impedance, LS 3% |
| Modulation Index, MImin, MImax 0.615, 0.915 |
| TABLE 2 |
| Switching Pattern Table of 11-Level Cascade Inverter |
| Modulation Index Switching Timing Angles (rad.) |
| MI θ1 θ2 θ3 θ4 |
| θ5 |
| 0.615 0.4353 0.7274 0.8795 1.0665 1.2655 |
| . . . . . . . . . . . . . . . . . . |
| 0.915 0.0687 0.1595 0.3124 0.4978 0.7077 |
Using the parameters of Tables 1 and 2 and Equations 7 and 10, the following values may be calculated:
C1 =2.1 mF;
C2 =1.89 mF;
C3 =1.56 mF;
C4 =1.18 mF; and
C5 =0.79 mF.
The total capacitance is calculated:
C=22.56 mF.
As the number of inverter cascade levels is increased for high voltage applications, the required capacitance of the cascade inverter, C, will approach that of a conventional multipulse inverter, Cdc, wherein the ratio C/Cdc will approach one as a limit.
An SVG system using the delta connected embodiment of a 21-level cascade inverter having 10 FBI units per phase is connected directly to a 13 kV distribution system. The SVG capacity is ±50 MVAR. ISVG =2.22 kA, I=1.282 kA, LC =3%, MImin =0.6385, MImax =0.8054, Vdc =2 kV and ε=±5%. At the rated load of +50 MVAR, [θ1, θ2. . . θi ]=[0.0334, 0.1840, 0.2491, 0.3469, 0.4275, 0.5381, 0.6692, 0.8539, 0.9840, 1.1613] rad. For this SVG system, the total required capacitance of DC capacitors can be calculated as C=370 mF. The required capacitance for a comparable conventional multipulse inverter will be Cdc =332 mF. Therefore, the ratio C/Cdc approached unity at 1.11.
To demonstrate the validity of the multilevel cascade inverter described herein, an SVG prototype using an 11-level wye-connected cascade inverter was built. FIG. 6 and Tables 1 and 2 show the experimental configuration and the corresponding parameters. For the DC voltage control loops, only the voltages of C1 and C5 of phase "a" are detected and controlled directly. The control voltages for C2, C3 and C4 uses interpolating values of ΔαC1 and ΔαC5.
FIGS. 8, 9 and 10 show the experimental results when the SVG generates +1 kVAR reactive power. FIG. 11 shows experimental results at zero VAR output. FIGS. 12 and 13 show the case of generating -1 kVAR reactive power.
From FIGS. 8, 9 and 10 it is demonstrated that the inverter output phase voltage is an 11-level steplike waveform and the line-to-line voltage is a 21-level steplike waveform over a half cycle. Each step has the same span, which means the voltage of each DC capacitor is well controlled and balanced. The DC voltage command, Vdc *, was 40 V, and the modulation index was the maximum, MI=0.915, in this case.
It is well known to those of ordinary skill in the art that either the modulation index or the DC voltage or both may be controlled to regulate the output voltage. FIG. 12 shows the experimental waveforms to generate zero reactive power or zero current with a different DC voltage and the same modulation index as that of FIGS. 8, 9 and 10. In this case, the DC voltage of each DC capacitor was controlled to be 34 V, Vdc *=34 V.
In FIGS. 12 and 13, M1=0.615 and Vdc *=40 V. The inverter generates -1 kVAR of reactive power, that is, the current, ICa, is lagging the voltage, VSa, by 90 degrees.
These experimental results show that the voltages of the DC capacitors are well balanced. The results also show that pure sinusoidal current has been obtained with only 20% impedance on the AC side of the inverter. Using the delta-connected embodiment of the cascade inverter can compensate for a balanced or unbalanced three-phase load reactive power.
Applications for the multilevel cascade voltage source inverters with separate DC sources are not limited to static VAR compensation or power system applications. These multilevel cascade inverters may also be used for providing clean AC power to AC loads with separate DC sources. FIG. 14 shows a circuit diagram having a multiphase, multilevel cascade inverter with separate DC sources 701 connected to an AC load 790 through smoothing inductors 760, 770 and 780. Typically, this circuit contains a set of separate DC voltage sources 710, 720, 730 and 740 which feed through a multilevel cascade inverter 701 to produce a step-like AC output voltage waveform. The voltage is then filtered by small smoothing inductors 760, 770 and 780 to produce a pure sinusoidal wave for an AC load 790. If the specific application is for AC motors, then the smoothing inductors 760, 770 and 780 may be removed from the circuit because the load motor has sufficient inductance to filter the input current. Examples of typical loads comprise motor drives, actuators and appliances. The DC voltage sources 710, 720, 730 and 740 may be obtained from any type conventional voltage source such as batteries, capacitors, photocells, fuel cells and biomass.
While there has been shown and described what is at present considered the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications can be made therein without departing from the scope of the invention deformed by the appended claims.
Lai, Jih-Sheng, Peng, Fang Zheng
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