A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
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35. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the support comprises an adhesive tape.
42. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attached the leads to a support, wherein the support is attaching to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein at least one of the leads comprises a power supply bus bar.
43. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein at least one of the leads comprises a power supply bus bar; and wherein the power supply bus bar is attached to a central portion of the semiconductor chip.
38. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive.
25. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the semiconductor chip has a length, wherein the leads extend along the length of the semiconductor chip, and wherein the leads do not extend beyond the length of the semiconductor chip.
1. A semiconductor package comprising:
a semiconductor chip with a plurality of bond pads including at least one power supplying bond pad at a central portion of a bottom surface of said semiconductor chip; a plurality of leads connected to bond pads for input/output of said bond pads, respectively, each of said leads defining an inner lead and an outer lead; at least one bus bar connected to said at least one power supplying bond pad, said at least one bus bar defining an inner lead and an outer lead; insulation adhesives for attaching said inner leads of each of the leads and said at least one bus bar to said bottom surface of the semiconductor chip; metal wires for electrically connecting the inner leads of the leads and the at least one bus bar to the bond pads, respectively; and a molding compound enveloping the semiconductor chip, and the inner leads of the leads and the bus bar with bottom surfaces of said outer leads of the leads and the bus bar exposed to outside on the bottom surface of said molding compound.
40. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive, and wherein the insulating adhesive comprises an insulating film.
41. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of lead with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive, and wherein the insulating adhesive comprises an insulating paste.
36. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached to the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of lead with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points; wherein the exposed second portions of the leads are positioned on a bottom surface of the semiconductor device, and wherein the exposed second portions of the leads comprise less than a majority portion of the area of the bottom surface.
39. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by the insulating adhesive, and wherein the leads are attached at a central portion of the major surface.
37. A method of packaging a semiconductor device, comprising the steps of:
manufacturing a semiconductor chip; forming a plurality of leads, wherein the leads each have at least a first portion and a second portion, and attaching the leads to a support, wherein the support is attached to the leads at the second portion; attaching the plurality of leads to the semiconductor chip with an insulating adhesive, wherein the chip is attached at the first portion of the leads; electrically connecting the leads to the semiconductor chip; molding the semiconductor chip and the plurality of leads with a resin, wherein the support is attached to the second portion of the leads during the molding, wherein the second portion of the leads are not covered by the resin; and removing the support from the second portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the semiconductor chip has a length, wherein the leads extend along the length of the semiconductor chip, and wherein the leads do not extend beyond the length of the semiconductor chip, and wherein the semiconductor device comprises a memory device.
7. A method of packaging a semiconductor device, comprising the steps of:
forming a plurality of contoured leads attached to a support; attaching the plurality of contoured leads to the semiconductor chip with an insulating adhesive, wherein the contoured leads each have at least a first portion and a second portion, wherein the chip is attached at a first portion of the contoured leads, wherein the contoured leads extend away from a point where a bottom surface of the semiconductor device will be formed to provide for electrical connection of the contoured leads to the semiconductor chip; electrically connecting the contoured leads to the semiconductor chip; molding the semiconductor chip and the plurality of contoured leads with a resin, wherein the support is attached to the second portion of the contoured leads during the molding, wherein the semiconductor chip is completely enveloped by the resin, wherein the second portion of the contoured leads attached to the support during the molding are not covered by the resin; and removing the support from the second portion of the contoured leads, wherein the second portion of the contoured leads is exposed to provide electrical connection points, wherein the second portion of the contoured leads is flush with the bottom surface of the semiconductor device.
2. A semiconductor package according to
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and, which may serve as a support during a molding procedure, are removed after a the molding procedure.
The lead frame 10 is attached to the semiconductor package 3 in such a manner that insulating adhesives 6 such as insulating films and insulating paste are applied to the bottom surface of the semiconductor chip 3 formed with the bond pads 3a and then the inner leads 11a, 12a of the leads 11 and the bus bars 12 are attached to the insulating adhesives 6.
Also, the leads 11 and the bus bars 12 of the semiconductor package of the present invention are shorter than those of a prior LOC type of semiconductor package in lengths between its inner leads 11a, 12a and its outer leads 11b, 12b so that lead conductance is increased when a memory chip of 16-mega-bit DRAM or greater is packaged. In addition, heat occurring in operation of chip can be easily discharged from the short leads.
FIG. 6A shows a front side of the semiconductor package of the invention and FIG. 6B shows a bottom surface of semiconductor package of the invention. As shown in FIG. 6A, the outer leads 11b and 12b of the leads 11 and the bus bars 12 are not protruded from the semiconductor package but are flush with the bottom surface of the semiconductor package.
That is, the outer leads 11b and 12b of the leads 11 and the bus bars 12 are arranged in a row at the bottom surface of the package and faces to outside to be contacted with elements of a printed circuit board, as shown in FIG. 6B. As shown in FIGS. 4 and 6B, the leads may be elongated and contoured and extend away from the bottom surface, and the exposed portion of the leads may occupy less than a majority portion of the bottom surface.
A manufacturing process of the semiconductor package as constructed above will be described in detail hereinafter.
First, a semiconductor chip 3 which has been cut separately is applied with insulating adhesive 6 such insulating film and insulating paste at its bottom surface formed with bond pads 3a. Inner leads 11a and 12a of leads 11 and bus bars 12 are attached to the bottom surface of the chid via the insulating adhesive 6 applied to the bottom surface.
Thereafter, the lead frame 10 attached to the semiconductor chip 3 is die-attached in a wire bonder (a wire bonding apparatus) and subjected to a wire bonding procedure for electrically connecting the inner leads 11a, 12a of the leads 11 and the bus bars 12 to the bond pads 3a by metal wires 7 such as gold and aluminum wires.
Subsequently, the resulting semiconductor chip assembly is subjected to a known transfer molding procedure to be enveloped. Then, as adhesive tapes attached to a bottom surface of the molded resin are removed, the outer leads 11b and 12b of the leads 11 and the bus bars 12 are exposed to outside. Thereafter, as the bottom surface of the molded package and the exposed outer leads are simply removed by a deflash procedure, the manufacturing process of the semiconductor package is completed.
The semiconductor package of the invention as prepared above is mounted on a printed circuit board such that the exposed outer leads 11b and 12b are connected to a pattern of printed circuit board by a soldering.
FIG. 7 illustrates a manufacturing process such as described herein. At step 15, the semiconductor chip is manufactured, as described earlier. At step 16, leads 11 are formed and attached to the support, which may be an adhesive tape as described earlier. At step 17, inner leads 11a and 12a are attached to semiconductor chip 3 with insulating adhesive 6. At step 18, inner leads 11a and 12a are wire bonded to bond pads 3a. At step 19, the resulting semiconductor chip assembly is subjected to a transfer molding procedure. At step 20, the adhesive tapes serving as the support during the molding procedure are removed. At step 21, the semiconductor package of the present invention is mounted on a printed circuit board.
As apparent from the above description, the present invention can leave out procedures next to a molding step. That is, since a prior semiconductor package has outer leads protruded therefrom, a manufacturing process of a prior semiconductor package requires a forming procedure for bending the protruded outer leads and a trimming procedure for cutting dampers of leads. However, since leads according to the invention are attached to adhesive tapes to form an integral lead frame and outer leads of leads are exposed to outside, a manufacturing process of the invention does not require trimming and forming procedures.
Therefore, the present invention has advantages in that since the number of manufacturing steps is significantly reduced, occurrence of poor products and manufacturing cost are reduced.
Also, since the semiconductor package of the invention has not outer leads protruded therefrom, space occupied by the semiconductor package is reduced thereby allowing the packages to be densely mounted when the packages are mounted on a printed circuit board.
In addition, since the semiconductor package of the invention has leads shortened as possible as, it is possible to improve its electrical property and to radiate heat easily as compared with prior art.
While prior semiconductor package may have gaps between outer leads and a molded resin due to outer shock applied to the outer leads during trimming and forming procedures, the semiconductor package of the invention has outer leads exposed to out side and does not require trimming and forming procedures so that the outer leads are not shocked. Therefore, the semiconductor package of the invention can prevent gaps from occurring in the contact area and thus improve humidity resistance. Also, since the semiconductor package is tested in state of tip, the test can be precisely carried out without a particular testing socket. That is, "Good rate" can be reduced.
Changes in construction will occur to those skilled in the art and various apparently different modifications and embodiments may be made without departing from the scope of the invention. The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting.
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