Display controller and display control method for multiscan liquid crystal display

Abstract

A display controller including a frequency discriminator for attaining modes of horizontal and vertical frequencies of video signals inputted thereto according to horizontal and vertical sync signals, a memory for setting therein a screen mode matching the input video signals according to the determined frequency modes, and a horizontal timing signal generator and a vertical timing signal generator capable of arbitrarily setting horizontal and vertical display positions of the video signals. Obtaining the horizontal and vertical frequencies of the video signals, the controller conducts a control operation to generate horizontal and vertical timing signals associated with the horizontal and vertical frequencies. Even when the number of dots of the lcd panel is different from the number of dots supplied during a video display period from the input video signals, the resultant image can be presented in the central screen portion of the lcd panel.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a liquid crystal display and, in particular, to a display and a display method in which video signals of a plurality of signal standards can be displayed in a similar manner as for multiscan-type displays.

DESCRIPTION OF THE RELATED ART

Recently, liquid crystal displays having features such as decreased thickness, lower-voltage operation, and reduced power consumption have been practically applied in place of cathode-ray tube (CRT) displays to personal computers, word processors, color television sets, etc.

A multiscan-type or multisync-type display is a display configured to present images in a plurality of resolutions by a multiscan function (i.e., an automatic frequency follow-up function with synchronization set to various kinds of signals). For example, video signals having resolutions of 640×400, 640×480, 1024×768, and 1120×750 dots can be displayed as images on a screen of one display. In this connection, "MULTISYNC" is a registered trademark of NEC HOME ELECTRONICS (U.S.A.) INC. in accordance with the U.S. trademark registered No. 1,443,951.

Conventionally, when handling input signals of a plurality of signal standards by one liquid crystal display (LCD), there is conducted correction of display positions for fear of positional difference in the vertical and horizontal directions associated with input signals. For example, a control circuit for use with a liquid crystal display has been described in the Japanese Patent Laid-Open Publication No. Hei-3-280084 as shown in FIG. 1.

Referring to FIG. 1, the conventional liquid crystal display controller disclosed by the Japanese Patent Laid-Open Publication No. Hei-3-280084 (to be referred to as conventional example 1 herebelow) includes a vertical synchronization (sync) signal discriminator 71, a horizontal sync signal discriminator 72, a screen mode storage circuit 73, a logical converter for horizontal and vertical sync signals 74, and a liquid crystal controller 75. The vertical sync signal discriminator 71 includes a frequency divider 76 and a latch circuit 77, whereas the horizontal sync signal discriminator 72 includes a divider 78 and a latch circuit 79.

Next, description will be given of operation of the conventional liquid crystal display controller shown in FIG. 1.

A vertical sync signal VS and a horizontal sync signal HS supplied to the controller are fed respectively to the vertical sync signal discriminator 71 and the horizontal sync signal discriminator 72 screeen

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the accompanying drawings, description will be given in detail of an embodiment in accordance with the present invention.

FIG. 5 shows structure of a display controller of a multiscan liquid crystal display in an embodiment in accordance with the present invention.

The configuration of the embodiment of FIG. 5 includes a horizontal timing signal generator 1, a vertical timing signal generator 1, a frequency discriminator 3, and a memory circuit 4. The frequency discriminator 3 includes a horizontal frequency discriminator circuit 5 and a vertical frequency discriminator circuit 6. In the diagram, letters H, V, and CLK stand for a horizontal sync signal input terminal, a vertical sync signal input terminal, and a clock signal input terminal, respectively.

FIGS. 6 and 7 respectively shows details respectively of the horizontal and vertical frequency discriminators 5 and 6 of the frequency discriminator 3.

Referring to FIG. 6, the horizontal frequency discriminator 5 includes D flip flop circuits 51 and 52, an OR gate circuit 53, a counter 54, a D flip flop circuit 55, and a decoder circuit 56. In the D flip flop circuit 55, a parallel output signal (an n-bit signal in FIG. 6) representing a count value from the counter 54 is received to be kept therein.

The vertical frequency discriminator 6 of FIG. 7 includes D flip flop circuits 61 and 62, an OR gate circuit 63, a counter 64, a D flip flop circuit 65, and a decoder 66. In the D flip flop circuit 65, a parallel output signal (a m-bit signal in FIG. 7) indicating a count value of the counter 64 is received to be memorized therein.

Next, operation of the embodiment will be described.

A horizontal sync signal H and a vertical sync signal V supplied thereto are fed to the horizontal and vertical timing signal generators 1 and 2 as well as the frequency discriminator 3 at the same time.

Also delivered to the frequency discriminator 3 is a clock signal CLK. In the discriminator 3, the input signal is judged as follows according to the received signals H, V, and CLK.

First, the horizontal frequency discriminator 5 will be described by referring to FIG. 6.

The clock signal CLK is fed to the clock input terminal of the counter 54 as shown in FIG. 6 such that the counting operation is accomplished during one horizontal (1 H) period. The D flip flop circuit is controlled to store therein the count value for the 1 H period.

That is, in FIG. 6, the horizontal sync signal H is supplied to the D flip flop circuit 51. An output signal Q from the circuit 51 is then fed to the D flip flop circuit 52 and a first input terminal of the OR gate circuit 53. Inputted to a second input terminal of the circuit 53 is an inverted output Q from the D flip flop circuit 52. An output signal from the OR gate circuit 53 is inputted to a Load terminal of the counter 54. Moreover, the output signal from the or gate circuit 53 is delivered as a latch timing (low active) signal to a control terminal of the D flip flop circuit 55. In the counter 54, when the Load terminal becomes active, the count value thereof is reset or cleared to zero and then there is commenced the operation to count the clock signal CLK inputted to the terminal CK. While the output from the OR circuit 53 is active (at a high level in FIG. 6), namely, during one 1 H period, the clock signal is counted such that when the signal from the OR gate circuit 53 is changed from the high level to the low level, the count operation is terminated and then the count value is fed from the counter 54 to the D flip flop circuit 55.

The circuit 55 is controlled to continuously output the count value memorized therein for the 1 H period to the decoder 56 in the subsequent stage.

In the decoder 56, the count value is compared with several mode values beforehand registered so as to set a bit associated with the mode value matching the count value. The resultant signal from the decoder 56 is outputted to the memory signal 4 of FIG. 5.

Referring now to FIG. 7, the vertical frequency discriminator 6 will be described. The input vertical sync signal H is fed to a clock input terminal of the counter 64 to conduct a count operation for one vertical period. The D flip flop circuit 65 is controlled to keep therein the count value for the vertical period.

That is, in FIG. 7, the vertical sync signal V is delivered to the D flip flop 61, which accordingly produces an output signal Q. The signal Q is supplied to the D flip flop circuit 62 and a first input terminal of the OR gate circuit 63. Inputted to a second input terminal of the circuit 63 is an inverted output signal Q from the D flip flop circuit 62. A resultant signal outputted from the OR gate circuit 63 is inputted to a Load terminal of the counter 64. Moreover, the signal from the OR gate circuit 63 is supplied as a latch timing (low active) signal to a control terminal of the D flip flop circuit 65. In the counter 64, when the load terminal becomes active, the internal count value is cleared to zero to start the count operation of the horizontal sync signal supplied to a terminal CK. During the signal from the OR gate circuit 63 is active (at a high level in FIG. 7), namely, during one vertical period, the horizontal sync signal H is counted. When the signal from the OR gate circuit 63 is altered from the high level to the low level, the count operation is stopped and then the count value is delivered from the counter 64 to the D flip flop 65.

Like in the horizontal frequency discriminator 5, the D flip flop circuit 65 is controlled to continuously output the first memorized count value to the decoder circuit 66 in the next stage.

In the circuit 66, the count value is compared with several mode values beforehand registered, thereby setting a bit related to the mode value matching the count value. The signal thus produced from the decoder 66 is fed to the memory circuit 4 of FIG. 5 in a manner similar to that of the horizontal frequency discriminator 5.

In the memory 4, control signals created respectively from the decoder circuits 56 and 66 in the preceding stages respectively of FIGS. 6 and 7 are delivered to an address input terminal of the memory circuit 4. In response thereto, as can be seen from FIG. 10, data beforehand stored in the memory 4 at addresses respectively associated therewith are read therefrom to be fed to the horizontal and vertical timing signal generators 1 and 2.

Referring to FIG. 10, for example, when the decoder 66 of the vertical frequency discriminator 6 outputs "01_H" (high-order bits in hexadecimal notation) and the decoder 56 of the horizontal frequency discriminator 5 outputs "02_H" (low-order bits in hexadecimal notation), "0102_H" (hexadecimal notation) is delivered to the memory 4 to be stored at the associated address. Supplied to the horizontal and vertical timing signal generators 1 and 2 is data of, for example "7C21_H" (hexadecimal notation).

In this regard, although the address data and output data respectively include 16 bits in the memory circuit 4, the bit configuration is selected only for simplicity of explanation. Furthermore, according to the output data (including 16 bits) from the memory 4, data of a predetermined bit width is allocated and supplied to each of the horizontal and vertical timing signal generators 1 and 2. The values of output data from the memory circuit 4 are substantially expressed in dots (pixels) and lines (scanning lines) in the horizontal and vertical directions, respectively. The memory 4 includes, for example, a read-only memory.

Subsequently, in the horizontal and vertical timing signal generators 1 and 2, operations are carried out as shown in FIG. 4 according to the data fed from the memory 4. FIG. 8A shows a relationship in phase between the input horizontal sync signal H, input video signal, and sync signal HS produced according to the embodiment; whereas, FIG. 8B shows a relationship in phase between the input vertical sync signal V, input video signal, and sync signal VS created in the embodiment.

As shown in FIGS. 8A and 8B, in response to the horizontal and vertical sync signals H and V inputted thereto, the system produces the sync signals HS and VS in a form matching the input mode by delaying the signals H and V by a period of time related to the value of data outputted from the memory 4. In other words, the display position (in the horizontal direction) is adjusted according to a phase difference positoncenteral central screen portion of the LCD panel. The disadvantage that the image is shifted from the center of the screen can be prevented.

Moreover, in accordance with the present invention, the frequency discriminator to attain the horizontal and vertical frequency modes from the horizontal and vertical sync signals and clock signal inputted thereto includes simple circuits such as counters and control circuits related thereto. The apparatus of the present invention is implemented by adding a memory circuit thereto, which consequently reduces the circuit size and production cost of the apparatus.

Additionally, in accordance with the present invention, when a circuit counducting conducting a fine adjustment is disposed between the memory circuit and the horizontal and vertical timing circuit generators, there is achieved a display control operation capable of conducting a fine adjustment of phases of signals from the timing signal generators. Consequently, the present invention is particularly favorable for a system in which the video signals are treated in the analog form.

Furthermore, the display controller in accordance with the present invention can be added to the circuit structure of the conventional liquid crystal display, which resultantly minimizes the production cost of the multiscan liquid crystal display.

While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by those embodiments but only by the appended claims. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.

Claims

1. A display controller of a multiscan liquid crystal display (lcd) using an lcd panel, comprising:

frequency discriminator means for attaining a mode of horizontal frequency and a mode of vertical frequency of video signals according to a horizontal sync signal, a vertical sync signal, and a clock signal inputted thereto;

memory circuit means for receiving as an input thereto data outputted from the frequency discriminator means and producing data matching a frequency inputted thereto; and

horizontal timing signal generator means and vertical timing signal generator means, responsive to data from the memory circuit means, for setting timing of controlling a display position of the video signals on the lcd panel.

2. A display controller of a multiscan lcd as claimed in claim 1, wherein the frequency discriminator means includes:

horizontal sync signal frequency discriminator means for receiving as inputs thereto the horizontal sync signal and the clock signal; and

vertical sync signal frequency discriminator means for receiving as inputs thereto the vertical sync signal and the horizontal sync signal,

the horizontal sync signal frequency discriminator means including a pixel counting section including a counter for counting the clock signal for one horizontal period of the horizontal sync signal,

the vertical sync signal frequency discriminator means including a line counting section including a counter for counting the horizontal sync signal for one vertical period of the vertical sync signal.

3. A display controller of a multiscan lcd as claimed in claim 2, wherein the horizontal sync signal frequency discriminator means includes a decoder for decoding a horizontal mode according to a count value of the counter.

4. A display controller of a multiscan lcd as claimed in claim 2, wherein the vertical sync signal frequency discriminator means includes a decoder means for decoding a vertical mode according to a count value of the counter.

5. A display controller of a multiscan lcd as claimed in claim 1, wherein the horizontal timing generator means includes a fine adjuster circuit means for correcting control data outputted from a memory circuit means in the frequency discriminator means.

6. A display controller of a multiscan lcd as claimed in claim 1, wherein the vertical timing generator means includes fine adjuster circuit means for correcting control data outputted from a memory circuit means in the frequency discriminator means.

7. A display controller of a multiscan lcd as claimed in claim 5, wherein the fine adjuster circuit means includes a circuit for performing an addition or a subtraction between a fine adjustment signal supplied from an external device and an output from the memory circuit means.

8. A display controller of a multiscan lcd as claimed in claim 6, wherein the fine adjuster circuit means includes a circuit for performing an addition or a subtraction between a fine adjustment signal supplied from an external device and an output from the memory circuit means.

9. A display control method for use with a multiscan liquid crystal display (lcd) using an lcd panel, comprising steps of:

attaining, according to a horizontal sync signal, a vertical sync signal, and a clock signal inputted thereto, a frequency mode of the horizontal frequency and a frequency mode of the vertical frequency of video signals;

referencing a look-up table according to the frequency modes and obtaining data matching a frequency inputted thereto; and

variably controlling, according to the data, generation of a horizontal timing signal and a vertical timing signal determining a display position of the video signals on the lcd panel.

10. A liquid crystal display (lcd) in which video signals of a plurality of signal standards can be displayed, wherein a display controller for said lcd comprises:

a pixel counter that determines a number of pixels per line of an image;

a line counter that determines a number of lines per image;

a memory that stores data corresponding to predetermined numbers of pixels and lines, which data is read out of the memory based on the number of pixels and the number of lines determined by the pixel counter and the line counter;

a horizontal timing signal generator and a vertical timing signal generator that set the timing by which video signals are displayed on the lcd based on data retrieved from the memory to thereby control the position of an image displayed on the lcd.

11. A liquid crystal display according to claim 10, wherein the pixel counter counts the number of pixels during one period of a horizontal sync signal.

12. The liquid crystal display according to claim 10, wherein the line counter counts the number of pulses of a horizontal sync signal during one period of a vertical sync signal.

13. The liquid crystal display according to claim 10, wherein the memory stores data corresponding to more than four display modes.

14. The liquid crystal display according to claim 10, further comprising an adder/subtracter to adjust the phase of a timing signal that determines the position of an image displayed on the lcd.

15. The liquid crystal display according to claim 14, further comprising an external adjusting input for receiving input data for manual adjustment of the position of an image displayed on the lcd.

16. A method for displaying video signals of a plurality of signal standards on a liquid crystal display (lcd), comprising:

counting a number of pixels per line of an image;

counting a number of lines per image;

retrieving from a memory data corresponding to predetermined numbers of pixels and lines, which data is read out of the memory based on the counted number of pixels and the counted number of lines;

setting the timing by which video signals are displayed on the lcd based on data retrieved from the memory to thereby control the position of an image displayed on the lcd.

17. The method according to claim 16, wherein the number of pixels is counted during one period of a horizontal sync signal.

18. The method according to claim 16, wherein the number of pulses of the horizontal sync signal is counted during one period of a vertical sync signal.

19. The method according to claim 16, wherein the memory stores data corresponding to more than four display modes.

20. The method according to claim 16, further comprising adjusting the phase of a timing signal that determines the position of an image displayed on the lcd.

21. The method according to claim 18, further comprising inputting data corresponding to a manual adjustment of the position of an image displayed on the lcd.

22. A liquid crystal display (lcd) in which video signals of a plurality of signals standards can be displayed, wherein a display controller for said lcd comprises:

a first counter that determines a number of first pulses appearing during a first period of time based on a horizontal sync signal;

a second counter that determines a number of second pulses appearing during a second period of time based on a vertical sync signal;

a memory that stores data corresponding to predetermined number of first and second pulses, which data is read out of the memory based on the number of first pulses and the number of second pulses determined by the first and second counters; and

a timing signal generator that sets the timing in horizontal and vertical directions by which video signals are displayed on the lcd in response to the data read out of the memory to thereby control the position of an image displayed on the lcd.

23. The liquid crystal display according to claim 22, wherein a clock signal is used as the first pulses and said horizontal sync signal is used as the second pulses.

24. A method for displaying video signals of a plurality of signal standards on a liquid crystal display (lcd), comprising:

counting first pulses during a first period of time based on a horizontal sync signal;

counting second pulses during a second period of time based on a vertical sync signal;

retrieving from a memory data corresponding to predetermined numbers of first and second pulses, which data is based on the counted numbers of the first and second pulses; and

setting the timing by which video signals are displayed on the lcd based on the data retrieved from the memory to thereby control the position of an image displayed on the lcd.

25. The method according to claim 24, wherein a clock signal is used as the first pulses and the horizontal sync signal is used the second pulses.