A user configurable circuit contains clock logic, a switching element and a data path circuit. input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.
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0. 19. A method for configuring a circuit comprising the steps of:
receiving a plurality of user configurable inputs for configuring said circuit; receiving a clock input; generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; receiving an input signal for said circuit in a switching element including at least one pass gate; receiving some of said conditional clock signals in said switching element; generating a logic output from said switching element, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and providing a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
0. 1. A circuit comprising:
a plurality of user configurable inputs for configuring said circuit; clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; a switching element including at least one pass gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said pass gate; and a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
0. 10. A programmable logic device (PLD) comprising:
a plurality of user configurable inputs for configuring said PLD; at least one macrocell, coupled to receive said user configurable inputs, said macrocell comprising: clock logic coupled to said user configurable inputs and coupled to receive a clock input, said clock logic for generating conditional clock signals to implement a logic function for said circuit based on said clock input and said user configurable inputs; a switching element including at least one transmission gate coupled to said clock logic to receive some of said conditional clock signals and coupled to receive an input signal for said circuit, said switching element for generating a logic output, in accordance with said conditional clock signals, to implement said logic function by controlling propagation of said input signal through said transmission gate; and a data path circuit coupled to receive said logic output and some of said conditional clock signals for providing additional functionality, wherein propagation delay through said switching element to said data path circuit is independent of said user configurable inputs.
0. 40. A method for configuring a circuit, comprising the steps of:
(a) generating a set of conditional clock signals in response to a clock input and a plurality of configurable inputs; (b) implementing a logic function at a switch comprising at least one pass gate, said switch receiving an input signal; (c) generating a logic output from the switch in accordance with at least one of the conditional clock signals; and (d) controlling propagation of the input signal through the switch in accordance with at least one of the conditional clock signals.
0. 20. A circuit comprising:
a plurality of configurable inputs; clock logic generating a plurality of conditional clock signals in response to a clock input and the configurable inputs, the conditional clock signals implementing a logic function; a pass gate controlling propagation of an input signal and generating a logic output in accordance with at least one of the conditional clock signals; and a data path circuit receiving (i) the logic output of the pass gate and (ii) at least one of the remaining conditional clock signals, the data path circuit providing additional functionality.
0. 38. A programmable logic device, comprising:
a plurality of configurable inputs; clock logic generating a plurality of conditional clock signals in response to a clock input and the configurable inputs, the conditional clock signals implementing a logic function; a pass gate controlling propagation of an input signal and generating a logic output in accordance with at least one of the conditional clock signals; and a data path circuit receiving (i) the logic output of the pass gate and (ii) at least one of the remaining conditional clock signals, the data path circuit providing additional functionality.
0. 2. The circuit as set forth in
0. 3. The circuit as set forth in
0. 4. The circuit as set forth in
0. 5. The circuit as set forth in
0. 6. The circuit as set forth in
0. 7. The circuit as set forth in
0. 8. The circuit as set forth in
said user configurable inputs comprise a D-type register select, a T-type resister select, a latch select and a polarity select; said logic function implemented in said clock logic comprises a multiplexer function, for selecting among a D-type flip-flop, a T-type flip-flop and a latch, said logic function comprises a toggle function for implementing a T-type flip-flop, and said logic function comprises a polarity function for generating a true or a bar output for said circuit; and said data path circuit comprises a master latch, coupled to receive said logic output, and a slave latch coupling said master latch and said circuit output.
0. 9. The circuit as set forth in
a three state inverter coupled to said input signal and being controlled by said clock logic for inverting said input data in accordance with said D-type register select, said T-type resister select, and said polarity select; and a transmission gate coupled to said input signal and being controlled by said clock logic for passing said input data in accordance with said D-type register select, said T-type resister select, and said polarity select.
0. 11. The programmable logic device as set forth in
0. 12. The programmable logic device as set forth in
0. 13. The programmable logic device as set forth in
0. 14. The programmable logic device as set forth in
0. 15. The programmable logic device as set forth in
0. 16. The programmable logic device as set forth in
0. 17. The programmable logic device as set forth in
said user configurable inputs comprise a D-type register select, a T-type resister select, a latch select and a polarity select; said logic function implemented in said clock logic comprises a multiplexer function, for selecting among a D-type flip-flop, a T-type flip-flop and a latch, said logic function comprises a toggle function for implementing a T-type flip-flop, and said logic function comprises a polarity function for generating a true or a bar output for said circuit; and said data path circuit comprises a master latch, coupled to receive said logic output, and a slave latch coupling said master latch and said circuit output.
0. 18. The programmable logic device as set forth in
a three state inverter coupled to said input signal and being controlled by said clock logic for inverting said input data in accordance with said D-type register select, said T-type resister select, and said polarity select; and a transmission gate coupled to said input signal and being controlled by said clock logic for passing said input data in accordance with said D-type register select, said T-type resister select, and said polarity select.
0. 21. The circuit of
0. 22. The circuit of
0. 23. The circuit of
0. 24. The circuit of
0. 25. The circuit of
0. 26. The circuit of
0. 27. The circuit of
0. 28. The circuit of
0. 29. The circuit of
0. 30. The circuit of
0. 31. The circuit of
0. 32. The circuit of
0. 33. The circuit of
0. 34. The circuit of
0. 35. The circuit of
0. 36. The circuit of
0. 37. The circuit of
0. 39. The device of
0. 41. The method of
0. 42. The method of
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This is a continuation of application Ser. No. 08/360,469, filed Dec. 20, 1994, now U.S. Pat. No. 5,502,403.
The present invention relates to the field of programmable logic devices, and more particularly to a high speed programmable macro cell with a propagation delay independent of the configuration.
In general, programmable logic devices (PLDs) permit a user to configure the PLD device to accommodate a wide spectrum of applications. One type of PLDs has a programmable macro cell. The programmable macro cell provides the capability of defining the architecture of each output individually. Each of the potential outputs may be specified to be "registered" or "combinatorial". In addition, the polarity of each output may also be individually selected allowing complete flexibility of the output configuration. In addition, further configurability is provided through "array" configurable "output enable" for each potential output. This feature allows the outputs to be reconfigured as inputs on an individual basis, or alternatively, used as a combinational I/O controlled by the programmable array. An example of such a PLD device is manufactured by Cypress Semiconductor Corporation, the Assignee of the present invention.
The macro cell circuit 100 contains an exclusive OR gate (XOR) 102, a register 120, and a plurality of transmission gates 105, 110, 152 and 154. The XOR gate 102 implements the toggle function for the T-type flip-flop. As is shown in
The "Data In" is input to the XOR 102 and a transmission gate 105. If a D-type flip-flop is specified by the static control signals, then the transmission gate 105 conducts the "data in" signal to a transmission gate 115. If the static control signals specify a T-type flip-flop, then the output of the XOR gate 102 is coupled to the transmission gate 115 via the transmission gate 110.
During a clock transition from a high state to low logic state, the data input to transmission gate 115 is passed to the master latch. Also, during the high state to low logic state transition, the transmission gates 125 and 140 are
The clock logic 210 receives both the plurality of user configurable inputs, and the clock. In a preferred embodiment, the user configurable inputs are set or programmed by the user in an initialization period. Specifically, the user configurable inputs are programmed into a non-volatile memory, thereby storing user configurable bits in a PLD application. In the preferred embodiment, the user configurable bits are stored in an electrically erasable programmable read only memory (EEPROM). In an alternative embodiment, the user configurable inputs may be stored in a register, such as a serial shift register or a static random access memory (SRAM). After the initialization period, and upon powering of the user configurable circuit 200, the user configurable inputs do not change state, and therefore are characterized as pseudo DC signals. The circuitry utilized to set the user configurable input during the initialization period is well known in the art and will not be described further. The clock logic 210 generates a conditional clock signals205 , labeled as conditional clock signals 0-m on FIG. 2.
The switching element 205 receives the conditional clock signals "0-m" and the data input. In general, the clock logic 210 and the switching element 205 implement at least one logic function for the user configurable circuit 200. For example, the clock logic 210 and the switching element 205 may implement a multiplexing function to select among three configurations such as a D-Type flip flop, T-type flip-flop and latch. The output of the switching element 205 is, coupled to the input of data path circuit 215. The data path circuit 215 may comprise any type of circuit, such as a registered or combinational, used to implement the user configurable circuit. One embodiment for the data path circuit 215 is described more fully below. The output of data path circuit 215 is labeled "data output" on FIG. 2. The output of data path circuit 215 is also coupled to the clock logic 210 to provide implementation of certain flip flop functions.
In one embodiment, the switching element 205 gates the data input with the clock to provide synchronous operation between the input data and the data path circuit 215. In a preferred embodiment, the switching element 205 contains at least one gating or pass gate element, such as a transmission gate. However, the transmission gate may include any type of pass gate, such as a three state inverter or a switching transistor, without deviating from the spirit or scope of the invention. One embodiment for gating the input data in the switching element 205 is described more fully below. The conditional clock signals, generated in the clock logic 210, are utilized to gate the input data in the switching element 205.
The switching element 205 and the data path circuit 215 constitute the data path for the user configurable circuit 200, and the clock logic 210 provides the clock path for the user configurable circuit 200. Consequently, the critical path for reducing delay of the user configurable circuit 200 lies in the data path (e.g. data being propagated through the switching element 205 and data path circuit 215) and the clock path. In general, the user configurable circuit 200 is constructed such that most of the processing to implement the logic function or logic functions are done prior to an active clock (e.g. in the clock logic 210). Because the user configurable inputs are available as pseudo DC signals after power-up, most of the processing for the logic function occurs prior to receiving data for input to the data path. Also, because the operation of the data path circuit 215 requires gating the data, no additional delay is introduced to implement the logic function or logic functions in the switching element 205. Because of the decrease in gates in the data path, propagation delay through the user configurable circuit 200 is reduced.
In general, the clock logic 310 and the D/T/L element 320 executes the toggle function, the polarity function, and a multiplexing function to select among the T-type flip-flop, the D-type flip-flop or latch configuration. The data input is received in the D/T/L element 320. The D/T/L element 320 is coupled to the register 330, and the data are output from the register 330. The data output are also input to the clock logic 310 in order to implement the T-type flip-flop function.
During a configuration period for the user configurable circuit 300, the function select and the polarity select signals are set. After the user configurable circuit 300 is powered up, the clock logic 310 generates the conditional clock signals in accordance with the function select and polarity select signals and the clock signal. During the rising edge of the clock, the data input are gated in the D/T/L element 320 in accordance with the conditional clock signals. The propagation delay in the D/T/L element 320 is equal to the propagation delay from one transmission gate. During the falling edge of the clock, data are latched in the register 330. The control of the data through the register 330 is also conducted by the conditional clock signals.
As discussed above in conjunction with
The CLK 1 and {overscore (CLK1+L )} signals control the enabling of the three state inverter 335, and the CLK 2 and {overscore (CLK2+L )} signals control the transmission gate 332. The {overscore (CLK3+L )} signal controls the p channel transistors in transmission gates 342 and 348, and the CLK 3 signal controls the n channel transistors in transmission gates 342 and 348. The {overscore (CLK4+L )} signal controls the p channel transistor in transmission gate 358, and the CLK 4 signal controls the n channel transistor in transmission gate 358. In addition, the {overscore (CLK5+L )} signal controls the n p channel transistor in transmission gate 350, and the CLK 5 signal controls the p n channel transistor in transmission gate 350.
In operation, data are input to the D/T/L element 420 on the {overscore (Data In)} line. If the configurable circuit 300 is operating in the D-type flip-flop mode, and the polarity select indicates a bar output, then the CLK 1 and {overscore (CLK1+L )} signals disable the three state inverter 335, and the CLK 2 and {overscore (CLK2+L )} signals toggles the transmission gate 332. For the embodiment illustrated in
As shown in
If the T-type select function is active, the {overscore (Data In)} is "1", and the slave latch 355 stores a "0", then the CLK 1 and {overscore (CLK1+L )} signals enable the three state inverter 335, and the CLK 2 and {overscore (CLK2+L )} signals disable the transmission gate 332. However, if the T-type select is active, {overscore (Data In)} is "1", and the slave latch 355 stores a "1", then the CLK 1 and {overscore (CLK1+L )} signals disable the three state inverter 335, and the CLK 2 and {overscore (CLK2+L )} signals enable the transmission gate 332.
When the user configurable circuit 400 is operating in the latch mode, the {overscore (Data In)} is passed directly to the register 430. Therefore, for operation in the latch mode with bar output, the CLK 1 and {overscore (CLK1+L )} signals disable the three state inverter 335, and the CLK 2 and {overscore (CLK2+L )} signals enable the transmission gate 332 independent of the clock signal. For latch mode with true output, CLK2 and {overscore (CLK2+L )} disable transmission gate 332 and CLK1 and {overscore (CLK1+L )} signals enable three state inverter 335 independent of clock signal. Regardless of the true or bar output, when operating in the latch mode, transmission gate 358 is enabled with the CLK 4 and {overscore (CLK4+L )} signals to bypass the master latch.
In the rising edge of the clock, data is passed from the {overscore (DataIn)} to the output of the D/T/L element 420 as described above, and the data is latched in the master latch 345 when operating in both the T-type and D-type modes. When the user configurable circuit 400 is operating in the latch mode, the CLK 4 and {overscore (CLK4+L )} signals enable the transmission gate 358 to pass data from the output of the D/T/L element 420 to the slave latch 355. In all modes of operation, the data is latched in the slave latch 355 and the data is output from the master latch 345 during the falling edge of the clock.
For the user configurable circuit 400, the user configurable bits are C2, C3 and C4, and define the configuration of the circuit (e.g. toggle mode, latch mode, and polarity select). Specifically, the user configurable bits C2, C3 and C4 define the operation of the user configurable circuit 400 as follows:
C4=POLARITY ACTIVE HIGH
As shown in
Where
AND
The equations may be implemented using well known circuits. Table 1 below provides a truth table corresponding to the equations above.
| TABLE 1 | ||||||||||
| Clock | {overscore (Clk)} | |||||||||
| Cycle | Slave | C4 | C3 | C2 | Clkb | Clk1 | Clk2 | Clk3 | Clk4 | Clk5 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 4 | 0 | 0 | 0 | 1 | 1 | 0 1 | 0 | 0 | 0 | 1 |
| 5 | 0 | 0 | 1 | 0 | 0 | 0 | 0 1 | 0 | 1 | 0 |
| 6 | 0 | 0 | 1 | 0 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 7 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 8 | 0 | 0 | 1 | 1 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 9 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 10 | 0 | 1 | 0 | 0 | 1 | 0 1 | 0 | 0 | 0 | 1 |
| 11 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 12 | 0 | 1 | 0 | 1 | 1 | 0 1 | 0 | 0 | 0 | 1 |
| 13 | 0 | 1 | 1 | 0 | 0 | 0 1 | 0 | 0 | 1 | 0 |
| 14 | 0 | 1 | 1 | 0 | 1 | 0 1 | 0 | 0 | 0 | 1 |
| 15 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 16 | 0 | 1 | 1 | 1 | 1 | 0 1 | 0 | 0 | 0 | 1 |
| 17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 18 | 1 | 0 | 0 | 0 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 19 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 20 | 1 | 0 | 0 | 1 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 21 | 1 | 0 | 1 | 0 | 0 | 0 | 0 1 | 0 | 1 | 0 |
| 22 | 1 | 0 | 1 | 0 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 23 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 24 | 1 | 0 | 1 | 1 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 25 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 26 | 1 | 1 | 0 | 0 | 1 | 0 1 | 0 | 0 | 0 | 1 |
| 27 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 28 | 1 | 1 | 0 | 1 | 1 | 0 | 0 1 | 0 | 0 | 1 |
| 29 | 1 | 1 | 1 | 0 | 0 | 0 1 | 0 | 0 | 1 | 0 |
| 30 | 1 | 1 | 1 | 0 | 1 | 0 1 | 0 | 0 | 0 | 1 |
| 31 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
| 32 | 1 | 1 | 1 | 1 | 1 | 0 1 | 0 | 0 | 0 | 1 |
In a preferred embodiment, in addition to the logic shown in
The present invention has application for use in a programmable macro cell.
Although the present invention has been described in terms of specific exemplary embodiments, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.
Raza, Syed Babar, Nazarian, Hagop, Liu, Lin-Shih, Ansel, George M., Douglass, Stephen M., Hunt, Jeffrey Scott
| Patent | Priority | Assignee | Title |
| 7816946, | Jan 31 2008 | MICROSEMI SOC CORP | Inverting flip-flop for use in field programmable gate arrays |
| 7932745, | Jan 31 2008 | MICROSEMI SOC CORP | Inverting flip-flop for use in field programmable gate arrays |
| 8255854, | Sep 22 2006 | MICROSEMI SOC CORP | Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit |
| Patent | Priority | Assignee | Title |
| 4593205, | Jul 01 1983 | Motorola, Inc. | Macrocell array having an on-chip clock generator |
| 4870302, | Mar 12 1984 | XILINX, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
| 4903233, | Jun 20 1986 | Sharp Kabushiki Kaisha | Word processor having capability of continuously entering documents into a column or a block of an editing system |
| 4914322, | Dec 16 1988 | Lattice Semiconductor Corporation | Polarity option control logic for use with a register of a programmable logic array macrocell |
| 5027315, | Sep 28 1984 | Lattice Semiconductor Corporation | Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions |
| 5121006, | Apr 22 1991 | ALTERA CORPORATION A CORPORATION OF DELAWARE | Registered logic macrocell with product term allocation and adjacent product term stealing |
| 5159278, | Apr 02 1991 | ADELANTE TECHNOLOGIES B V | State machine architecture providing increased resolution of output timing |
| 5164612, | Apr 16 1992 | SAMSUNG ELECTRONICS CO , LTD ; CECIL H KAPLINSKY BYPASS TRUST DATED NOVEMBER 11, 1999, THE; VESSELINA KAPLINSKY MARITAL TRUST DATED NOVEMBER 11, 1999, THE | Programmable CMOS flip-flop emptying multiplexers |
| 5191243, | May 06 1991 | LATTICE SEMICONDUCTOR CORPORATION, A CORPORATION OF DE | Output logic macrocell with enhanced functional capabilities |
| 5225724, | Oct 22 1990 | SGS-THOMSON MICROELECTRONICS S R L | Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit |
| 5254886, | Jun 19 1992 | Actel Corporation | Clock distribution scheme for user-programmable logic array architecture |
| 5280203, | May 15 1992 | ALTERA CORPORATION, A DELAWARE CORPORATION | Look-ahead asynchronous register set/reset in programmable logic device |
| 5300830, | May 15 1992 | Micron Technology, Inc | Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control |
| 5302866, | Mar 18 1993 | XILINX, Inc.; Xilinx, Inc | Input circuit block and method for PLDs with register clock enable selection |
| 5332929, | Apr 08 1993 | XILINX, Inc.; Xilinx, Inc | Power management for programmable logic devices |
| 5376849, | Dec 04 1992 | International Business Machines Corporation | High resolution programmable pulse generator employing controllable delay |
| 5391942, | Jun 19 1992 | Actel Corporation | Clock distribution scheme for user-programmable logic array architecture |
| 5424654, | Sep 22 1994 | SAMSUNG ELECTRONICS CO , LTD ; CECIL H KAPLINSKY BYPASS TRUST DATED NOVEMBER 11, 1999, THE; VESSELINA KAPLINSKY MARITAL TRUST DATED NOVEMBER 11, 1999, THE | Programmable macrocell circuit |
| 5426380, | Sep 30 1994 | Sun Microsystems, Inc. | High speed processing flip-flop |
| 5457409, | Aug 03 1992 | Lattice Semiconductor Corporation | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices |
| 5473266, | Apr 19 1993 | ALTERA CORPORATION, A DELAWARE CORPORATION | Programmable logic device having fast programmable logic array blocks and a central global interconnect array |
| 5489857, | Aug 03 1992 | Lattice Semiconductor Corporation | Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
| 5502403, | Dec 20 1994 | Cypress Semiconductor Corporation | High speed configuration independent programmable macrocell |
| 5506878, | Jul 18 1994 | XILINX, Inc.; Xilinx, Inc | Programmable clock having programmable delay and duty cycle based on a user-supplied reference clock |
| 5512766, | Oct 10 1990 | Renesas Electronics Corporation | Semiconductor integrated circuit device |
| 5528170, | Nov 04 1992 | Lattice Semiconductor Corporation | Low-skew signal routing in a programmable array |
| 5532500, | Sep 01 1993 | NEC Corporation | Semiconductor integrated circuit device having clock signal wiring construction for suppressing clock skew |
| 5565792, | Jan 28 1993 | XILINX, Inc. | Macrocell with product-term cascade and improved flip flop utilization |
| 5570051, | Jan 28 1993 | XILINX, Inc. | Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization |
| 5594365, | Aug 03 1992 | Lattice Semiconductor Corporation | Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device |
| 5621338, | Dec 20 1994 | Cypress Semiconductor Corp. | High speed configuration independent programmable macrocell |
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