Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.
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9. A semiconductor device comprising:
a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers; wherein a threshold voltage of each of the transistors in each of the sense amplifiers is varied in accordance with the operating condition of the sense amplifiers.
6. A semiconductor device comprising:
a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers; wherein when said sense amplifiers start to operate, voltage of the data lines is varied to effectively boost an absolute value of the gate-source voltage of transistors in each of the sense amplifiers.
8. A semiconductor device comprising:
a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, and common driving lines for driving said sense amplifiers; wherein said sense amplifiers operate with a voltage amplitude higher than that of the data lines and each of said sense amplifiers includes an inverter which operates with a voltage amplitude as that of the data lines.
1. A semiconductor device comprising:
a plurality of data line pairs, a plurality of word lines intersecting said plurality of data line pairs, memory cells located at the intersecting points, sense amplifiers each for amplifying a difference voltage of a data line pair of said plurality of data line pairs to a first voltage in a term of an amplifying operation, and a common driving line pair for driving said sense amplifiers; wherein the voltage amplitude between said common driving line pair is made larger than the maximum value of said first voltage between the data line pair in a part of the term of the amplifying operation.
0. 82. A semiconductor device comprising:
a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, CMOS sense amplifiers each for amplifying a memory cell signal read out on each of the data lines to a first potential or a second potential, a precharge circuit for precharging the plurality of data lines to a third potential which is a half of the first and second potentials, and common driving lines for driving said CMOS sense amplifiers; wherein when said CMOS sense amplifiers start to operate, voltage of the data lines is varied to effectively boost an absolute value of the gate-source voltage of transistors in each of the CMOS sense amplifiers.
5. A semiconductor device comprising:
a plurality of data lines, a plurality of word lines intersecting the plurality of data lines, memory cells located at the intersecting points, sense amplifiers each for amplifying a memory cell signal read out on each of the data lines, common driving lines for driving said sense amplifiers, and an internal voltage generator to generate a first internal voltage; wherein said first internal voltage is substantially an intermediate value between a first external voltage and a second external voltage when the difference between the first and second external voltages is larger than a first reference voltage, whereas the difference between the first internal voltage and one of the external voltages is made constant when the difference between the first and the second external voltages is larger than a second reference voltage.
0. 53. A semiconductor device comprising:
a first node and a second node for receiving a first voltage defined by a first potential and a second potential; a first circuit block including a first gate circuit having a first MISFET with a first conduction type, a second MISFET with the first conduction type, a third MISFET with a second conduction type, and a fourth MISFET with the second conduction type which are coupled in series between the first node and the second node; a bias voltage supplying circuit having a third node coupled to the gate of the second MISFET and a fourth node coupled to the gate of the third MISFET, wherein the bias voltage supplying circuit supplies a first bias potential to the third node and a second bias potential to the fourth node, and wherein the gate of the first MISFET is prepared to receive a first signal having an amplitude that is smaller than the first voltage and the gate of the fourth MISFET is prepared to receive a second signal having an amplitude that is smaller than the first voltage.
0. 69. A semiconductor device comprising:
a plurality of memory cells located at the intersecting points of a plurality of data lines and a plurality of word lines; an X-decoder for selecting one of the plurality of word lines, driving the selected word line to a first potential, and driving non-selected word lines of the plurality of word lines to a second potential, a plurality of sense amplifiers each coupled to a corresponding data line of said plurality of data lines and for amplifying the corresponding data line to one of a third potential and a fourth potential; a first driving line coupled to first power receiving nodes of said plurality of sense amplifiers; a second driving line coupled to second power receiving nodes of said plurality of sense amplifiers; a sense amplifier driving circuit for driving said first driving line to the third potential and driving said second driving line to the fourth potential, wherein the first potential is higher than the third potential, the third potential is higher than the fourth potential and the fourth potential is higher than the second potential.
0. 13. A semiconductor device comprising:
a first circuit block having a plurality of circuits and being operative by a first voltage which is defined by a first potential and a second potential; and a voltage generator producing a first bias potential which is determined with reference to the first potential and a second bias potential which is determined with reference to the second potential, wherein each of the plurality of circuits includes a first MISFET with a first conduction type, a second MISFET with the first conduction type, a third MISFET with a second conduction type, and a fourth MISFET with the second conduction type which are coupled in series between the first potential and the second potential, wherein the first bias potential is supplied to the gate of the second MISFET and the second bias potential is supplied to the gate of the third MISFET, and wherein the gate of the first MISFET is prepared to receive a first signal having an amplitude that is smaller than the first voltage and the gate of the fourth MISFET is prepared to receive a second signal having an amplitude smaller than the first voltage.
0. 72. A semiconductor device comprising:
a voltage converter circuit having a first power receiving node coupled with an operating voltage and an output node for outputting an internal voltage; and a circuit block having a second power receiving node coupled to the output node, wherein said semiconductor device has a first operation mode and a second operation mode, wherein when the operating voltage is in a first voltage range, said voltage converter circuit supplied the internal voltage at a first voltage changing rate opposing the change of the operating voltage and at an amplitude smaller than the operating voltage in both the first and second operation modes, and wherein when the operating voltage is in a second voltage range larger than the first operating voltage range, said voltage converter circuit supplies the internal voltage at the first voltage changing rate and at an amplitude smaller than the operating voltage at the first operation mode, and the internal voltage at a second changing rate, which is positive and larger than the first voltage changing rate, opposing the change of the operating voltage in the second operation mode.
0. 78. A semiconductor device comprising:
a plurality of dynamic memory cells each having a first MISFET with N-type and a capacitor; and a peripheral circuit for selecting one of the plurality of memory cell and read a data stored therein or write a date thereto and including a plurality of second MISFETs with N-type, a plurality of third MISFETs with N-type, a plurality of fourth MISFETs with P-type, wherein said semiconductor device is formed in a semiconductor substrate with P-type, wherein the first MISFETs of the plurality of memory cells are formed in a first semiconductor region with P-type isolated from said semiconductor substrate with P-type by a second semiconductor region with N-type, wherein the plurality of second MISFETs are formed in a third semiconductor region with P-type isolated from said semiconductor substrate with P-type by a fourth semiconductor region with N-type, wherein the plurality of third MISFETs are formed in said semiconductor substrate with P-type, wherein plurality of fourth MISFETs are formed in a fifth semiconductor region with N-type, and wherein said semiconductor substrate is coupled with a ground potential and the first semiconductor region and the third semiconductor region are coupled with a negative potential lower than the ground potential.
0. 60. A semiconductor device comprising:
a plurality of memory cells located at the intersection points of a plurality of data line pairs and a plurality of word lines; a plurality of sense amplifiers each for amplifying a difference voltage of a corresponding data line pair of said plurality of data line pairs to a first voltage; a first driving line coupled to first power receiving nodes of said plurality of sense amplifiers; a second driving line coupled to second power receiving nodes of said plurality of sense amplifiers; a precharge circuit for precharging said plurality of data line pairs, said first driving line, and said second driving line to a precharge voltage; a first voltage supplying circuit for supplying the first voltage; a second voltage supplying circuit for supplying a second voltage which is larger than the first voltage; and a switching circuit inserted between said first and second driving lines and said first and second voltage supplying circuits; wherein when said plurality of sense amplifiers begin an amplifying operation, said switching circuit has: a first period for making the voltage between said first and second driving lines larger than the first voltage by making a current path between said second voltage supplying circuit and said first and second driving lines which have been at the precharge voltage; and a second period for making the voltage between said first and second driving lines the first voltage by making a current path between said first voltage supplying circuit and said first and second driving lines after the first period. 0. 42. A semiconductor device comprising:
a first circuit block being operative by a first voltage; and a second circuit block being operative by a second voltage which is larger than the first voltage and is defined by a first potential and a second potential, wherein said second circuit block includes an output circuit which receives a first signal outputted from the first circuit block and outputs a second signal having an amplitude that is larger than that of the first signal, wherein the output circuit further includes a level converter circuit which receives the first signal, a first inverter circuit, and a second inverter circuit, wherein the level converter circuit includes a 1st MISFET, a 2nd MISFET, a 3rd MISFET, and a 4th MISFET which are coupled in series between the first potential and the second potential, wherein the level converter circuit includes a 5th MISFET, a 6th MISFET, a 7th MISFET, and an 8th MISFET which are coupled in series between the first potential and the second potential, wherein the level converter circuit includes a first coupling node between the 5th MISFET and the 6th MISFET and a second coupling node between the 7th MISFET and the 8th MISFET, wherein the gates and drains of the 1st and the 5th MISFETs are cross-coupled together, wherein the first signal is supplied to the gate of the 4th MISFET and inverted the first signal is supplied to the gate of the 8th MISFET, wherein the first inverter circuit includes a 9th MISFET, a 10th MISFET, an 11th MISFET, and a 12th MISFET which are coupled in series between the first potential and the second potential, wherein the first inverter circuit further includes a third coupling node between the 9th MISFET and the 10th MISFET and a fourth coupling node between the 11th MISFET and the 12th MISFET, wherein the gate of the 9th MISFET is coupled to the first coupling node and the gate of the 12th MISFET is coupled to the second coupling node, wherein the second inverter circuit includes a 13th MISFET, a 14th MISFET, a 15th MISFET, and a 16th MISFET which are coupled in series between the first potential and the second potential, wherein the second inverter circuit further includes a fifth coupling node between the 14th MISFET and the 15th MISFET, wherein the gate of the 13th MISFET is coupled to a third coupling node and the gate of the 16th MISFET is coupled to the fourth coupling node, and wherein the fifth coupling node can output the second signal.
2. A semiconductor device according to
wherein the common driving line pair is one of a plurality of common driving line pairs and, wherein the voltage of one of said common driving line pairs is boosted by boosting capacitors.
3. A semiconductor device according to
first, second and third power supply lines, and three switches connecting said first, second and third power supply lines with said common driving line pair respectively; wherein the voltage between said first and second power supply lines is larger than the voltage between said second and third power supply lines which is substantially equal to the maximum value of said first voltage between the data line pair.
4. A semiconductor device according to
wherein one of the voltages of the power supply lines is generated on the chip.
7. A semiconductor device according to
10. A semiconductor device according to
11. A semiconductor device according to
12. A semiconductor device according to
0. 14. A semiconductor device according to
wherein each of the plurality of circuits further includes, a first coupling node between the first MISFET and the second MISFET, a second coupling node between the third MISFET and the fourth MISFET, and a third coupling node between the second MISFET and the third MISFET, wherein the first coupling node can output a first output signal having an amplitude that is smaller than a difference voltage between the first potential and the first bias potential, wherein the second coupling node can output a second output signal having an amplitude that is smaller than a difference voltage between the second potential and the second bias potential, and wherein the third coupling node can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.
0. 15. A semiconductor device according to
wherein the channel conductance of the second MISFET is larger than that of the first MISFET, and wherein the channel conductance of the third MISFET is larger than that of the fourth MISFET.
0. 16. A semiconductor device according to
wherein one of the plurality of circuits is an inverter circuit including the first, second, third, and fourth MISFETs, wherein the inverter circuit further includes a first coupling node between the first MISFET and the second MISFET, a second coupling node between the third MISFET and the fourth MISFET, and a third coupling node between the second MISFET and the third MISFET, wherein the first coupling node can output a first output signal having an amplitude that is smaller than the first voltage, wherein the second coupling node can output a second output signal having an amplitude that is smaller than the first voltage, and wherein the second coupling node can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.
0. 17. A semiconductor device according to
wherein one of the plurality of circuits is an output circuit which receives a third signal with a first amplitude outputted from the second circuit block and outputs a fourth signal with a second amplitude which is larger than the first amplitude, wherein the output circuit includes a level converter circuit which receives the third signal, a first inverter circuit which receives a set of signals outputted from the level converter circuit, and a second inverter circuit which receives a set of signals outputted from the first inverter circuit and outputs the fourth signal, and wherein each of the level converter circuit, the first inverter circuit, and the second inverter circuit includes the first, second, third, and fourth MISFETs.
0. 18. A semiconductor device according to
0. 19. A semiconductor device according to
wherein the NAND circuit further includes a fifth MISFET with the first conduction type having a source-drain path that is coupled in parallel with the source-drain path of the first MISFET and a sixth MISFET with the second conduction type having a source-drain path that is coupled between one end of the source-drain path of the fourth MISFET and the second potential, wherein the NAND circuit further includes a set of first input nodes which are the gates of the first and fourth MISFETs, a set of second input nodes which are the gates of fifth and sixth MISFETs, a first coupling node between the first MISFET and the second MISFET, a second coupling node between third MISFET and the fourth the MISFET, and a third coupling node between the second MISFET and the third MISFET, wherein the set of first input nodes are prepared to receive the first signal and the second signal, respectively, wherein the set of second input nodes are prepared to receive a fifth signal and a sixth signal, respectively, each of the fifth and sixth signals having an amplitude that is smaller than the first voltage, wherein the first coupling node can output a first output signal having an amplitude that is smaller than the first voltage, wherein the second coupling node can output a second output signal having an amplitude that is smaller than the first voltage, and wherein the second coupling node can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.
0. 20. A semiconductor device according to
wherein one of the plurality of circuits is a tri-state output buffer circuit including a NAND circuit, a NOR circuit, and an output driver, and wherein each of the NAND circuit, the NOR circuit, and the output driver includes the first, second, third, and fourth MISFETs.
0. 21. A semiconductor device according to
wherein the NAND circuit further includes a set of first input nodes which are the gates of the first and fourth MISFETs of the NAND circuit to which a set of first input signals are supplied, and a first output node from which a first output signal is outputted, wherein the NOR circuit further includes a set of second input nodes which are the gates of the first and fourth MISFETs of the NOR circuit to which a set of second input signals are supplied, and a second output node from which a second output signal is outputted, wherein the output driver further includes a set of third input nodes which are the gates of the first and fourth MISFETs of the output circuit, and a coupling node between the second and third MISFETs, wherein the first output node is coupled to one the set of third input nodes and the second output node is coupled to another one of the set of the third input nodes, and wherein the coupling node of the output driver can output a third output signal having an amplitude that is larger than that of the first output signal or the second output signal.
0. 22. A semiconductor device according to
wherein the amplitude of the third output signal is substantially the same as the first voltage.
0. 23. A semiconductor device according to
wherein said semiconductor device is formed on a chip, wherein one of the plurality of circuits is an input circuit which receives an input signal from an outside of the chip and includes the first, second, third, and fourth MISFETs, wherein the input circuit further includes a fifth MISFET with the first conduction type having one end of the source-drain path that is coupled to the gate of the first MISFET and having a gate that is coupled to the gate of the second MISFET, and a sixth MISFET with the second conduction type having one end of the source-drain path that is coupled to the gate of the fourth MISFET and having a gate that is coupled to the gate of the third MISFET, wherein the input circuit further includes a first coupling node between the first MISFET and the second MISFET, and a second coupling node between the third MISFET and the fourth MISFET, wherein another end of the source-drain path of the fifth MISFET and another end of the source-drain path of the sixth MISFET are coupled together and the input signal is supplied thereto, wherein the first coupling node can output a first output signal having an amplitude that is smaller than a difference voltage between the first potential and the first bias potential, and wherein the second coupling node can output a second output signal having an amplitude that is smaller than a difference voltage between the second potential and the second bias potential.
0. 24. A semiconductor device according to
0. 25. A semiconductor device according to
0. 26. A semiconductor device according to
wherein the first potential has a first changing rate according to the variation of the first voltage and the second potential has a second changing rate according to the variation of the first voltage, wherein when the first voltage is in a first predetermined voltage range, the first bias potential has a third changing rate according to the variation of the first voltage and the second bias potential has a fourth changing rate according to the variation of the first voltage, and wherein the third changing rate is larger than the fourth changing rate.
0. 27. A semiconductor device according to
wherein the first changing rate is larger than the second changing rate, and wherein the third changing rate is proportional to the first changing rate, and the fourth changing rate is proportional to the second changing rate.
0. 28. A semiconductor device according to
wherein the third changing rate is substantially equal to the first changing rate, and the fourth changing rate is substantially equal to the second changing rate.
0. 29. A semiconductor device according to
wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block.
0. 30. A semiconductor device according to
wherein the first conduction type is a P-channel and the second conduction type is an N-channel, and wherein said semiconductor device is a microprocessor LSI in a chip.
0. 31. A semiconductor device according to
wherein when the first voltage is in a second predetermined voltage range which is larger than the first predetermined voltage range, the first bias potential has a fifth changing rate according to the variation of the first voltage and the second bias potential has a sixth changing rate according to the variation of the first voltage, and wherein the fifth changing rate is smaller than the third changing rate and sixth changing rate is larger than the fourth changing rate.
0. 32. A semiconductor device according to
0. 33. A semiconductor device according to
0. 34. A semiconductor device according to
0. 35. A semiconductor device according to
wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block.
0. 36. A semiconductor device according to
0. 37. A semiconductor device according to
0. 38. A semiconductor device according to
wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block.
0. 39. A semiconductor device according to
wherein said semiconductor device is a microprocessor LSI chip, and wherein the second circuit block is an internal circuit block and the first circuit block is an interface circuit block between the internal circuit and an outside of the microprocessor LSI chip.
0. 40. A semiconductor device according to
0. 41. A semiconductor device according to
wherein said semiconductor device is a microprocessor LSI chip, wherein a thickness of a gate insulator layer of said MISFETs in said first circuit block is substantially the same as that of MISFETs included in said second circuit block, and wherein the first voltage is an external voltage supplied from an outside of the microprocessor LSI chip.
0. 43. A semiconductor device according to
wherein the first bias potential is supplied to the gates of the 2nd, 6th, 10th, and 14th MISFETs and the second bias potential is supplied to the gates of the 3rd, 7th, 11th, and 15th MISFETs.
0. 44. A semiconductor device according to
wherein the channel conductance of the 2nd, 6th, 10th, and 14th MISFETs is larger than that of the 1st, 5th, 9th, and 13th MISFETs, and wherein the channel conductance of the 3rd, 7th, 11th, and 15th MISFETs is larger than that of the 4th, 8th, 12th and 16th MISFETs.
0. 45. A semiconductor device according to
0. 46. A semiconductor device according to
wherein the first potential is higher than the second potential, the first bias potential is lower than the first potential, and the second bias potential is higher than the second potential, wherein the first potential has a first changing rate according to the variation of the second voltage and the second potential has a second changing rate according to the variation of the second voltage, wherein when the second voltage is in a first predetermined voltage range, the first bias potential has a third changing rate according to the variation of the second voltage and the second bias potential has a fourth changing rate according to the variation of the second voltage, and wherein the third changing rate is larger than the fourth changing rate.
0. 47. A semiconductor device according to
wherein when the second voltage is in a second predetermined voltage range which is larger than the first predetermined voltage range, the first bias potential has a fifth changing rate according to the variation of the second voltage and the second bias potential has a sixth changing rate according to the variation of the second voltage, and wherein the fifth changing rate is smaller than the third changing rate and sixth changing rate is larger than the fourth changing rate.
0. 48. A semiconductor device according to
0. 49. A semiconductor device according to
0. 50. A semiconductor device according to
0. 51. A semiconductor device according to
0. 52. A semiconductor device according to
wherein said semiconductor device is a microprocessor LSI chip, and wherein the first circuit block is an internal circuit block and the second circuit block is an interface circuit block between the internal circuit and an outside of the microprocessor LSI chip.
0. 54. A semiconductor device according to
wherein the first potential is higher than the second potential, the first bias potential is lower than the first potential, and the second bias potential is higher than the second potential, and wherein when the first voltage is varied in a predetermined voltage range, the changing rate of the second bias potential is smaller than that of the first potential.
0. 55. A semiconductor device according to
a fifth node and a sixth node for receiving a second voltage defined by a voltage between the second potential and a fifth potential which is higher than the second potential; and a second circuit block, including a second gate circuit having a fifth MISFET with the first conduction type and a sixth MISFET with the second conduction type which are coupled in series between the fifth node and the sixth node and having a logical amplitude of the second voltage, wherein the second voltage is smaller than the first voltage, and wherein a thickness of a gate insulator layer of each of the first to sixth MISFETs is substantially the same.
0. 56. A semiconductor device according to
0. 57. A semiconductor device according to
wherein said semiconductor device is formed on a chip, and wherein the first gate circuit is a tri-state output buffer circuit and outputs one of the first potential, the second potential, and a floating state to an outside of the chip from a coupling node between the second MISFET and the third MISFET.
0. 58. A semiconductor device according to
0. 59. A semiconductor device according to
0. 61. A semiconductor device according to
wherein said switching circuit includes a first MISFET having a source-drain path coupled between a first node and said first driving line, a second MISFET having a source-drain path coupled between a second node and said first driving line, and a third MISFET having a source-drain path coupled between a third node and said second driving line, and wherein the first voltage is supplied between the second node and the third node and the second voltage is supplied between the first node and third node.
0. 62. A semiconductor device according to
wherein each of said plurality of memory cells has a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein the first node is coupled with a first potential, the second node is coupled with a second potential lower than the first potential, and the third node is coupled with a ground potential lower than the second potential.
0. 63. A semiconductor device according to
0. 64. A semiconductor device according to
wherein said semiconductor device is formed on a semiconductor chip, wherein each of said plurality of memory cells has a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, wherein the precharge voltage is half of the first voltage, and wherein said first voltage supplying circuit includes a voltage generating circuit which receives an operating voltage larger than the first voltage from the outside of the semiconductor chip and generates the first voltage.
0. 65. A semiconductor device according to
wherein said semiconductor device is formed on a semiconductor chip, wherein each of said plurality of memory cells has a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein said second voltage supplying circuit includes a voltage generating circuit which receives an operating voltage smaller than the second voltage from the outside of the semiconductor chip and generates the second voltage.
0. 66. A semiconductor device according to
wherein said switching circuit includes a first switch coupled between a first node and said first driving line, a second switch coupled between a second node and said first driving line, a third switch coupled between a third node and said second driving line, and a fourth switch coupled between a fourth node and said second driving line, and wherein the first voltage is supplied between the second node and third node and the second voltage is supplied between the first node and the fourth node.
0. 67. A semiconductor device according to
wherein each of said plurality of memory cells includes a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein the first node is coupled with a first potential, the second node is coupled with a second potential lower than the first potential, the third node is coupled with a third potential lower than the second potential, and the fourth node is coupled with a ground potential lower than the third potential.
0. 68. A semiconductor device according to
wherein each of said plurality of memory cells includes a MISFET and a capacitor, wherein each of said plurality of sense amplifiers includes a p-channel MISFET pair cross-coupled with each other and an n-channel MISFET pair cross-coupled with each other, and wherein the first node is coupled with a first potential, the second node is coupled with a second potential lower than the first potential, the third node is coupled with a ground potential lower than the second potential, and the fourth node is coupled with a negative potential lower than the ground potential.
0. 70. A semiconductor device according to
wherein each of said plurality of memory cells includes a switching MISFET and a capacitor having a first electrode coupled to a source-drain path of the switching MISFET and a second electrode, and wherein the second potential is a ground potential.
0. 71. A semiconductor device according to
a plate wiring coupled to the second electrodes of said plurality of memory cells; and a plate driving circuit for driving the plate wiring to the third potential when the plurality of word lines are not selected and driving said plate wiring to a fifth potential lower than the fourth potential when one of the plurality of word lines is selected; a precharge circuit for precharging said plurality of data lines to a precharge voltage having a potential half way between the third and fourth potentials; a voltage generating circuit for generating the fourth and fifth potentials from an operating voltage higher than the fourth and fifth potentials.
0. 73. A semiconductor device according to
wherein said semiconductor device is formed on a semiconductor chip, wherein said voltage converter circuit has a node for receiving a control signal which indicate the first and second operation modes, and wherein the control signal is generated by information supplied from outside of the semiconductor chip.
0. 74. A semiconductor device according to
a first reference voltage circuit supplying a first reference voltage to be a standard of the first voltage changing rate, a second reference voltage circuit supplying a second reference voltage to be a standard of the second voltage changing rate, and a switching circuit for selecting one of the first reference voltage and the second reference voltage according to the control signal.
0. 75. A semiconductor device according to
0. 76. A semiconductor device according to
0. 77. A semiconductor device according to
wherein the first voltage changing rate is substantially zero, wherein the second operation mode is an aging operation mode of said semiconductor, and wherein said circuit block includes a memory circuit having a plurality of memory cells each having a MISFET and a capacitor.
0. 79. A semiconductor device according to
0. 80. A semiconductor device according to
0. 81. A semiconductor device according to
wherein the first semiconductor region is a first P-well, wherein the second semiconductor region is a second N-well formed in the semiconductor substrate and the first P-well is formed in the second N-well, wherein the third semiconductor region is a third P-well, wherein the fourth semiconductor region is a fourth N-well formed in the semiconductor substrate and the third P-well is formed in the fourth N-well, and wherein the fifth semiconductor region is a fifth N-well formed in the semiconductor substrate.
0. 83. A semiconductor device according to
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This application is a continuation of application Ser. No. 07/366,869 filed Jun. 14, 1989, now U.S. Pat. No. 5,297,097.
The present invention relates to a large scale integrated circuit, and more particularly to a high-density integrated semiconductor device constituted by a voltage converter circuit and miniaturized devices (devices with small dimension) which can keep up with a wide range of an operating power-supply voltage and kinds of power supplies, i.e. a large scale integrated circuit in which integrated on a monolithic chip are a microcomputer, a logic circuit, a dynamic RAM (random access memory), a static RAM, a ROM (read-only memory), etc.
In recent years, onto the market have come portable electronic machines such as a lap-top type personal computer, an electronic pocket notebook, etc., and portable electronic media machines such as a solid-state voice recorder which performs voice recording without using a magnetic medium, a solid-state camera (electronic still camera) which performs image recording without using the magnetic medium. In order for these portable electronic machines to be widely popularized, it is indispensable to realize an ultra large scale integrated circuit (ULSI) which permits a battery based operation or an information (data) retention operation using a battery (battery back-up). On the other hand, there has been increased demand for a semiconductor disk, which can provide higher speed accessing than a magnetic disk, as a large-capacity-file memory system for implementing a computer with higher performance. And this semiconductor disk requires a very large-capacity memory LSI which can perform the information using a battery.
The ULSIs used for these applications must satisfy the following requirements.
(1) The operation in a wide range of operating power supply voltage (1-5.5 V). This requirement permits one-chip ULSI to be adapted for many kinds of power supplies including, e.g. 5 V which is a standard power supply voltage for the present TTL compatible digital LSI, 3.3 V which is one candidate for the standard power supply voltage for the future TTL reversible digital LSI, 3-3.6 V which is a typical output voltage of a primary cell of lithium, etc., 1.2 V which is a typical output voltage of a secondary cell of cadmium and nickel, and so on.
(2) The measures for a secular change or time-dependent fluctuation (for a short period or long period) in the power supply voltage. This requirement removes fear of operation failure due to voltage fluctuation resulting from the secular change in the cell voltage and the switching of power supply in shifting between the operation under a nominal condition and a battery back-up operation.
(3) The power reduction in the standard operation or the battery back-up operation. This requirement permits a small-sized battery to operate the ULSI for a long period.
(4) The reduction in a switching current. This requirement decreases voltage fluctuation caused by switching in the battery voltage, thus preventing the operation failure.
One example of the product of microprocessor which operates in a wide range of the operating voltage is disclosed in the 4-bit microprocessor handbook, p 148 published by NIPPON DENKI Co., Ltd. The product name is μPD7507SC. The range of the power supply voltage in this microprocessor is 2.2-6.0 V. Information in a data memory (static RAM) is retained with a minimum voltage of 2 V. In this memory, the recommendable voltage is generally 5 V for the operating power supply voltage and for 2 V the data retention.
An example of the dynamic memory for battery back-up in which power consumption in the data retention (refresh) is decreased is disclosed in IEEE, Journal of Solid-State Circuits. Vol. 23, No. 1, pp. 12-18, February 1988. The power supply voltage is 5 V for both nominal operation and data retention.
An example in which an external voltage is dropped to be supplied to an internal circuit is disclosed in U.S. Pat. No. 4,482,985.
An example of the battery back-up for a memory is disclosed in U.S. Pat. No. 4,539,660.
A technique for changing the plate voltage of a dynamic RAM is disclosed in Japanese Patent Publication No. 61-61479.
The battery back-up of a static RAM is disclosed in the catalogue published by Hitachi, Ltd., pp. 44-45.
The other relevant references and patent publications will be identified in the following description.
The present invention intends to lower the operation voltage of a system provided on a monolithic chip so that the operation speed is not affected by changes in the power supply voltage supplied from the outside.
The present invention has been accomplished by devising voltage converter means which is capable of stably supplying a fixed voltage in a wide range of power-supply voltage. The voltage converter means in the present invention is referred to as means including at least one amplifier which generates an output voltage on the basis of an input reference voltage, and is different from means of only dropping voltage using resistors, etc.
In the present invention, it is also critical to improve a dynamic RAM which is the biggest obstacle against lowering the operation voltage. This is because the dynamic RAM requires a refresh operation even during data retention due to its dynamic operation and so does not permit only the operation voltage during data retention to be lowered unlike the static RAM.
The microprocessor and static RAM as mentioned above have a wide range of the operating power-supply voltage of 2-5 V. However, since they are designed around the power supply voltage of 5 V, the operation speed thereof (the highest clock frequency in the case of the microprocessor and access time in the case of the static RAM) is not assured for the operation outside the recommended fluctuation (generally, +10%) in the power supply voltage. Particularly at a low power supply voltage, it is common that the operation speed is greatly lowered. The dependency of the operation speed on the power-supply voltage is different with the products. Therefore, the operation speed of a system must be designed to accord with the lowest one of the operation speeds of LSIs constituting the system. This made it impossible to provide a necessary performance of the system for the operation outside at 5 V and difficult to design the system for the operation at a low power supply voltage.
These LSIs, the lowest operating power supply voltage of which is 2.2 V, are difficult to adapt to all of many power kinds of power supply voltages as mentioned above, which is a restriction to system design. Further, the dynamic RAM to be incorporated in the system, the lowest operating power supply voltage of which is 4.5 V, are further difficult to adapt to the many kinds of power supply voltages. Particularly, the absence of different between the power supply voltage for normal operation and that for data retention made very complicated the arrangement of a power supply switching circuit, thereby making the data retention difficult.
Meanwhile, with rapid development of miniaturization (scaling down) of semiconductor devices, by using the processing technology lower than 0.5 μm, it is possible to constitute a so-called system LSI in which several LSI blocks are integrated on a monolithic chip. In such a system LSI, it is required that the operating power-supply voltage ranges and operating speeds of the respective LSI blocks are aligned with each other. However, as mentioned above, only combining the conventional LSIs could not constitute such a system LSI.
The present invention can be constituted by an LSI circuit block which has a power down mode suited for battery back-up can operate at a low power supply voltage of about 1 V at the minimum; a power supply voltage converter circuit which supplies an internal power supply voltage suitable to the operating mode to the LSI; and an input/output circuit for converting the signal amplitude.
By operating the main LSI block, which performs storage and processing of information, at a substantially fixed low voltage regardless of the external power supply voltage, it is possible to provide substantially constant operation speed performance over a wide range of the power supply voltage. The external power supply voltage can be reduced to the operation voltage of the LSI block as required so that power consumption during data retention can be reduced to a necessary and minimum value and also a battery back-up circuit can be simplified in its constitution. Further, the optimum operation voltage according to the characteristic of miniaturized devices constituting the main LSI block can be set independently of the external power supply voltage so that performances of high integration degree, high operation speed, and low power consumption can be obtained simultaneously.
An object of the present invention is to provide a large scale integrated circuit (LSI) which can operate at a fixed operation speed against wide range fluctuation of an operating power supply voltage.
Another object of the present invention is to provide voltage converter means which can produce a constant output voltage against wide range fluctuation of the operating power supply voltage.
Still another object of the present invention is to reduce power consumption in an LSI and particularly the power consumption during battery based operation.
Yet another object of the present invention is to prevent operation failure of an LSI which performs a low voltage operation.
A further object of the present invention is to provide an LSI with a plurality of input/output levels.
A further object of the present invention is to provide a dynamic RAM which can perform a low voltage operation.
A further object of the present invention is to improve a sense amplifier used for the dynamic RAM which performs a low voltage, and its operation.
These and other objects and many of the attendant advantages of the present invention will be readily appreciated as the same become better understood by reference the following detailed description when considered in connection with the accompanying drawings.
The present invention intends to an LSI which can operate at a wide range of an operating power supply voltage (for example 1 to 5.5 V). The following description discloses four techniques roughly classified:
(1) a voltage converter (limiter) which can produce a stabilized internal power supply voltage even in a wide range of the operating power supply voltage,
(2) an input/output buffer which can be adapted to several input/output levels,
(3) a dynamic RAM which can operate at a power supply voltage of 2 V or less, and
(4) a sense amplifier suited for the dynamic RAM operating at a low voltage and its operation.
These techniques enables one (single) chip LSI to perform a stabilized operation by many kinds of power supplies including a battery (e.g. 1.2 V) to a normal power supply (e.g. 5 V). It is apparent that the following embodiments can be combined and also it can be understood by those skilled in the art that only necessary parts may be adopted without aparting from the spirit of the present invention.
Numerals 5a and 5b are a main circuit block, respectively. Numeral 5 is a collection thereof. Numeral 6 is a power supply power converter circuit block for converting a power supply voltage Vcc supplied from the outside of the LSI chip into internal power supply voltages VCL1, and VCLn for the respective circuit blocks. In the power supply voltage converter circuit, numerals 6a and 6c are a converter circuit for normal operation, respectively, and numerals 6b and 6d are a converter circuit for data retention.
In the present invention, the external power supply voltage Vext in a wide range (e.g. 1-5.5 V) so that only one power supply voltage can not cover this wide range. This is because the power supply voltage converter circuits in the present invention serve to produce output voltages (VCL1, VCL2) on the basis of an input reference voltage VL. For this reason, a plurality of the power supply voltage converter circuits are provided.
The power supply voltages for the circuit blocks are produced on the basis of the reference voltage as mentioned above. For this reason, if the external power supply voltage Vext or the battery voltage Vbt becomes equal to the reference voltage VL (or the internal voltage VCL1-VCL2), the operation of the voltage converting circuits become unstable. For such a case, a switch 6a is provided to connect the external power supply voltage with the circuit blocks 5a and 5b.
In an example of the present invention, the internal power supply voltages (e.g. VCL1, VCL2) for the main circuit blocks 5a and 5b are adapted to be 1.5 V. In this case, if the external power supply voltage varies in a wide range of 1.5 V to 3.6 V, it is difficult to produce the internal power supply voltage using only one voltage converter. For this reason, a plurality of the voltage converter circuits L1 and L1B are provided. The voltage converter circuit L1b mainly serves to convert the power supply voltage of 2.5 to 3.6 V into 1.5 V to be supplied to the main circuit 5a (C1) and the voltage converter L1B mainly serves to convert the power supply voltage 1.5 to 2.5 V to be supplied to the main circuit 5a. Switching of L1 and L1B is controlled by a data retention state signal PD as described later.
Generally, the operation voltage and current required during data retention may be smaller than during normal operation so that even when the current to be consumed in the voltage converter circuits is reduced to lower the driving capability thereof, any trouble does not occur. This enables the current consumed in the entire LSI chip to be remarkably reduced together with reduction in the power consumption in the main circuit blocks. Incidentally, although in this example, switching is made between two voltage converter circuits, three or more voltage converters may be provided. Also, only one voltage converter circuit may be used to vary its output voltage and power consumption.
As mentioned above, SW6a and SW6c are a switch for directly apply the power supply voltage Vcc to the circuit blocks when Vcc is decreased to a value substantially equal to VCL1 or VCLW. By using this switch to turn off the voltage converter circuits, the consumed current can be further reduced. Although in the above example, the power supply voltage converter circuit 6 is constituted by a plurality of switches and a plurality of voltage converter circuits, only one voltage converter circuit may be used when viewed in a block form as long as the same effect can be obtained.
Numeral 9 is a circuit for generating the reference voltage V on the basis of which the internal power supply voltage VCL1 or VCL2 is created. Numeral 8 is a circuit for generating a signal PD indicative of the data retention operation state. Although the signal PD can be generated through several techniques, there is here adopted a method of comparing the power supply voltage Vcc with a reference voltage Vcx and producing the signal PD when the former is smaller than the latter. Numeral 10 is a circuit for generating a limiter enable signal LM. If the external power supply voltage is higher than the internal power supply voltage, thereby operating the voltage converter circuit (voltage limiter), LM of a high voltage ("1") is generated whereas if the external power supply voltage is decreased to a value equal to the internal power supply voltage, LM of a low voltage of ("0") is generated. In the latter case, the external power supply voltage is directly applied to the main circuit block and also the voltage converter is not operated to restrain power consumption. In the example as shown, when the power supply voltage Vcc is compared with the reference voltage Vcx, and LM is generated if the former is larger than the latter. The output voltage and consumed current of the power supply voltage converter circuit 6 can be changed using the above two signals PD and LM.
Numeral 7 is an input/output buffer circuit; numeral 11 is an input/output bus for transmitting/receiving control signals and data between the inside and the outside of the chip; and numeral 12 is an internal bus which is within the chip and serves to transmit/receive control signals and data. The input/output buffer circuit 7, which also serves as a voltage level converting circuit, can transmit/receive the control signals and data even if the logic swing in the chip does not coincide with that in the outside. In the data retention operation state, the control signals and data are not required to be transmitted/received between the inside and the outside of the chip so that the input/output buffer circuit 7 is turned off by the data retention state signal PD. Thus, the power consumption can be reduced.
Further, as a value of the input reference voltage VL in the power supply voltage converter circuit, 1.5 V itself which is the internal power supply voltage is not adopted. This is due to the following two reasons:
(1) If the power supply voltage is close to the reference voltage level, the voltage stabilizing characteristic of the reference voltage generating circuit is generally deteriorated, thereby reducing the reference voltage level.
(2) The upper limit of the in-phase input range in the differential amplifier circuit is generally slightly lower than the power supply voltage level. Therefore, in order to sufficiently use the characteristic of the differential amplifier circuit, the input reference voltage is desired to be lower than the power supply voltage (1.5 V at the minimum).
By setting the input reference voltage at a level lower than the minimum value of the power supply voltage, the power supply voltage converter circuit can be stably operated in the range where difference between the external power supply voltage and the internal power supply voltage is small. Incidentally, L1 and L1B are activated by a {overscore (PD)} signal and PD signal, respectively.
Further, in the above example, a bipolar transistor is used in L1 and a p-channel MOS transistor is used in L1B. However, a p-channel MOS may be used for L1 and L1B. Also in this case, since the phase characteristic of the circuits can be individually designed, a more stabilized power supply converter circuit can be provided than the case where only one voltage converter is used. Moreover, by means of the combination of the other devices without being limited to that of the above devices, if the voltage condition adapted for the characteristic of the devices is selected, a power supply voltage converter circuit which can operate in a wide range of the power supply voltage.
By means of such a circuit, it is possible to provide an LSI which can operate with the operation speed (response speed) even when a power supply voltage varies in a wide range. The operation speed can be represented by an access time for a memory and a maximum clock frequency for a microcomputer (CPU). The memory access time includes an address access time which is a time from an address change to data output, a chip select (or chip enable) access time which is a time from input of a chip select (or chip enable) signal to data output and a RAS (or CAS) access time in the case of DRAM which is a time from input of an address strobe signal RAS (or CAS) to data output. As these access times are shorter, the amount of data transfer per unit time can be increased, thereby improving the processing performance of a system. In accordance with the present invention, these operation speeds can be made substantially constant and also elements used in the system can operate at a higher speed than the conventional low voltage operating elements through circuit contrivance and contrivance in element designing (e.g. setting of a threshold voltage) so that the performance of the system can be greatly improved.
where Vcc (min) is a minimum value of the power supply voltage for normal operation, VBT(max) is a maximum value of the power supply voltage for data retention, and Vcx is the reference voltage. Further, although the internal power supply voltage VcL is set at 1.5 V, it may be set at a suitable value corresponding to the operation characteristic of the circuit within a range not exceeding the power supply voltage Vcc. Moreover, in this example, in order to directly supply the power supply voltage Vcc which is 1.5 V or less to the internal circuit, VLX is set at 1.5 V.
In operation, in the case where Vcc is high and so is to be decreased to the internal power supply voltage, the limiter enable signal LM becomes a high voltage ("1"). Then, T1 is cut off and also T3 is made conductive, thereby supplying a bias current to the differential amplifier circuit A1. Thus, the voltage proportional to VL at a non-inverting input of A1 is output. On the contrary, when the signal LM is a low voltage ("1"), T3 is cut off and the bias current is not supplied. Then, Vcc is directly output as the internal power supply voltage.
During the data retention operation, the data retention signal PD becomes a high voltage ("1"). Then, T2 is cut off, thereby stopping the current supply to the circuit block 5d. On the other hand, T4 is cut off and so the value of the bias current to the differential amplifier circuit A1 is defined. The current consumed by the memory cell array in the data retention state is very small and can be regarded as a substantially constant D.C. current in time lapse. Therefore, the load driving capability of the differential amplifier circuit may be much smaller than that in the normal operation so that even if the bias current is remarkably decreased, any difficulty in operation does not occur. Also by making T5 conductive to increase the feed-back amount in the differential amplifier circuit, the internal power supply voltage for the data retention is decreased. Thus, the consumed current in the entire LSI chip during the data retention can be remarkably decreased. Incidentally, in this embodiment, VL=0.75 V, and R4=R6=3R5. Then, VCL2 is 1.5 V for the normal operation and 1.0 V for data retention.
In the embodiment mentioned above, there can be realized a static memory which can operate at a high speed during the normal operation and retain data with necessary minimum power during the data retention operation, and an LSI which locally incorporates such a static memory. Incidentally, in this embodiment, the static memory cells with high resistance load are used. However, the present invention can be also applied to the memory array which is constituted by CMOS memory cells each constituting of two CMOS inverters and two selective transistors, or latch circuits consisting of two NAND gates or two NOR gates.
Meanwhile, in the dynamic memory, data are stored by storing charges in the storage capacitors Cs1 so that so-called refresh operation in which signal charges are periodically read out and rewritten is required also in the data retention operation and to this end, a part of the peripheral circuit other than the memory cell array must be operated. Further, in order to assure sufficient noise margin, also in the data retention, the signal charge amount equivalent to in the normal operation must be assured. Then, in this embodiment, the internal power supply voltage is fixed at 1.5 V for both data retention and normal operation.
During the data retention, it is not necessary to perform the input/output of data between the inside and outside of the chip, so that all the input/output buffers are cut off by a data retention signal PD. The multiplexer 26 is controlled by the signal PD to switch the memory addresses into the addresses from the refresh address generator circuit 25 in the data retention operation. During the refresh operation, the refresh signal RFSH is at a high voltage level ("1"). This signal is supplied to the refresh address generator circuit 25 to sequentially increase or decrease the refresh address. Also the signal RFSH activates the clock generator circuit 21 to generate clocks for refresh.
The internal power supply voltage VCL is supplied from a power supply voltage converter circuit 6f of a p-channel MOS-FET T14 serving as a switch (
In operation, in the case where Vcc is high and so is to be decreased to the internal power supply voltage, the limiter enable signal LM becomes a high voltage ("1"). Then, T14 is cut off and also T15 is made conductive, thereby supplying a bias current to the differential amplifier circuit A2. Thus, the voltage proportional to VL at an non-inverting input of A2 is outputted. On the contrary, when the signal LM is a low voltage ("1"), T15 is cut off and the bias current is not supplied. Then, Vcc, which is at a low voltage level, is directly outputted as the internal power supply voltage.
During the data retention operation, the data retention signal PD is at the high voltage level ("1"). Then, the transistor T16 is cut off and the bias current for the differential amplifier A2 is defined by the resistor R3. The current consumed in the data retention state and in a period when the peripheral circuit does not operate is small. Therefore, the load driving capability of the differential amplifier circuit may be much smaller than that in the normal operation so that even if the bias current is remarkably decreased, any difficulty in operation does not occur. During the refresh operation, the signal RFSH is fed back to the power supply voltage converter circuit to make the transistor T17 conductive, thereby making the bias current for A2 substantially equivalent to that in the normal operation. In this way, during the refresh operation, the power supply current required for charging/discharging of data lines and operation of the peripheral circuit can be supplied. Therefore, also in the data retention operation, the current consumed in the entire chip can be remarkably decreased without lowering the noise margin. Incidentally, in this embodiment, with VL=0.75 V and R10=R11, the internal power supply voltage VCL32 1.5 V is obtained, but the other combination of the voltages and resistances may be adopted.
In the embodiment mentioned above, a so-called address multiplex system in which a row address and column address are taken in under time exchange is used. However, the present invention can be applied to a general system in which all address are simultaneously taken in. Further, by using a dynamic memory as described later in which the plate is driven to reduce the voltage amplitude in data lines, a memory with further reduced power consumption can be realized.
In operation, the counter 30 is operated by the clock φ1 and starts count from the state where a high voltage ("1") is applied to a reset terminal to reset all of the counter outputs at a low voltage ("0"). When the count becomes 4097, the counter output Q12 becomes a high voltage ("1"), the counting is stopped. In
In the embodiment mentioned above, there can be realized a dynamic memory which can operate at a high speed during the normal operation and retain data with necessary minimum power during the data retention operation, and an LSI which locally incorporates such a dynamic memory. Further, even if the external power supply voltage greatly fluctuates, which is problematic for the conventional dynamic memory, the dynamic memory in accordance with this embodiment can stably operated by operating the internal circuit at a low voltage of e.g. 1.5 V.
Although in the embodiments hereinbefore, a difference between the normal operation state and the data retention state is detected by the detection means provided on the LSI chip, the operation state may be controlled from the exterior of the chip
In such an arrangement, even when the external power supply voltage varies in a wide range of 1 to 3.6 V, an LSI which can-operate at several power supply voltages can be provided without sacrificing the operation performance of the main circuit. Further, the chip can be switched into a low power consumption mode such as data retention mode as required through external control, thereby reducing the power required during the operation using a battery.
With reference to the embodiments mentioned above, the basic idea of the LSI chip in which the main circuit block operates at the voltage of 1.5 V or less has been explained. In the following description, more detailed embodiments will be explained mainly in relation to a dynamic memory. It has been considered generally that the dynamic memory is difficult to operate at a low voltage as compared with a logic LSI or a static memory. The first reason is that the signal charge amount defined by a product of a storage voltage and storage capacitance is reduced due to voltage lowering, thereby decreasing the SIN. Therefore, it has been considered difficult to assure the noise margin for noise charge generated due to irradiation of rays emitted from a small amount of radioelements which are contained in a package and metallic wirings or noise charge due to leakage current, induced by thermal (or non-thermal) carrier generation, flowing into memory cells. These problems can be solved by one of the following two techniques.
(1) Using of a circuit which can provide the memory cell storage signal voltage (e.g. low voltage=0 V and high voltage=3 V) substantially equivalent to the conventional technique also at a low voltage power supply voltage (e.g. 1.5 V). In this case, the storage capacitance of the memory cells may be a value (e.g. 30 to 40 fF) substantially equivalent to the conventional technique.
(2) Increasing the storage capacitance of the memory cells in substantial inverse proportion to a power supply voltage in compensation for using the conventional circuit system. For example, when the power supply voltage is 1.5 V, the memory cell storage capacitance is set at 60 to 80 fF.
In connection with the technique of (1), disclosed in an embodiment described later is a technique in which by driving the plate of the memory cells as well as word lines and data lines, the signal amplitude larger than that in the data lines is stored in the memory cells. And, in connection with the technique of (2), a technique of remarkably increasing the storage capacitance as compared with the conventional technique is disclosed in JP-A-60-26711 and 1988 Symposium on VLSI Technology, Digest of Technical Papers, pp. 29-30, 1988. By means of these techniques, the storage signal charge required for stabilized operation can be assured.
The second problem to be solved for the low voltage operation is to simultaneously realize a high speed operation and low current consumption. The third problem is to realize a device or circuit which permits a low voltage operation circuit and a high voltage operation circuit to be integrated on the same chip. The third problem φ1, particularly problematic when the voltage ratio of a high voltage source to a low voltage source is 2 or more. A technique in which the third problem can be solved by two kinds of devices for low and high voltages are formed on the same chip is disclosed in U.S. Pat. No, 4,482,985. This technique permits the circuits for both the low and high voltage power sources to be constructed using optimized devices but a disadvantage that the production process of an LSI is made complicated. In connection with the embodiment explained below, explanation will be given for means for solving the second problem and operating at a minimum power supply voltage of 1 V and a method for solving the third problem without complicating the production process. By means of these techniques, the operation power supply voltage of the dynamic memory is reduced to 1 to 1.5 V or so, and the high integration degree, high speed, and low power consumption of the dynamic memory or the LSI chip locally incorporating it can be realized simultaneously. Also, the condition required for battery operation or battery back-up operation can be satisfied.
First, the means for solving the second problem will be explained. Although in the following example, a Complementary MOS-FET (CMOS-FET) is used, a bipolar transistor, junction transistor or device of material other than silicon may be used as long as the same effect is obtained.
The device of the case 1 has the following three problems.
(1) Fluctuation of the gate threshold voltage for variation of the channel length is large so that the case 1 is inferior in the controllability as compared with the case 2, thus making it difficult to provide a short channel. This is because the substrate voltage is set at -1 V.
(2) The substrate bias voltage, which is generated by a substrate bias voltage generator circuit provided on a chip, fluctuates due to production unevenness and also greatly varies in dine lapse depending on the number of operating circuits. Therefore, the gate threshold voltage, which is strongly modulated by the substrate bias voltage, can not satisfy the condition required for the low voltage operation with high accuracy.
(3) Since the substrate voltage is 0 V while the power supply is active, the gate threshold voltage is placed at a value lower than 0.3 V (e.g. 0 V) due to the body effect (see the broken line in FIG. 12B). Also, the substrate is substantially in a floating state so that the substrate voltage is transiently increased due to capacitive coupling with Vcc thereby making the gate threshold voltage minus. Thus, the MOS-FET in a peripheral circuit is made conductive so that a large transient current flows.
On the other hand, the present invention, in which the substrate voltage is set at VSS=0 V, can provide an LST chip with excellent controllability of the gate threshold voltage and with a small transient current during closure of the power supply source. Further, by externally supplying the ground voltage, variation of the substrate voltage during the circuit operation can be made approximately zero so that capacitive coupling noise from the substrate voltage can be greatly decreased.
The reason why the substrate voltage fluctuates is that the conventional substrate bias generator circuit is formed on the chip and so does not have sufficient driving capability.
The reason why the substrate voltage (-3 V) is conventionally applied is that the case where the input voltage of a signal is decreased is considered. More specifically, when the input voltage is decreased from 0 V, if the substrate voltage is 0 V, the p-n junction is forward-biased, thus injecting minority carriers. The minority carriers, which destroy data stored in the memory, are not very preferable. Then, it has been conventionally permitted that the signal input voltage is decreased.
The embodiment in the present invention, which does not have such margin, requires an improvement as explained with reference to
(1) If a minus voltage is externally applied to the input or output due to ringing, etc., electrons which are minority carriers are injected into the substrate. The electrons diffuse through the substrate and a part thereof reaches the charge storage portion of the memory cell, thereby deteriorating the refresh characteristic. This injection of minority carriers into the substrate is intended.
(2) By applying a minus voltage to the substrate, the junction capacitance between the n diffused layer and the p substrate is reduced thereby to reduce the load capacitance. This intends the high speed operation and low power consumption of the circuit.
(3) By applying a minus voltage to the substrate, the depiction layer below the channel is extended so that the potential at the channel becomes hard to be dependent on the substrate voltage. Thus, the gate threshold voltage is not almost affected by fluctuation of the substrate voltage. In other words, the body effect coefficient of the gate threshold voltage becomes small. This is convenient in the operation of a partial circuit of the memory.
Among these reasons, the reason of (3) has become weak with tendency of the twin-well structure of CMOS-LSI. Therefore, it is important to solve the problems of (1) and (2). A substrate structure which permits a plurality of substrate voltages to be applied in CMOS-LSI is disclosed in JP-A-62-119958 (corresponding to U.S. patent application Ser. No. 87256). By combining this structure and the low voltage LSI in accordance with the present invention, a low voltage LSI with the performances of high noise resistance, high operation speed and low power consumption can be constructed. An example of such a low voltage LSI using the substrate structure shown in
In
(1) By biasing the P-well of the memory cell array at a minus voltage, the data line capacitance can be reduced to improve the S/N.
(2) The N2 well covering the memory cell serves as a barrier for the minority carriers diffusing through the substrate. This restrains collection of noise charges into the storage capacitor, thus improving the noise resistance.
As mentioned above, by using the substrate structure as shown in
In the normal operation, i.e. when PD is at a low voltage ("1") level, the ring oscillator and the charge pumping circuit do not operate. Also, MOS-FET T44 is made conductive and anode N1 is at a high voltage level ("1") so that MOS-FET T42 is made conductive and VBP1 becomes ground potential. On the other hand, in the data retention operation, i.e. when PD is a high voltage ("1") level, MOS-FET T43 is made conductive and the node N1 becomes the same level as VBP1 so that MOS-FET T42 is cut off. Also, the ring oscillator 62 and the charge pumping circuit 63 operate, thus producing a minus VBP1. Incidentally, the substrate bias voltage is always applied to the memory cell array. As mentioned above, by controlling the substrate bias voltage in operating the memory by a low voltage power supply of 1 V or less, the high speed operation for the normal operation and low power consumption for the data retention can be realized. It should be noted that the idea mentioned above can be adapted to a circuit for generating VBN1.
Explanation will be given for a concrete construction of the low voltage operation dynamic memory using the substrate structure as previously mentioned.
(1) a ½ VCL generating circuit
(2) a word line driving circuit and
(3) a common source driving source
In
By means of the substrate structure, device constant and circuit arrangement in the embodiments as explained above, a dynamic memory assuring its operation at a minimum power supply voltage of 1 V can be realized. Further, in place of the circuit arrangement of the I/O lines and the Y-gates as shown in
Several arrangement examples of the main LSI circuit block which can operate a low internal power supply voltage of 1.5 V or less have been explained in relation to memories. However, in order to realize the LSI chip as shown in
(1) a reference voltage generating circuit,
(2) a voltage converting (dropping) circuit,
(3) an input circuit and
(4) an output circuit.
As indicated in the table of
(1) As mentioned previously, on the same chip integrated in addition to the devices operated by the internal power supply voltage are the devices, with a relatively thick gate oxide film, operated by the external power supply voltage.
(2) The circuit block is constituted by only the devices operated by the internal power supply voltage. In this case, circuit contrivance is made so that the external power supply voltage is not directly applied to the devices.
The technique of (1) is disclosed in U.S. Pat. No. 4,820,85. This technique, however, complicates the fabricating process of LSI and so increases the production cost. Also this technique includes manly steps in forming gate oxide films which is most important in fabricating the devices so that it provides high possibility of introducing impurities and defects, thus reducing the reliability of the devices. Explanation will be given for the circuit block at a high power supply voltage realized by the technique of (2). Although in the following example, complementary MOS-FETs are used, the other devices e.g. bipolar transistors or junction transistors, combination thereof with MOS-FET and devices made of semiconductor material (e.g. GaAs) other than silicon may be used.
When an inverter array is constructed using the above inverter (FIG. 20C), the voltage at each node is as shown in FIG. 20C. In
In accordance with the above arrangement, for example, when Vn=Vp=½ Vcc, in any transistor, the maximum voltage applied to the gate oxide film is limited to ½ Vcc and the maximum voltage applied between the drain and the source thereof i limited to ½ Vcc+VTN or to ½ Vcc+|VTP|. Actually, in order to assure sufficient operation margin of the inverter, Vn and Vcc-Vp are desired to be constant at a low power supply voltage. Further, in order that a large voltage is not applied between the drain and source, the channel conductance of T102 and T103 is desired to be larger than that of T100 an T101, respectively. In this way, realized is a circuit which can operate, without deteriorating the device characteristic, at a power supply voltage range reaching about twice as large as the maximum voltage applied to the devices.
Further, in the example shown in
Meanwhile, an aging test is performed for the normal LSI circuit to assure the reliability thereof. Namely, after the final fabrication step, a higher voltage than the voltage used for the normal operation is intentionally applied to each transistor in the circuit hereby to early find out the transistor(s) which is likely to be damaged by nature due to failure of the gate oxide film, etc.
Japanese Patent Application No. 63-125742 discloses a constant voltage generating circuit using a difference between MOS-FETs in their threshold voltage.
Meanwhile, in the case where the differential amplifier circuit of
The operation will be explained with reference to an operation timing chart shown in FIG. 27B. In the following explanation, it is assumed that the internal power supply voltage VCL during normal operation is 1.5 V (VL=0.75 V). As seen from
Meanwhile, in the case where a system is to be constructed using the LSI chip in accordance with the present invention as well as the other LSI's and semiconductor devices, the input/output levels of the signals to be communicated among these components are required to be aligned with each other. The standard input/output level in the LSI operating at a single power supply (generally 5 V) includes the following two items:
(a) a TTL level, and
(b) a CMOS level.
In the case of using the TTL level, the value of a high voltage ("1") output (VOH) is required to be 2.4 V or more. Therefore, if the system is to be operated at the power supply voltage of 2.4 V or less, it is necessary to use the CMOS level or newly set a standard of the input/output level. If a system is to be constructed by the conventional LSI and TTL logic circuits, it is important to assure compatibility with the above input/output level. To assure the compatibility makes it unnecessary to provide level converter circuits thereby to reduce the number of components, thus leading to reduction of the production cost. Further, this improves the circuit performance such as noise resistance, operation speed, etc. and provides the most excellent performance of the system. Then, in the following description, explanation will be given for an embodiment of the present invention having an input/output circuit arrangement which can assure compatibility with the conventional input/output level. In accordance with the present invention, the following three product specifications can be realized using a single chip without changing the circuit design.
(1) In the normal operation (e.g. the power supply voltage Vcc of 4.5 V-5.5 V or 3-3.6 V), and input/output is made at the TTL level. The reduction of Vcc (e.g. 1.0-2.5 V) is detected as required in the chip to carry out the data retention (battery back-up).
(2) The power supply voltage Vcc e.g. 1.0-5.5 V is used and an input/output is made at the CMOS level. The reduction of Vcc (e.g. 1.0-5.5 V) is detected as required in the chip or an external control signal, etc. is used to carry out the data retention (battery back-up).
(3) The power supply voltage Vcc of e.g. 1.0-5.5 V is used and the chip changes the input/output level in accordance with the value of the power supply voltage. For example, when Vcc is 2.5-5.5 V, the input/output is made at the TTL level and when Vcc is 1.0-2.5 V, the input/output is made at the CMOS level.
As a technique of making these selections in an actual LSI, there is a "master slice" using wirings of aluminum, etc. In this technique, in forming wiring layers of aluminum, etc. two kinds of masks for duplicating a wiring pattern are prepared in accordance with the above switches and these masks are adopted in accordance with the product to be made. Further, with two kinds of bonding pads in accordance with the input/output levels provided on the LSI chip, the product to be made may be bonded to one of these bonding pads. Otherwise, with one bonding pad provide on the chip, the connection of the product with the input/output buffer may be changed by means of the master slice using the wiring of aluminum, etc.
By means of the arrangement mentioned above, the three product specifications can be realized on one chip. This is convenient from the point of view of the production cost and also using convenience for a user. Incidentally, although the above arrangements are directed to a so-called I/O common system in which an input and an output are made at the same terminal, the present invention may be applied to the case of only the input or output of the input/output level. In the following description, a concrete arrangement of each of the output buffer, the input buffer, and an input protection circuit will be explained. Although in the embodiments mentioned below, the circuit is constructed by MOS-FETs having a thin gate oxide film (e.g. 6.5 nm) to be used in internal circuit, the present invention may be applied to the case where the MOS-FETs having two kinds of gate oxide films in accordance with the operating voltage are provided in a single chip.
In constructing the output buffer, it is necessary to convert a signal amplitude from an internal low signal amplitude (e.g. 1.5 V) to an external high signal amplitude (e.g. 2.4 V at the TTL level and 5 V at the CMOS level when Vcc is 5 V). First, a circuit arrangement providing for an output signal at the CMOS level will be explained.
The operation of the circuit of
Generally, in constructing a system, the outputs of a plurality of LSIs are connected with a data bus and only the outputs of the selected LSIs are adapted to drive the data bus. In order to carry out such a control, the output impedance of the non-selected are desired to be infinite. The conventional LSI was given by a three-output (tri-state) characteristic of driving the output level into a high voltage, a low voltage or not driving it into either voltage (the output impedance is infinite). In order to provide such a characteristic, it is necessary to perform the control of driving the output (low impedance) or not driving it (infinite impedance). The signal for this control is provided by either one of an output enable (OE) signal, a chip select (CS) signal, etc. which are externally inputted. In the output circuit, the tri-state characteristic was realized in the manner of taking a logic between that signal and an output data and driving the transistors at a final stage by the resultant signal. In the case where the same output circuit is to be constructed in accordance with the present invention, there may be proposed an arrangement in which a logic circuit is operated by a low power supply voltage and the circuit does not include the logic circuit. However, in this case, the following inconveniences will occur. The number of the stages of the amplitude converting circuits and the inverters placed between the logic circuit and the output is increased, thus for example increasing the delay time from the OE signal to the output, and generating a difference between the timing of driving the transistor on high voltage side and the transistor on the low voltage side to cause a large current to transiently flow. On the other hand, if the logic circuit can be constructed by an external power supply voltage, freedom degree of design is increased, which is preferable from the viewpoint of circuit performance. One embodiment of constructing the logic circuit by the external power supply voltage will be explained below. This logic circuit can be efficiently used as means of generating a control signal for several kinds of circuits operated by the external power supply voltage as well as the output buffer.
An exemplary input circuit for the CMOS level will be explained with reference to FIG. 33. In
Thus, examples of the output circuit and input circuit for CMOS level have been explained.
Meanwhile, if the value of the bias voltage Vn1 is suitably varied in accordance with the power supply voltage in these circuits, input/output at the TTL level can be made for a high power supply voltage and input/output at the CMOS level can be made for a low power supply voltage.
First, the operation of the output buffer circuit OB5 will be explained. The voltage at a node N48 is 0 V when a low voltage ("0") is outputted and Vcc when a high voltage ("1") is outputted. Therefore, when the low voltage is output, 0 V is output at a Dout irrespectively of Vcc. On the other hand, when the high voltage is outputted, the voltage level at Dout depends on Vcc as seen from FIG. 34B. Namely, when Vcc≧3 V, it is Vn1-VT1 (TON2) and when Vcc<3 V, it is Vcc. Thus, when Vcc>3 V, the output voltage amplitude satisfying the output characteristic at the TTL level can be obtained. Incidentally, by limiting the output voltage to 2.5 V or less, the power supply current in charging/discharging large load capacitance can be minimized.
The operation of the input circuit IB5 will be explained. The power supply voltage for the CMOS inverter constituted by TIN1 and TIP1 is supplied from the source terminal of TIN2. The value thereof is 2.5 V when the power supply voltage Vcc≧3 V and it is 0 V when Vcc<3 V. On the other hand, an input voltage for the inverter is limited to 2.5 V or less when Vcc≧3 V and the voltage input to Din is applied to the inverter as it is when Vcc<3 V. By means of the circuit arrangement mentioned above, even when the power supply voltage Vcc is greatly changed in a range of e.g. 1 V to 5 V, the power supply voltage for the inverter and the input signal have a substantially equal amplitude. If the channel conductances of the transistors constituting the inverter are set at a substantially equal value, the logic threshold voltage of the inverter is ½ of the power supply voltage therefor. Therefore, the logic threshold voltage when Vcc≧3 V is about 1.25 V and it is Vcc/2 when Vcc<3 V Thus, with the boundary of a certain voltage (3 V in this example), there can be provided an input buffer which operates at the TTL level for Vcc of the certain voltage or more and operates at the CMOS level for Vcc lower than the voltage.
In accordance with the present invention, LSI having a wide range of operation power supply voltage can operate an optimum input/output level for the power supply voltage used, thus realizing the maximum noise margin by minimum power consumption. Further, in the output buffer OB5, the three transistors TON0, TON1 and TON2 have a common substrate (back-gate). Thus, when a high voltage surge is applied to the output terminal, the charges can be swiftly discharged through a large current. This is, like the operation of a clamping MOS-FET in the input protection device described later, because when the substrate potential is increased due to breakdown, a parasitic bipolar transistor between the substrate potential and the ground potential is likely to be turned on. As a result, even when scaled-down devices are used, the static breakdown voltage can be enhanced. Moreover, although in the above embodiment, the substrate voltage VBP1 of the N channel MOS-FETs is generally set at a minus value (e.g. -3 V) so that the input voltage becomes minus (undershoot), the PN junctions are not forward biased, it may be 0 V as long as the forward current is permitted to flow. Furthermore, the N channel MOS-FETs may be formed in P substrate or may be formed in a P well electrically isolated from the P substrate as shown in
In the embodiment mentioned above, it is necessary to generate a bias voltage Vn higher than the power supply voltage.
The operation of the input buffer circuit IB5 will be explained. The power supply voltage for the CMOS inverter constituted by TIN1 and TIP1 is supplied from the source terminal of TIN2. The value thereof is 2.5 V when the power supply voltage Vcc≧3 V and it is 0 V when Vcc<3 V. On the other hand, an input voltage for the inverter is limited to 2.5 V or less when Vcc≧3 V and the voltage input to Din is applied to the inverter as it is when Vcc<3 V. By means of the circuit arrangement mentioned above, even when the power supply voltage Vcc is greatly changed in a range of e.g. 1 V to 5 V, the power supply voltage for the inverter and the input signal have a substantially equal amplitude. If the channel conductances of the transistors constituting the inverter are set at a substantially equal value, the logic threshold voltage of the inverter is ½ of the power supply voltage therefor. Therefore, the logic threshold voltage when Vcc≧3 V is about 1.25 V and it is Vcc/2 when Vcc<3 V Thus, with the boundary of a certain voltage (3 V in this example), there can be provided an input buffer which operates at the TTL level for Vcc of the certain voltage or more and operates at the CMOS level for Vcc lower than that voltage.
In accordance with the present invention, LSI having a wide range of operating power supply voltage can operate an optimum input/output level for the power supply voltage used, thus realizing the maximum noise margin by minimum power consumption. Further, in the output buffer OB5, the three transistors TON0, TON1 and TON2 have a common substrate (back-gate). Thus, when a high voltage surge is applied to the output terminal, the charges can be swiftly discharged through a large current. This is, like the operation of a clamping MOS-FET in the input protection device described later, because when the substrate potential is increased due to breakdown, a parasitic bipolar transistor between the substrate potential and the ground potential is likely to be turned on. As a result, even when scaled-down devices are used, the static breakdown voltage can be enhanced. Moreover, although in the above embodiment, the substrate voltage VBP1 of the N channel MOS-FETs is generally set at a minus value (e.g. -3 V) so that the input voltage becomes minus (undershoot), the PN junctions are not forward biased, it may be 0 V as long as the forward current is permited to flow. Furthermore, the N channel MOS-FETs may be formed in a P substrate or may be formed in a P well electrically isolated from the P substrate as shown in
In the embodiment mentioned above, it is necessary to generate a bias voltage Vn higher than the power supply voltage.
The operation of this circuit arrangement will be explained in two cases.
The plan structure of the gate clamping device 121 is shown in FIG. 36B and the sectional structure thereof along line A--A' is shown in FIG. 36C. In
The operation of the input protection device will be explained. When the voltage applied to the node N60 exceeds the breakdown voltage of the PN junction formed between the impurity diffused layer 136 and the substrate, the current due to the breakdown enhances the potential at the substrate (P type), thus turning on the above parasitic bipolar transistors. Thus, a large collector current flows between the diffused layers 136 and 135 (or 138) so as to extract charges at the node N60, thus clamping its potential. Since Q1b and Q1c are connected in series, their collector current is smaller than Q1a and so they are first effectively broken down. Therefore, the MOS-FET's turn on the parasitic transistor and thereafter the parasitic bipolar transistor Q1a passes the large current. In this way, if an impurity diffused layer is provided, in the neighborhood of the node N60, independently from the impurity diffused layers of the MOS-FETs and is grounded, the effective length between the collector and emitter of the parasitic bipolar transistor can be shortened so as to cause a large collector current to flow when the parasitic bipolar transistor operates. Also, the above arrangement of placing a grounded impurity diffused layer in the neighborhood of the terminal to be clamped may be used in an output protection device as well as in the input protection device. Further, although in the above embodiment, the gate clamping device is formed in the P substrate, it may be formed in the P well electrically separated from the substrate in such a structure as shown in FIG. 14. Then, the resistance of the base and the P well is increased and the parasitic transistor is further likely to be turned on so that the clamping effect can be further improved. Moreover, the bias voltage of the P substrate or the P well is generally set a minus value (e.g. -3 V), it may be 0 V as long as a forward current is permitted to flow for input undershoot. Furthermore, although a p-type substrate is employed in the above embodiment, an n-type substrate may be employed as long as the clamping device is formed within the P well.
Although the details of the present invention have been explained in relation to several embodiments, the application field of the present invention should not be limited to these embodiments. For example, although the present invention has been explained mainly in relation to a memory circuit, as mentioned in the beginning of the specification, it can be also applied to a memory LSI, a logic LSI, a composite LSI by combination thereof, or the other any LSI. Further, as regards the kind of the devices (elements) to be used, the present invention can be applied to an LSI including both P and N channel MOS-FETs, an LSI including bipolar transistors, an LSI including junction FETs, a Bi-CMOS type LSI by combination of CMOS transistors and bipolar transistors, and further an LSI in which devices are formed in a substrate of the material other than Si, e.g. GaAs.
In accordance with the embodiments of the present invention as explained above, it is possible to provide an LSI which can use the characteristic of the devices fabricated by the up-to-date scaled-down processing technique, operate with low power consumption and a high speed and also perform normal operation and data retention using a battery through exchange of the operation state.
Explanation will be given for embodiments of the dynamic random access memory (DRAM) in accordance with the present invention which is suited for low voltage operation. In accordance with the embodiments mentioned below, disclosed is the DRAM which can sufficiently assure storage charges of memory cells even when an internal power supply voltage is lowered. The point of these embodiments resides in the following three items:
(1) using a half precharge system,
(2) setting the threshold voltage of the MOS-FETs constituting a CMOS sense amplifier at a value that is about one-third of the potential difference between data lines D and {overscore (D)} (hereinafter referred to as data line voltage amplitude), and
(3) boosting the potential of a memory cell signal at a higher potential using a terminal of a capacitor constituting the memory cell which is not connected with the MOS-FET for a transfer gate.
Setting the data line voltage amplitude in amplifying the memory cell signal at a small value permits the internal power supply voltage to be lowered and also the data line charging/discharging current to be greatly reduced, thus reducing power consumption. Also, though reducing the data line voltage amplitude decreases the voltage to be written from the data line into the memory cell, the memory cell signal can be increased by boosting that voltage from one terminal of the capacitor constituting the memory cell. Thus, the characteristics of data retention time, α ray-resistance soft error and S/N can be improved.
In
The read operation of the circuit shown in
While the data line precharge signal {overscore (φP+L )} is at a high potential level (4 V), the data lines D0, {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential (1 V). Then, the sense amplifier driving signals φSP, {overscore (φSN+L )} are 1 V and the sense amplifier is in an OFF state. After {overscore (φP+L )} has been changed to a low potential level (0 V), one of the word lines is selected. Now it is assumed that the word line W0 has been selected. When W0 is changed from a low potential level (0 V) to a high potential level (4 V), a memory cell signal appears at each data line. Now it is assumed that the memory cells connected with the data lines D0, Dn have stored a signal at a high potential level. Therefore, the potential at the data line Do (Dn) becomes slightly higher than that at the data line {overscore (D0+L )} ({overscore (Dn)}). Next, when φsp is changed from 1 V to 2 V, and φSN is changed from 1 V to 0 V, the sense amplifiers SAo to SAn operate to amplify the memory signals. Thus, the data line D0 becomes 2 V and the data line {overscore (D0+L )} becomes 0 V. Thereafter, a pair of the data lines is selected by the Y decoder YD. It is now assumed that D0 and {overscore (D0+L )} are selected. Thus, the potential at the data line selection line Y0 becomes high (4 V) so that the memory cell signal is read out to the data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide the Dout.
The rewrite operation of a signal into a memory cell will be explained. After the sense amplifier has been operated, the potential at a storage terminal 10, which is one terminal of the capacitor constituting a memory cell, is 2 V like D0 (case where the potential at the terminal is at a high potential). Then, the potential at the plate P0 is changed from 4 V to 0 V. However, the potential on the word line W0 is 4 V so that the potential on the data line and at the storage terminal are held by the sense amplifier. Thereafter, the potential on the word line W0 is lowered from 4 V to 2 V. Then, assuming that the threshold voltage of a transistor constituting the memory cell is 1 V, both potentials of at the storage terminal and on the data line D0 are 2 V so that the transistor T0 is in an OFF state. Therefore, when the potential on the plate P0 is changed from 0 V to 4 V, the potential at the storage terminal is enhanced from 2 V to about 6 V. Thus, 6 V is written in the memory cell.
On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory will be explained with reference to the waveform in the case where the terminal 10 in
Thereafter, the potential on the word line W0 becomes 0 V to complete the rewrite operation. Subsequently, φSP and {overscore (φSN+L )} become 1 V. Further, φP becomes 4 V to precharge the data line to 1 V.
The write operation in the circuit shown in
On the other hand, the operation of writing a high potential signal in the memory in which a low potential signal has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D0 and {overscore (D0+L )} are 0 V and 2 V, respectively. The potentials on I/O and {overscore (I/O)} are 2 V and 0 V, respectively, in accordance with Din. Thereafter, the potential on Y0 is enhanced to 4 V so that the potentials on D0 and {overscore (D0+L )} are 2 V and 0 V. Accordingly, the high potential of 2 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is rewritten from the low potential to high potential).
The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted and stored at about 6 V whereas the low potential is stored at 0 V.
As explained above, in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, by decreasing the voltage amplitude of the data lines, which affects the power consumption of the memory, and also increasing the voltage amplitude of the plates, which is relative to memory cell signals, reduced power consumption and increased S/N of the memory can be simultaneously realized. In this embodiment, the voltage amplitude of the plate is set to be larger than that of the data lines. In this way, most of the memory cells signals can be stored through the plates so that the voltage amplitude of the data lines can be decreased to the neighborhood of the operation limit of the sense amplifiers. Thus, the power consumption can be remarkably reduced while assuring a sufficient signal voltage for the memory cells. In this embodiment, the potential on the data lines during its precharge is set at an intermediate value between the high and low potentials of the voltage amplitude of the data lines. This permits the power consumption to be further reduced.
Further, although the amplitude of the data line voltage can be decreased to the neighborhood of the threshold voltage of the MOS-FETs constituting the sense amplifier, it is desired to be slightly larger than a sum of the absolute values of the respective threshold values of N channel MOS-FETs and P channel MOS-FETs which constitute the sense amplifier. This will be explained with reference to FIG. 37D.
With respect to power consumption, the charging/discharging current in the case of the data line voltage amplitude of 2 V can be decreased to {fraction (1/2.5)} of the case of 5 V assuming that the respective threshold voltage of the N channel MOS-FETs and the P channel MOS-FETs are 0.7 V and -0.7 V. Incidentally, the power consumption may be increased due to driving the plates. But, in an array of 256 words lines * 1024 data pair lines, the capacitance charged at one time is 15 to 30 pF for plates, which is negligibly small whereas it is 200 to 300 pF for the data lines.
In accordance with this embodiment, the voltage amplitude of the data lines can be decreased while assuring a sufficient voltage to be written into the memory cells so that low power consumption and high S/N in the memory can be simultaneously realized. Additionally, if the plate potential is set at an intermediate value between two potentials of the memory cells during the stand-by of the memory as shown in
Further, in accordance with this embodiment, the signal stored in the memory cell is larger on the high potential side than on the low potential side. Since the memory cell signal on the high potential side is required to be large in order to increase the margin for data retention time and ray soft error, in accordance with this embodiment, a memory with large margin for them can be provided.
Another embodiment of the present invention will be explained with reference to
Another embodiment of the present invention will be explained with reference to
The read operation of the circuit shown in
While the data line precharge signal {overscore (φP+L )} (not shown in
The rewrite operation of a signal into a memory cell will be explained. After the sense amplifier has been operated, D0 is at a high potential of 5 V and {overscore (D0+L )} is a low potential of 3 V. Then, the storage terminal 10 of the memory cell is at the high-potential of 5 V like D0 (case where the potential at the terminal is at a high potential in FIG. 40B). Then, the potential at the plate P0' is changed from 6 V to 3 V. However, the potential on the word line W0 is 4 V so that the potential on the data line and at the storage terminal are held by the sense amplifier and not varied. Thereafter, the potential on the word line W0 is lowered from 7 V to 5 V. Then, assuming that the threshold voltage of a transistor constituting the memory cell is 1 V, both potentials of at the storage terminal 10 and on the data line D0 are 5 V so that the transistor T0 is in an OFF state. Therefore, when the potential on the plate P0' is changed from 3 V to 6 V, the potential at the storage terminal is enhanced from 5 V to about 8 V. Thus, the high potential about 8 V is written in the memory cell.
On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory will be explained with reference to the waveform in the case where the terminal 10 in
Meanwhile, in this embodiment, the plate of the memory cell connected with a non-selected word line is varied in its potential. Then, the behavior of a storage terminal 11 of the memory cells connected with a non-selected word line W1 will be explained. The operation in the case where a high potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory; the plate P0' is at 6 V and the storage terminal 11 is at 8 V. After the sense amplifier has amplified the memory signal, P0 becomes 3 V and then the storage terminal becomes 5 V. Then, the word line W1 becomes 0 V and the data line {overscore (O0+L )} becomes 3 V or 5 V so that a transistor T1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P0' becomes 0 V and the storage terminal 11 returns to 8 V.
The operation in the case where a low potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P0' is at 6 V and the storage terminal 11 is at 3 V. After the sense amplifier has amplified the memory signal, P0' becomes 3 and then the storage terminal 11 becomes 0 V. Then, the word line W1 becomes 0 V and the data line {overscore (O0+L )} becomes 3 V or 5 V so that a transistor T1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P0 becomes 6 V and the storage terminal 11 returns to 3 V.
Thereafter, the potential on the word line W0 becomes 0 V to complete the rewrite operation. Subsequently, φSP and {overscore (φSN+L )} become 4 V. {overscore (φP+L )} becomes the high potential to precharge the data line to 4 V.
In this way, if the plate voltage amplitude (6-3=3 V) is equal to the low potential level of the data line, the lowest potential of the storage terminal 11 is 0 V. Therefore, the transistor T1 is never turned on.
The write operation in the circuit shown in
On the other hand, the operation of writing a high potential signal in the memory in which a low potential has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D0 and {overscore (D0+L )} are 3 V and 5 V, respectively. The potentials on I/O and {overscore (I/O)} are 5 V and 3 V, respectively, in accordance with Din. Thereafter, the potential on Y0 is enhanced to 6 V so that the potentials on D0 and {overscore (D0+L )} are 5 V and 3 V. Accordingly, the high potential of 5 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is rewritten from the low potential to high potential.
The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted and stored at about 8 V whereas the low potential is stored at 3 V.
As mentioned above, in accordance with this embodiment, the data line voltage amplitude during the operation of the sense amplifier is decreased so that the charging/discharging current of the data line can be decreased, thus reducing the power consumption. Further, a sufficiently large voltage is written into the memory cell through the plate so that the characteristics of data retention time and α ray soft error resistance can be improved. Moreover, one plate is commonly used for two word lines so that space is not required between the plates, thus reducing the memory chip size. Incidentally, in the case where one plate is commonly used for plural word lines, if the low potential of the data line is set at a higher level than the low potential of the word line by a plate voltage amplitude or more, the signal in the memory cell connected with the non-selected word line is never destroyed.
A still another embodiment of the present invention will be explained with reference to
In this embodiment, the voltage amplitudes of both data line and plate are set at the same value. The other operation and circuit arrangement are the same as the embodiment shown in FIG. 40A.
Meanwhile, it should be noted that in the embodiments mentioned above, the plate is made of a poly-silicon layer. The poly-silicon layer has a larger resistance than a metallic layer of e.g. aluminium so that the rising time and falling time in pulse-driving the plate are very long. This increases the operation cycle time of a memory and hence the use efficiency. In order to obviate such a disadvantage, it is proposed to shunt the plate by an aluminium (Al) wiring. This will be explained with reference to
Two data line arrangements are proposed for the memory cell arrangement of FIG. 45A. One is an open-type data line (bit line) arrangement and the other is a two-cell/bit type data line arrangement.
A further embodiment of the present invention will be explained with reference to FIG. 46.
The rewrite operation is performed as follows. After the sense amplifier has been operated. D0 is at a high potential of 4 V and {overscore (D0+L )} is a low potential of 2 V. Then, the storage terminal 10 of the memory cell is at the high potential of 4 V like D0 (case where the terminal 10 is at a high potential in FIG. 46). Then, the potential at the plate P0 is changed from 5 V to 4 V. Then, assuming that the threshold voltage of a transistor constituting the memory cell is 1 V, both potentials of at the storage terminal 10 and on the data line D0 are 4 V so that the transistor T0 is in an OFF state. Therefore, when the potential on the plate P0' is changed from 2 V to 4 V, the potential at the storage terminal is enhanced from 4 V to about 6 V.
On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory is as follows. After the sense amplifier has been operated, both potentials on the data line D0 and at the storage terminal 10 are 2 V. Therefore, even if the potential on the word line W0 is subsequently lowered to 5 V, the transistor T0 constituting the memory cell is an ON state. Thus, even if the potential at the plate P0' is subsequently changed from 2 V to 4 V, the potential at the storage terminal 10 is held 2 V. Thereafter, after the word line W0 has become 0 V, the plate P' is changed from 4 V to 2 V. Thus, the potential at the storage terminal 10 is changed from about 6 V to 4 V when a high potential has been stored at the terminal, whereas it is changed from 2 V to 0 V when a low potential has been stored there. Accordingly, stored in the memory cell is 4 V on the high potential side and is 0 V on the low potential side.
Next, the behavior of a storage terminal 11 of the memory cells connected with a non-selected word line W1 will be explained. The operation in the case where a high potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P0 is at 2 V and the storage terminal 11 is at 4 V. After the sense amplifier has amplified the memory signal, P0' becomes 3 V and then the storage terminal becomes about 6 V. Then, the word line W1 becomes 0 V and the data line becomes 3 V or more so that a transistor T1 is never in the ON state and so the-signal in the memory cell is not destroyed. Thereafter, the plate P0' becomes 2 V and the storage terminal 11 returns to 4 V.
The operation in the case where a low potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P0' is at 2 V and the storage terminal 11 is at 0 V. After the sense amplifier has amplified the memory signal, P0' becomes 4 V and then the storage terminal becomes about 2 V. Then, the word line W1 becomes 2 V and the data line becomes 2 V or more so that a transistor T1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P0' becomes 2 V and the storage terminal 11 returns to 0 V.
Also in accordance with this embodiment, the voltage amplitude of the data lines can be decreased so that reduced power consumption of a memory chip can be realized. Further, in this embodiment, the memory cell signal on the low potential side can be made larger than that on the high potential side.
A further embodiment of the present invention will be explained.
A further embodiment of the present invention will be explained with reference to FIG. 48. In this embodiment, the voltage of the data lines is binary. The other operation and circuit arrangement are the same as those of FIG. 37A. In operation, while a data line precharge signal {overscore (φP+L )} is 4 V, the data lines are precharged to 1 V. After p has become 0 V, the word line W0 is raised to 2 V+Vt (Vt is the threshold voltage of MOS-FET). Thus, a memory cell signal is read out to the data lines. Next, the sense amplifier driving signal φsp varies from 1 V to 2 V and the same amplifier signal {overscore (φSN+L )} varies from 1 V to 0 V, thus amplifying the memory signal read out. Now it is assumed that the signal at a high potential has been stored in the memory cells connected with the word line W0. Then, the data line D0 (Dn) becomes 2 V and the data line D0 (Dn) becomes 0 V. Also, the word line W0 is 2 V+Vt, the data line D0 is 2 V and the storage terminal 10 so that the transistor T0 constituting the memory cell connected with the data line D0 is turned off. Next, when the potential at the plate P0 is lowered from 4 V to 0 V, the potential at the terminal 10 is slightly lowered, thus turning on the transistor T0. The potential 2 V at the terminal 10 is held in the sense amplifier. Thereafter, when the potential at the plate P0 is boosted from 0 V to 4 V, the transistor T0 is turned off, thus raising the potential at the terminal to about 6 V.
On the other hand, the operation in the case where a signal at a low potential has been stored in the memory cells is as follows (see the waveform in the case where the terminal 10 is at a low potential in FIG. 48). After the memory cell signal has been amplified by the sense amplifier, the data line D0 is at 0 V, the storage terminal 10 is at 0 V and the word line W0 is at 2 V+Vt so that the transistor T0 constituting the memory cell is turned on. Therefore, even when the potential at the plate P0 varies from 4 V to 0 V or from 0 to 4 V, the potential at the terminal 10 is held 0 V.
After the signal has been stored in the memory cell in the above manner, the word line becomes 0 V. Subsequently, φp becomes 4 V and φsp, and {overscore (φSN+L )} become 1 V, thus precharging the data lines to 1 V.
As mentioned above, in accordance with this embodiment, the same operation as the embodiment of
Meanwhile, in the memory in accordance with the present invention, as understood from the embodiment shown in
The embodiment shown in
As understood from the above description, in accordance with the circuit shown in
In this way, three value levels of the word line voltage can be provided by means of the circuit as shown in FIG. 51A.
An embodiment of another read operation for the circuit shown in
While the data precharge signal {overscore (φD+L )} is 4 V, the data lines D0, {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential level of 1 V. Then, the sense amplifier driving signals φsp and {overscore (φSN+L )}, are 1 V and the sense amplifiers SA0 to SAn are in the OFF state. It is assumed that after {overscore (φp+L )} has become 0 V, a plate (wiring) P0 is selected from a plural plate wirings. When P0 varies from 4 V to 0 V, a memory cell signal appears on each data line. Now it is assumed that a signal at a low potential of 0 V has been stored in the memory cell connected with the data line D0. When P0 varies from 4 V to 0 V, 0 V in the memory cell is reduced toward -4 V. Then, since the word line W0 is at 0 V, if the reduction amount exceeds the threshold voltage of the MOS-FET T0, the storage terminal (node) 10 of the memory cell is communicated with the data line D0. Thus, a current flows from the data line D0 to the memory cell so that the memory cell signal appears on the data line D0. Then, a dummy word line {overscore (WD0+L )} varies from 4 V to 0 V. Thus, a reference signal appears on the data line {overscore (D0+L )}. Incidentally, in the case where a signal at a high potential of 6 V has been stored at the storage terminal 10, the potential at the terminal is 2 V in accordance with the voltage change of P0. In this case, the potential on the data line D0 does not vary since the MOS-FET T0 constituting the memory cell in the OFF state.
After the memory cell signal and the reference signal have appeared on the data lines D0 (Dn) and {overscore (D0+L )} ({overscore (Dn)}), respectively, φSP varies from 1 V to 2 V and {overscore (φSN+L )} varies from 1 V to 0 V. Thus, sense amplifiers SA0 to SAn operate to amplify the corresponding memory cell signals. Therefore, the data line D0 becomes 0 V and the data line {overscore (D0+L )} becomes 2 V. Thereafter, when the word line W0 varies from 0 V to 4 V, 0 V (2 V in the case of reading the high potential) is stored in the memory cell. Next, a pair of data lines are selected by the Y decoder YD. Now it is assumed that the data lines D0, {overscore (D0+L )} are selected. Thus, the potential on the data line selection line Y0 becomes 4 V and the memory cell signal is read out to data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dout. Next, the word line W0 is lowered from 4 V to 2 V. Thereafter, the plate P0 is boosted from 0 V to 4 V. Then, since the low potential of 0 V has been stored in the memory cell, the transistor T0 constituting the memory cell is in the ON state. Therefore, the voltage of 0 V in the memory does not vary. Incidentally, in the case where the high potential of 2 V has been stored in the memory cell, the transistor T0 is in the OFF state. Therefore, 2 V in the memory cell is boosted to 6 V. Thereafter, the word line W0 becomes 0 V thereby to complete the rewrite operation mentioned above. Also the dummy word line {overscore (WD0+L )} varies from 0 V to 4 V. Thereafter, φSP and {overscore (φSN+L )} become 1 V and {overscore (φP+L )} becomes 4 V thereby to precharge the data lines to 1 V.
The write operation will be explained with reference to the waveform chart of FIG. 52B. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal becomes 4 V, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become 2 V and 0 V, respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed that D0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y0 becomes 4 V so that D0 and {overscore (D0+L )} become 2 V and 0 V, respectively. Accordingly, a high potential of 2 V is written at the storage terminal 10 of the memory cell (see the waveform in the case where the terminal 10 is at a low potential). On the other hand, the operation of writing a high potential signal in the memory in which a low potential signal has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D0 and {overscore (D0+L )} are 2 V and 0 V, respectively. The potentials on I/O and {overscore (I/O)} are 0 V and 2 V, respectively, in accordance with Din. Thereafter, the potential on Y0 is enhanced to 4 V so that the potentials on D0 and {overscore (D0+L )} are 0 V and 2 V. Accordingly, the low potential of 0 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is at a high potential).
The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted and stored at about 6 V whereas the low potential is stored at 0 V.
As explained above, in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, the voltage amplitude of the data lines (voltage amplitude when the sense amplifiers operate), which affects the power consumption of the memory, can be decreased, and also the voltage amplitude of the plates, which decides the high potential level of the memory cells relative to the data retention time for the memory cell, is increase. In this embodiment, the voltage amplitude of the plate is set to be larger than the that of the data lines. In this way, the power consumption can be remarkably reduced while assuring a sufficient signal voltage for the memory cells. Therefore, reduced power consumption and high S/N can be simultaneously realized. Further, in this embodiment, the potential on the data lines during its precharge is set at an intermediate value between the high and low potentials of the voltage amplitude of the data lines. This permits the power consumption to be further reduced. Moreover, the voltage amplitude of the data line can be decreased to the neighborhood of a sum of the absolute values of the threshold voltages of the N channel MOS-FET and P channel MOS-FET. Since the threshold voltage is generally 0.5 V to 1 V, the charging/discharging current in the case of the data line voltage amplitude of 2 V can be decreased to {fraction (1/2.5+L )} in the case of that of 5 V. Further, in this embodiment, the memory cell signal is read by reducing the potential on the plate P0 from a high potential of 4 V to a low potential of 0 V. In the case where a signal line is driven using a MOS-FET, the discharging operation is performed at a higher speed than the charging operation. Therefore, the read operation in this embodiment can be performed at a higher speed than the read operation by boosting the word line from a low potential to a high potential.
The operation of the circuit of
In accordance with this embodiment, the word line can be selected by selecting the plate so that a selection circuit for the word line is not required. Also, since the plate and the word line can be substantially, simultaneously selected, the high speed of a memory can be realized.
A further embodiment of the present invention will be explained with reference to
The operation of the memory circuit will be explained with reference to the waveform chart of FIG. 54B. While the data precharge signal {overscore (φp+L )}is 4 V, the data lines D0, {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential level of 1 V. Then, the sense amplifier driving signals φsp and {overscore (φSN+L )} are 1 V and the sense amplifiers SA0 to SAn are in the OFF state. Next, the plate P0 is selected and varies from 4 V to 0 V. Thus, the signal in each of the memory cells connected with the plate P0 is read out on the corresponding data line. Now it is assumed that a high potential of 6 V has been stored at the storage terminal (node) 10 and a low potential of 0 V has been stored at the storage terminal (node) 11. When the plate 0 varies from 4 to 0 V, the potential at the terminal 10 varies from 6 V to 2 V. Then, the data line D0 is 1 V and the word line W0 is 0 V so that a transistor T01 in the OFF state whereby the voltage on the data line D0 is not varied. On the other hand, the potential at the terminal 11 is reduced from 0 V toward -4 V. Then, the data line {overscore (D0+L )} is 1 V and the word line W0 is 0 V so that when the potential at the terminal 11 becomes lower than the threshold voltage Vt of MOS-FET (T02), the transistor T02 is turned ON, whereby a current flows the data line D0 to the terminal 11. Thus, the potential on the data line {overscore (D0+L )} is slightly lowered. Accordingly, the memory cell signal is read out on both data lines D0 and {overscore (D0+L )}.
Thereafter, the sense amplifier driving signal φSP varies from 1 V to 2 V and {overscore (φSN+L )} varies from 1 V to 0 V thereby to operate the sense amplifiers. Thus, the data line D0 becomes 2 V and the data line {overscore (D0+L )} becomes 0 V. Next, when the word line W0 becomes 4 V, 2 V is rewritten at the terminal 10 and 0 V is rewritten at the terminal 11. Thereafter, the data lines D0 and {overscore (D0+L )} are selected by the Y decoder YD and so the data line selection line Y0 becomes 4 V. Thus, the memory cell signal is read out on the data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dout. Next, the word line W0 is lowered from 4 V to 2 V. Then, D0 is 2 V, {overscore (D0+L )} is 0 V, the storage terminal 10 is 2 V and the storage terminal 11 is 0 V so that the transistor T01 is turned OFF and the transistor T02 is turned ON. Next, when the plate P0 is boosted from 0 V to 4 V, the potential at the storage terminal 10 is boosted about 6 V whereas the potential at the storage terminal 11 is held 0 V. Thereafter, the word line becomes 0 V thereby to complete the rewrite operation mentioned above. Accordingly, about 6 V is rewritten at the storage terminal 10 whereas 0 V is rewritten at the storage terminal 11. Thereafter, the data line precharge signal {overscore (φP+L )} is 4 V, and the sense amplifier driving signals φSP and {overscore (φSN+L )} become 1 V thereby to precharge the data lines to 1 V.
The write operation will be explained with reference to the waveform chart of FIG. 54C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal becomes 4 V, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become 0 V and 2 V, respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed that D0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y0 becomes 4 V so that D0 and {overscore (D0+L )} become 0 V and 2 V, respectively. Accordingly, 0 V is written at the storage terminal 10 of the memory cell whereas 2 V is written at the storage terminal 11.
The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the potential at the storage terminal 11 is boosted to 6 V which is stored there whereas the potential of 0 V at the storage terminal 10 is stored as it is.
As understood from the description, also in accordance with this embodiment, the voltage amplitude of the data lines and the voltage to be written into the memory cells can be determined independently from each other. Therefore, the charging/discharging current for the data lines can be decreased and so power consumption of the memory can be reduced. Further, reduction of the voltage to be written into the memory cells due to decreasing of the voltage amplitude of the data lines is compensated for by the write operation from the plates. Therefore, the characteristics of data retention time and α-ray resistance soft error can be improved. Moreover, since the memory cell arrangement of two cells/bit provides memory cell signals twice those in the memory cell arrangement of one cell/bit, high S/N in the memory can be realized. Also, any dummy cell is not required.
A further embodiment of the present invention will be explained with reference to
The read operation of the circuit of
After the memory cell signal and the reference signal have appeared on the date lines D and {overscore (D)}, the sense amplifier driving signal φsp varies from 2 VBE to 3 VBE and the sense amplifier driving signal {overscore (φSN+L )} varies from 2 VBE to VBE. Thus, the sense amplifier(s) operates so that D becomes VBE and {overscore (D)} becomes 3 BVE. Subsequently, when the potential of the word line W becomes 4 V, VBE is rewritten at the storage terminal 10. Thereafter, when a data line selection signal Yr becomes 4, the memory cell signal is read out on the signal read lines O and {overscore (O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dour. Thereafter the potential of the word line W lowers from 4 V to 3 VBE. Then, the potential of the data line D is VBE and the potential at the storage terminal is also VBE so that the transistor T is in the ON state. Therefore, even when the plate P is boosted from 0 V to 4 V, the potential at the storage terminal 10 remains VBE. In the case where the high potential of 3 VBE+4 V has been stored at the storage terminal 10, when the potential of the word line W becomes 3 VBE, the potential of the data line is 3 VBE and that at the storage terminal 10 is also 3 VBE so that the transistor T is in the OFF state. Thus, when the plate P is boosted from 0 V to 4 V, the potential at the storage terminal 10 is also boosted to 3 VBE+4 V.
Thereafter, the potential of the word line becomes 0 V thereby to complete the rewrite operation for the memory cell(s). The dummy word line WD varies from 1 V to 4 V. Thereafter, the data line precharge signal becomes 4 V and the sense amplifier driving signals φSP and {overscore (φSN+L )} become 2 VBE thereby to precharge the data lines at 2 VBE.
The write operation will be explained with reference to the waveform chart of FIG. 55C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal becomes 4 V, the potentials on the signal write lines I and {overscore (I)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I and {overscore (I)} have become 3 VBE and VBE, respectively. Thereafter, a data line selection signal Yw is placed at 4 V by the Y decoder YD. Thus, the data line D becomes 3 VBE and the data line {overscore (D)} becomes VBE thereby to store 3 VBE at the storage terminal 10.
The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the potential at the storage terminal 11 is boosted to 3 VBE+4 V which is stored there.
As understood from the above description, also in accordance with this embodiment, the voltage amplitude of the data lines can be decreased while assuring a sufficient memory cell signal so that power consumption of the memory can be reduced. Further, the potential of the data lines is decided using as a standard the forward voltage between the base and emitter of the bipolar transistor so that a memory LSI in which MOS-FETs and bipolar transistors are mixedly provided can be easily designed.
A further embodiment of the present invention will be explained with reference to FIG. 36. This embodiment relates to another operation for the circuit shown in FIG. 40A.
The operation from the read of a memory cell signal to boosting of the potential at a storage terminal through a plate is the same as that shown in FIG. 40B. In this embodiment, after the boosting by the plate, the {overscore (WE)} signal varies from a high potential to a low potential thereby to provide a write operation. Thus, the potential of the word line W0 is boosted again from 5 V to 7 V. On the other hand, when the data line selection signal Y0 varies from 0 V to 6 V, signals are written on the data lines D0 and {overscore (D0+L )} through the data input/output lines I/O and {overscore (I/O)}. It is now assumed that 3 V is written on D0 and 0 V is written on {overscore (D0+L )}. Thus, 3 V is stored at the storage terminal 10 of the memory cell. Next, the plate P0' varies from 6 V to 3 V again. Then, the potential of the word line W0 is 7 V so that the potential at the storage terminal 10 is held by the sense amplifier. Thereafter, the potential of the word line W0 lowers to 5 V. Next, the plate P0' varies from 3 V to 6 V. Then, the potential of the word line W0 is 5 V and that of the data line D0 is 3 V so that the transistor T0 constituting the memory cell is the ON state, whereby the potential of 3 V at the storage terminal 10 is held by the sense amplifier. Further, in the case where a high potential of 5 V has been stored at the storage terminal 10, when the potential of the word line W0 becomes 5 V, the transistor T0 is turned OFF. Thus, when the plate P0' varies 3 V to 6 V, the potential at the storage terminal 10 is boosted 5 V to about 8 V (see the waveform in the case where the terminal 10 is at a high potential level). After the above operation, the potential of the word line W0 becomes 0 V thereby to complete the write of signals into the memory cell. Thereafter, the data lines D0 and {overscore (D0+L )} are precharged at 4 V and also φsp and {overscore (φSN+L )} become 4 V.
In accordance with this embodiment, the voltage amplitude of the data lines can be decreased also in the operation mode in which a write instruction is inputted with delay so that power consumption in a memory can be reduced.
A further embodiment of the present invention will be explained with reference to FIG. 57. The operation waveforms shown in
A further embodiment of the present invention will be explained with reference to
The read operation of the circuit shown in
While the data line precharge signal {overscore (φp+L )} is 4 V, the data lines D0, {overscore (D0+L )} (Dn, {overscore (Dn)}) are at a precharge potential level of 2 VBE (1.6 V). Then the sense amplifier driving signals φsp and {overscore (φSN+L )} are 2 VBE and the sense amplifier is in an OFF state. It is assumed that after {overscore (φp+L )} has become 0 V, one word line W0 has selected from the plural word lines. Then, when W0 varies from 0 V to 5 VBE (4 V), a memory cell signal appears on each data line. Now it is assumed that a high potential of 3 VBE+5 VBE=8 VBE (6.4 V) has been stored at the storage terminal (node) of the memory cell connected with the data line D0. When the word line W0 varies from 0 V to 5 VBE (4 V), a read-out signal voltage corresponding a data line capacitance Co and a storage capacitance Cs appears on the data line D0. The amount Vs of the read-out signal voltage is expressed by
where
Cs: storage capacitance
CD: data line capacitance
VBE: forward voltage (0.8 V) between the base and emitter of a bipolar transistor
Vs(`1`): storage voltage (8 VBE-2 VBE=6 VBE (4.8 V)) The amount Vs (`0`) of the read-out signal voltage in the case where a low potential has been stored in expressed by
where Vs (`0`): storage voltage (2 VBE-VBE=VBE (0.8 V))
If such a voltage relation is set, as understood from the above equations, the read-out signals are greatly different for the stored `1` and `0`. In order to eliminate such a difference, the dummy cells are provided. The dummy cells are selected in such a way that selected is a dummy cell connected with the data line opposite to the data line with which a memory cell is connected. Namely, when the word line W0 is selected, the dummy word line WD1 is selected so that a reference read-out signal voltage ΔVsD appears on the data line {overscore (D0+L )}. The value of ΔVsD is decided by the voltage DV to be stored in the dummy cell. The value of DV is set at an intermediate value between `1` and `0`, i.e. 4.5 VBE (3.6 V) If it is desired that the margin on the side of `1` is made large in view of α-ray soft error and refresh, the voltage of VD may be decreased.
After the memory cell signal and the reference signal have appeared on the data line respectively, φsp varies from 2 VBE (1.6 V) to 3 VBE (2.4 V) and {overscore (φSN+L )} varies 2 VBE. Thus, the sense amplifiers SA0 to SAn operate to amplify the corresponding memory cell signals. Therefore, the data line D0 becomes 3 VBE and the data line {overscore (D0+L )} becomes VBE. Next, the plate P0 is lowered from 5 VBE (4 V) to 0 V. Then, the word line W0 is 5 VBE (4 V) so that even when the plate voltage varies, the potential on the data line D0 remains 3 VBE. Thereafter, a pair of data lines are selected by the Y decoder YD. Now it is assumed that the data lines D0 and {overscore (D0+L )} are selected. Thus, the potential on the data line selection Y0 becomes 4 V and the memory cell signal is read out to the data input/output lines I/O and {overscore (I/O)}. This signal is amplified by the output amplifier AMP to provide an output signal Dout. Next, the word line W0 is lowered from 5 VBE (4 V) to 3 VBE (2.4 V). Thereafter, the plate P0 is boosted from 0 V to 5 VBE (4 V). Then, since a high potential of 3 VBE has been stored at the storage terminal 10 of the memory cell, the transistor T0 constituting the memory cell is in the OFF state. The potential at the storage terminal 10 is boosted from 3 VBE to 3 VBE+5 VBE (6.4 V). Incidentally, in the case where a low potential of VBE has been stored at the storage terminal 10 of the memory cell, the transistor T0 is in the ON state. Therefore, the potential at the storage terminal 10 remains VBE. Thereafter, the word line W0 becomes 0 V thereby to complete the rewrite operation mentioned above. Also, φsp and {overscore (φSN+L )} become 2 V and {overscore (φp+L )} becomes 4 V thereby to precharge the data lines to 2 VBE.
The write operation will be explained with reference to the waveform chart of FIG. 58C. After memory cell signals have been amplified by the sense amplifiers as in the read operation, a write signal Din is fetched into a data input buffer DiB. When a write control signal φw becomes 4 V, the potentials on the input/output lines I/O and {overscore (I/O)} are separated into a high potential and a low potential in accordance with Din. It is now assumed that I/O and {overscore (I/O)} have become VBE and 3 VBE, respectively. Thereafter, a pair of data lines are selected by the Y decoder YD. It is now assumed the D0 and {overscore (D0+L )} have been selected. Thus, the potential on the data line selection line Y0 becomes 4 V so that D0 and {overscore (D0+L )} become VBE and 3 VBE, respectively. Accordingly, a low potential of VBE is written at the storage terminal 10 of the memory cell (see the waveform in the case where the terminal 10 is at a high potential). On the other hand, the operation of writing a high potential signal in the memory in which a low potential signal has been stored in the memory is as follows. After the sense amplifier has been operated, the potentials on D0 and {overscore (D0+L )} are VBE and 3 VBE, respectively, in accordance with Din. Thereafter, the potential on Y0 is enhanced to 4 V so that the potentials on D0 and {overscore (D0+L )} are 3 VBE and VBE. Accordingly, the low potential of 3 V is written at the storage terminal of the memory cell (see the waveform in the case where the terminal 10 is at a low potential).
The operation after the signal has been written in the memory cell in the above manner is the same as the read operation as previously mentioned. Namely, the high potential signal in the memory cell is boosted to 3 VBE+5 VBE=8 VBE (6.4 V) which is stored whereas the low potential signal of VBE is stored as it is. Further, the constant voltage DV is written in the dummy cell by the dummy cell write signal DC through MOS-FET T3.
As explained above, in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, the voltage amplitude of the data lines (voltage amplitude when the sense amplifiers operate), which affects the power consumption of the memory can be decreased, and the voltage amplitude of the plates, which decides the high potential level of the memory cells relative to the data retention time for the memory cell. In this embodiment, the voltage amplitude of the plate is set to be larger than that of the data lines. In this way, the power consumption can be remarkably reduced while assuring a sufficient signal voltage for the memory cells. Therefore, reduced power consumption and high S/N can be simultaneously realized. Further, in this embodiment, the potential on the data lines during its precharge is set at an intermediate value between the high and low potentials of the voltage amplitude of the data lines. This permits the power consumption to be further reduced. Moreover, the voltage amplitude of the data line can be decreased to the neighborhood of a sum of the absolute values of the threshold voltages of the N channel MOS-FET and P channel MOS-FET. Since the threshold voltage is generally 0.5 V to 1 V, the charging/discharging current in the case of the data line voltage amplitude of 2 VBE (1.6 V) can be decreased to about {fraction (1/3+L )} in the case of that of 5 V. Further, in this embodiment, dummy cells are provided so that the storage voltage can be freely controlled. Therefore, the read-out signal amount of `1` or `0` can be controlled so that a memory having the characteristics of high α-ray soft error resistance, unvaried refresh and low power consumption can be designed. Moreover, the respective operation voltages such as the potential on the data lines are decided using as a standard the forward voltage between the base and the emitter of the bipolar transistor so that a memory LSI in which MOS-FETs and bipolar transistors are mixedly provided can be easily designed.
where V is the base-emitter voltage of the transistor Q0. Thus, the value of DV can be optionally set in accordance with the resistances of the resistors R2 and R3.
A further embodiment of the present invention will be explained with reference to FIG. 60. The memory circuit shown in
The read operation of the circuit shown in
The rewrite operation of a signal into a memory cell will be explained. After the sense amplifier has been operated, D0 is at a high potential of 5 VBE and {overscore (D0+L )} is a low potential of 3 VBE. Then, the storage terminal 10 of the memory cell is at the high potential of 5 VBE like D0 since the word line W0 is at the high potential level. Then, the potential at the plate P0' is changed from 5.5 VBE (4.4 V) to 2.5 VBE (2 V). However, the potential on the data line and at the storage terminal are held 5 VBE by the sense amplifier and not varied. Thereafter, the potential on the word line W0 is lowered from 5.5 V to 5 VBE. Then, assuming that the threshold voltage of a transistor substituting the memory cell is 1 V, both potentials of at the storage terminal 10 and on the data line D0 are 5 VBE and also that on the word line W0 is 5 VBE so that the transistor T0 is in the OFF state. Therefore, when the potential on the plate P0' is changed from 2.5 VBE to 5.5 VBE, the potential at the storage terminal 10 is boosted from 5 VBE to about 8 VBE (6.4 V). Thus, the high potential of about 8 VBE is written in the memory cell.
On the other hand, the rewrite operation in the case where a signal at a low potential has been stored in the memory will be explained with reference to the waveform in the case where the terminal 10 in
Meanwhile, in this embodiment, the potential of the memory cell connected with a non-selected word line is varied in its potential. Then, the behavior of a storage terminal 11 of the memory cells connected with a non-selected word line W1 will be explained. The operation in the case where a high potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P0 is at 5.5 VBE and the storage terminal 11 is at 8 VBE. After the sense amplifier has amplified the memory signal, P0' becomes 2.5 VBE and then the storage terminal 11 becomes 5 VBE. Then, the word line W1 becomes 0 VBE and the data line {overscore (D0)} becomes 3 VBE so that a transistor T1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P0' becomes 5.5 VBE and the storage terminal 11 returns to 8 V.
The operation in the case where a low potential has been stored at the storage terminal 11 is as follows. During the stand-by time of the memory, the plate P0' is at 5.5 VBE and the storage terminal 11 is at 3 VBE. After the sense amplifier has amplified the memory signal, P0' becomes 2.5 VBE and then the storage terminal 11 becomes 0 V. Then, the word line W1 becomes 0 VBE and the data line {overscore (D0)} becomes 5 VBE so that a transistor T1 is never in the ON state and so the signal in the memory cell is not destroyed. Thereafter, the plate P0 becomes 5.5 VBE and the storage terminal 11 returns to 8 VBE.
Thereafter, the potential on the word line W0 becomes 0 V to complete the rewrite operation. Subsequently, φSP and {overscore (φSN+L )} become 4 V. {overscore (φp+L )} becomes the high potential to precharge the data line to 4 V.
The write operation in the circuit shown in
As understood from the description, also in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, the charging/discharging current for the data lines can be decreased and so power consumption of the memory can be reduced. Further, reduction of the voltage to be written into the memory cells due to decreasing of the voltage amplitude of the data lines is compensated for by the write operation from the plates. Therefore, the characteristics of data retention time and (x-ray resistance soft error can be improved. Further, in this embodiment, dummy cells are provided so that the storage voltage can be freely controlled. Therefore, the read-out signal amount of `1` or `0` can be controlled so that a memory having the characteristics of high a-ray soft error resistance, unvaried refresh and low power consumption can be designed. Moreover, the respective operation voltages such as the potential on the data lines are decided using as a standard the forward voltage between the base and the emitter of the bipolar transistor so that a memory LSI in which MOS-FETs and bipolar transistors are mixedly provided can be easily designed. Furthermore, since one plate is commonly provided for two word lines W0 and W1, the areas of the memory chip can be decreased.
In accordance with this embodiment, the voltage amplitude of the data lines in operating the sense amplifiers can be greatly decreased so that the data line charging/discharging current can be decreased, thereby reducing the power consumption in a memory cell array to {fraction (1/2+L )} to ⅓l of the conventional memory cell array. Further, the memory cell signal at a high potential is boosted from the plate so that the memory cell signal can be increased. Accordingly, the present invention is efficient to implement the low power consumption in a memory and the high S/N thereof. More specifically, the present invention can improve the characteristics of data retention time, α-ray soft error resistance, noise reduction and reliability.
A further embodiment of the present invention will be explained with reference to
In
The peripheral circuit uses the voltage generated by the voltage limiting circuit and the voltage input from the outside of the chip. Decreasing the voltage amplitude of the pulse signals by the voltage limiting circuit intends to reduce power consumption in the memory chip. The memory array provides very large charging/discharging current on the data lines. The voltage amplitude of the data lines is set at a relatively large value for the purpose of assuring the charges to be stored in the memory cell. However, the charges stored in the memory cell is about {fraction (1/10+L )} or less of the charge on the data line. Namely, most charges are not employed but consumed as useless charging/discharging current. Meanwhile, if the charges stored in the memory cell can be increased irrespectively of the voltage amplitude of the data lines, the voltage amplitude of the data lines may be decreased. Then, in accordance with this embodiment, the stored charges are increased irrespectively of the voltage amplitude of the data lines so as to decrease the voltage amplitude of the data lines, thereby reduce the power consumption in the memory. As a technique of increasing the stored charges, there are proposed a method of increasing the capacitance of the capacitor in the memory cell and a method of writing a memory cell signal into the memory cell selected by the word line from a plate thereby to increase the stored charges, By means of these methods, reduced power consumption can be realized while assuring sufficient stored charges.
In accordance with this embodiment, power consumption of DRAM can be greatly reduced. Thus, the characteristic of data retention can be improved and also noise can be reduced so that malfunction of DRAM can be obviated. Further, DRAM can be operated using a battery so that it can be widely applied to a portable device. Incidentally, although in this embodiment, a battery is used as a power source, the voltage produced from a commercially available power supply may be employed.
A further embodiment of the present invention will be explained with reference to
The read operation of the circuit shown in
While the data line precharge signal {overscore (φp+L )} is 5 V, the data lines are precharged at a data line precharge voltage Vdp (=4 V). Then, the sense amplifier signal lines CSP and CSN are also 4 V. Therefore, the sense amplifiers are in the OFF state. After {overscore (φp+L )} has been changed to 0 V). one of the word lines is selected by the X decoder. It is assumed that the word line W0 has been selected. When W0 becomes 7 V, a memory cell signal appears on each data line. Now, it is assumed that a signal (1) at a high potential level has been stored in the memory cell MC0. Therefore, the potential of the data line D0 becomes slightly higher than 4 V. Next, CSP and CSN are changed from 4 V to 5 V and to 3 V, respectively by the sense amplifier driving signal generating circuit CD. Thus, the sense amplifiers SA0 to SAn operate to amplify the memory signals. Then, the data line D0 becomes a high potential level of 5 V and the data {overscore (D0)} becomes a low potential of 3 V. Thereafter, the potential at the plate P0 is changed from 5 V to 2 V by the plate driving circuit PD. Then, the potential at the storage node NO of each selected memory cell or that of the data line thereof varies through capacitive coupling, but the potential at each node is recovered to its previous level since it is held by the sense amplifier. Next, a pair of data lines are selected from the plural pairs of data lines by the Y decoder YD. It is now assumed that D0 and {overscore (D0)} are selected. Thus, the potential of the data line selection line Y0 from the Y decoder becomes 5 V so that the memory cell signal is read out on the data input/output lines IOs. This signal is amplified by the output amplifier DOB to provide an output signal D0. Incidentally, on the contrary, in a write operation, an input signal taken by the data input buffer DiB is written in the memory cell by the data input/output lines and the data lines when Y0 becomes 5 V.
After the input and output of the memory cell signal has been performed in the above manner, the potential of the word line W0 becomes 5 V. Then, the storage node NO of the memory cell MC0 is 5 V and the data line D0 is also 5 V so that the transistor T0 is in the OFF state. Next, the potential of the plate P0 varies from 2 V to 5 V. Thus, the storage node N0 of the memory cell MC0 is boosted from 5 V to about 8 V. Next, when the word line WO becomes 0 V, 8 V is stored in the memory cell MC0. Thereafter, φp becomes 5 V thereby to precharge the data lines. Also, CSP and CSN become 4 V.
In the case where a signal at a low potential level ("0") has been stored in the memory cell MC0 after the sense amplifier has been operated, D0 and {overscore (D0)} become 3 V and 5 V, respectively. Therefore, even when the potential of the word line W0 has become 5 V, the transistor T0 in the memory cell MC0 remains ON. Thereafter, when the plate P0 varies from 2 V to 5 V, the potential at the storage node N0 of the memory cell MC0 is slightly increased, but it is returned to 3 V since it is held by the sense amplifier. Thereafter, when the word line W0 becomes 0 V, 3 V is stored in the memory cell MC0.
Meanwhile, in this embodiment, the plate potential of a non-selection memory cell is also varied, whereby the potential at the storage node of the non-selection memory cell is varied. This will be explained with respect to the potential change at a node N1. Assuming that the signal at the high potential level (`1`) has been stored at the storage node N1, during the stand-by time of the memory, N1 is 8 V. Thereafter, when the plate P0 varies in the sequence of 5 V-2 V-5 V, N1 varies in the sequence of 8 V-5 V-8 V. Then, W1 is 0 V and D0 is 5 V or 3 V and so the transistor T1 of the memory cell is in the OFF state so that any problem does not occur. On the other hand, assuming that the signal at the low potential level (0) has been stored at the storage node. N1; during the stand-by time of the memory, N1 is 3 V. Thereafter, when the plate P0 varies in the sequence of 5 V-2 V-5 V, N1 varies in the sequence of 3 V-0 V-3 V. Then, W1 is 0 V and D0 is 5 V or 3 V and so the transistor T1 of the memory cell is in the OFF state so that any problem does not occur. In this way, by boosting the lower potential level of the memory cell, erroneous selection of the non-selection memory cell due to the potential change of the plate can be prevented.
As understood from the above description, also in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, by decreasing the charging/discharging current for the data lines which provide a large parasitic capacitance and also a large charging/discharging current and increasing the voltage amplitude of the plates which provide a small parasitic capacitance, power consumption in the memory can be reduced while assuring a sufficient memory cell signal. In this case, setting the voltage amplitude of the data lines at a larger value than that of the plates is efficient to realize them. In this embodiment in which the data line voltage amplitude is 1 V, the charging/discharging current can be decreased to {fraction (1/5+L )} of the conventional case where it is 5 V. The data line voltage amplitude may be decreased to the neighborhood of the threshold voltage of the MOS-FETs which constitute the sense amplifier, but it is desired to satisfy, in view of the stability of the operation, the condition, |Vtn|÷|Vtp|<ΔVd (Vtn: threshold voltage of NMOS, Vtp: threshold voltage of PMOS, Vd; data line voltage amplitude). The power consumption in driving the plate may be neglected in e.g. a memory array of 256 word lines×1024 data line pairs since the capacitance charged/discharged at a time is as small as 200 to 300 pF for the data line and 2 to 3 pF for the plate.
Further, in accordance with this embodiment, the precharging potential of the data line is set at an intermediate level between the high potential and the low potential of the data line voltage amplitude. Thus, the power consumption can be further reduced. Moreover, a capacitor in each memory cell is generally made using a thin oxide film. Correspondingly, in this embodiment, the plate potential is set, during the stand-by time of the memory, at an intermediate level between two storage potential level used in the memory cell. Therefore, the electric field applied to the capacitor of the memory cell is made small, thereby improving the reliability of the memory. Further, in this embodiment, the memory cell signal is larger on the high potential side than the low potential side so that the characteristics of data retention and a-ray soft error resistance can be improved.
A further embodiment of the present invention will be explained with reference to
The read operation of Ie circuit shown in
While the data line precharge signal {overscore (φp+L )} is 1.5 V, the data lines are precharged at a data line precharge voltage Vdp (=1.2 V). Then, the senser amplifier signal lines CSP and CSN are also 1.2 V. Therefore, the sense amplifiers are in the OFF state. After {overscore (φp+L )} has been changed to 0 V, one of the word lines is selected by the X decoder. It is assumed that the word line W0 has been selected. When W0 becomes 2 V, a memory cell signal appears on each data line. Now, it is assumed that a signal (`1`) at a high potential level has been stored in the memory cell MC0 Therefore, the potential of the data line D0 becomes slightly higher than 1.2 V. Next, CSP and CSN arc changed from 1.2 V to 1.5 V and to 0.9 V, respectively by the sense amplifier driving signal generating circuit CD. Thus, the sense amplifiers SA0 to SAn operate to amplify the memory signals. Then, the data line D0 becomes a high potential level of 1.5 V and the data line D0 becomes a low potential of 0.9 V. Thereafter, the potential at the plate P0 is changed from 1.5 V to 0.6 V by the plate driving circuit PD. Then, the potential at the storage node N0 of each selected memory cell or that of the data line thereof varies through capacitive coupling, but the potential at each node is recovered to its previous level since it is held by the sense amplifier. Next, a pair of data lines are selected from the plural pairs of data lines by the Y decoder YD. It is now assumed that D0 and {overscore (D0)} are selected. Thus, the potential of the data line selection line Y0 from the Y decoder becomes 1.5 V so that the memory cell signal is read out on the data input/output lines IOs This signal is amplified by the output amplifier DOB to provide an output signal D0. Incidentally, on the contrary, in a write operation, an input signal taken by the data input buffer DiB is written in the memory cell by the data input/output lines and the data lines when Y0 becomes 1.5 V.
After the input and output of the memory cell signal has been performed in the above manner, the potential or the-word line W0 becomes 1.5 V. Then, the storage node N0 of the memory cell MC0 is 1.5 V and the data line D0 is also 1.5 V so that the transistor T0 is in the OFF state. Next, the potential of the plate P0 varies from 0.6 V to 1.5 V. Thus, the storage node N0 of the memory cell MC0 is boosted from 1.5 V to about 2.4 V. Next, when the word line W0 becomes 0 V, 2.4 V is stored in the memory cell MC0. Thereafter, {overscore (φp)} becomes 1.5 V thereby to precharge the data lines. Also, CSP and CSN become 1.2 V.
In the case where a signal at a low potential level (`0`) has been stored in the memory cell MC0 after the sense amplifier has been operated, D0 and {overscore (D0)} become 0.9 V and 1.5 V, respectively. Therefore, even when the potential of the word line W0 has become 1.5 V, the transistor T0 in the memory cell MC0 remains ON. Thereafter, when the plate P0 varies from 0.6 V to 1.5 V, the potential at the storage node N0 of the memory cell MC0 is slightly increased, but it is returned to 0.9 V since it is held by the sense amplifier. Thereafter, when the word line W0 becomes 0 V, 0.9 V is stored in the memory cell MC0.
Meanwhile, also in this embodiment, the plate potential of a non-selection memory cell is also varied, whereby the potential at the storage node of the non-selection memory cell is varied. This will be explained with respect to the potential change at a node N1. Assuming that the signal at the high potential level (1) has been stored at the storage node N1, during the stand-by time of the memory, N1 is 2.4 V. Thereafter, when the plate P0 varies in the sequence of 1.5 V-0.6 V-1.5 V, N1 varies in the sequence of 2.4 V-1.5 V-2.4 V. Then, W1 is 0 V and D0 is 1.5 V or 0.9 V and so the transitor T1 of the memory cell is in the OFF state so that any problem does not occur. On the other hand, assuming that the signal at the low potential level (`0`) has been stored at the storage node N1, during the stand-by time of the memory, N1 is 0.9 V. Thereafter, when the plate P0 varies in the sequence of 1.5 V-0.6 V-1.5 V, N1 varies in the sequence of 0.9 V-0 V-0.9 V. Then, W1 is 0 V and D0 is 1.5 V or 0.9 V and so the transistor T1 of the memory cell is in the OFF state so that any problem does not occur. In this way, by boosting the lower potential level of the memory cell, erroneous selection of the non-selection memory cell due to the potential change of the plate can be prevented.
As understood from the description, also in accordance with this embodiment, the voltage amplitude of the data lines and that of the voltage to be written into the memory cells can be determined independently from each other. Therefore, by decreasing the charging/discharging current for the data lines which provide a large parasitic capacitance and also a large charging/discharing current and increasing the voltage amplitude of the plates which provide a small parasitic capacitance, power consumption in the memory can be reduced while assuring a sufficient memory cell signal. In this case, setting the voltage amplitude of the data lines at a larger value than that of the plates is efficient to realize them. In this embodiment in which the data line voltage amplitude is 1 V, the charging/discharging current can be decreased to {fraction (1/5+L )} of the conventional case where it is 5 V. The data line voltage amplitude may be decreased to the neighborhood of the threshold voltage of the MOS-FETs which constitute the sense amplifier, but it is desired to satisfy, in view of the stability of the operation, the condition, |Vtn|÷|Vtp<Vd (Vtn: threshold voltage of NMOS, Vtp: threshold voltage of PMOS, Vd: data line voltage amplitude).
Further, in accordance with this embodiment, the precharging potential of the data line is set at an intermediate level between the high potential and the low potential of the data line voltage amplitude. Thus, the power consumption can be further reduced. Moreover, a capacitor in each memory cell is generally made using a thin oxide film. Correspondingly, in this embodiment, the plate potential is set, during the stand-by time of the memory, at an intermediate level between two storage potential level used in the memory cell. Therefore, the electric field applied to the capacitor of the memory cell is made small, thereby improving the reliability of the memory. Further, in this embodiment, the memory cell signal is larger on the high potential side than the low potential side so that the characteristics of data retention and α-ray soft error resistance can be improved.
Further, in accordance with this embodiment, DRAM with a power supply voltage of 1.5 V and reduced power consumption can be realized. Therefore, DRAM which can be operated during, both the stand-by and operation of a memory can be realized. Also, DRAM can be operated with a power supply voltage so that exchange between a normal power supply source and battery can be easily made. Thus, the application of DRAM can be extended.
A further embodiment of the present invention will be explained with reference to
Incidentally, in the waveform shown in
The operation of the circuit shown in
The operation of this circuit will be explained with reference to FIG. 68B. During the stand-by time of a memory, φp is 5 V, φsap is 5 V and φsan is 0 V so that CSP and CSN are precharged at 4 V. When {overscore (φp+L )} becomes 0 V, a word line is selected whereby a memory cell signal appears on a data line. Thereafter, φsap and φsan become 0 V and 5 V, respectively. Thus, transistors T81 and T82 are turned ON so that CSP and CSN become 5 V and 3 V, respectively. Thereafter, φsap becomes 5 V, φsan becomes 0 V and {overscore (φp+L )} becomes 5 V so that CSP and CSN are precharged at 4 V.
The manner of operating such a chip at a power supply voltage of 1.5 V is as follows. The bonding pad 106 is connected with a power supply pin for the package. It is assumed that when a node 107 is at a low level, the voltage limiter L is OFF to provide an output terminal with high impedance, and when a node 107 is at a high level, it is ON thereby to operate. Therefore, the bonding pad 104 is not connected with anywhere but is placed in the open state. Also the bonding pad 105 is placed in the open state. Thus, the voltage of 1.5 V is applied to the memory array 103 and the peripheral circuit 102. On the other hand, the manner of operating the chip at a power supply voltage of 3.3 V is as follows. The bonding pad 105 is connected with the power supply pin for the package. The bonding pad 104 is also connected with the power supply pin thereby to place the node 107 in the high level. Thus, the voltage limiter L becomes ON, The bonding pad 106 is placed in the open state. Thus, the voltage lowered to 1.5 V by the voltage limiter is applied to the peripheral circuit 102 and memory array 105.
In this way, in accordance with this embodiment, the circuits in the chip other than the input/output interface circuit are always operated at a fixed voltage so that the operation speed and power consumption can be held substantially constant. Such a memory chip is convenient to use for a user. Further, two kinds of products can be made from one chip so that the production cost of the memory chip can be reduced. Moreover, the products are classified according to the bondings so that the number of the products can be easily adjusted. Further, in this embodiment, the ON/OFF is switched according the bonding, but is may be switched by using fuse provided on the chip. Also, it may be controlled by using the result of a logic gate provided in the memory chip to which plural input signals to the memory chip are applied. Incidentally, the idea of this embodiment may be also applied to the other chip in which the circuits indicated by numerals 102 and 103 are a combination of a memory circuit and a logic circuit or only logic circuits.
In this way, also in accordance with this embodiment, the circuits in the chip other than the input/output interface circuit are always operated at a fixed voltage so that the operation speed and power consumption can be held substantially constant. Such a memory chip is convenient to use for a user. Further, two kinds of products can be made from one chip so that the production cost of the memory chip can be reduced. Moreover, the products are classified according to the Al master-slice so that a small number of bonding pads are required thereby reducing the chip area.
In accordance with this embodiment, when the power supply voltage is varied in the range of 1.5 V to 3.3 V, the memory array and the peripheral circuit ate operated at 1 V. Therefore, with any optional power supply voltage between 1.5 V and 3.3 V, the memory chip can be operated. The circuits in the chip are always operated at the fixed voltage of 1 V so that the operation speed and power consumption can be held substantially constant. Such a memory chip is convenient to use for a user. Further, the ON/OFF control of the voltage limiter is not required so that the chip arrangement can be simplified. Incidentally, in this embodiment, 1.5 V corresponds to one battery and 3.3 V corresponds to two batteries so that the memory chip can be operated using one. battery or two batteries.
In accordance with this embodiment, the power consumption in DRAM can be greatly reduced. Particularly, the voltage amplitude of the data lines in operating the sense amplifiers can be greatly reduced as compared with the conventional case so that the charging/discharging current on the data line can be reduced. Further, the memory cell signal can be increased by rewriting it from a plate. Thus, the characteristics of data retention and a-ray soft error resistance of DRAM can be improved. Accordingly, reduced power supply voltage and reduced power consumption in DRAM can be realized so that DRAM can be operated using a battery(s).
Explanation will be given for several embodiments of improvements of the sense amplifier in their circuit configuration and operation which can assure the high speed operation of a memory at a relatively low power Supply voltage (2 V or less). In the embodiments explained hereinafter, the sense amplifier is improved on the basic premise of a precharging system of precharging the potential on a data line at an intermediate level between the high potential and low potential appearing on the data line (simply called "half precharge system") in which with the high potential of a power supply voltage of Vcc and the low potential of 0 V, the data line is precharged at {fraction (1/2+L )} Vcc.
The operation of this embodiment is different from the case of using the conventional sense amplifier when VDL is a low voltage of 1.0 V. or so. More specifically, in the case where the high Vth MOS transistors (VTO=0.5 V) as shown in
The low Vth MOS transistors as shown in
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI (e.g. pass gate) which can operate at a comparatively low power supply voltage can also be provided.
The operation of the circuit of
In order to provide the boosted voltages on the order shown in
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of-a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
In the circuit arrangement of
The operation of this circuit of
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
In the circuit arrangement of
The operation of this circuit of
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
The operation of the circuit of
Any voltage values at the respective terminals other than the values shown in
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
Incidentally, the voltage relation should not be limited to those as shown in
The operation of the circuit of
In order to drive the plate voltage for dummy word lines at a high speed, as shown in
The voltage of VDP may be generated by boosting VDL or reducing an external power supply voltage. Further, the sense amplifier driving transistors QP1, QP2, QN1 and QN2 may be P channel MOS transistors, N channel MOS transistors or bipolar transistors as long as the potential of the sense amplifier driving line can be varied from HVC to VDL on the side of CSP and can be varied from HVC to VSS on the side of CSN. By placing the substrate potential of Q3 and Q4 in the sense amplifier at the same potential level as the sense amplifier driving line CSP or placing that of Q1 and Q2 in the sense amplifier at the same potential level as the sense amplifier driving line CSN, the increase of the threshold voltage thereof due to the body effect can be prevented, thereby further improving the operation of the sense amplifiers. Placing the substrate potential in the sense amplifier at the same potential as the sense amplifier driving line can be realized by using the triple well structure of the substrate. Further, by commonly using the sense amplifier driving line CSP or CSN and a wiring for precharging, the precharging speed can be enhanced without increasing the wiring area. Moreover, by using the low Vth MOS transistors in the embodiment of
Accordingly, in accordance with this embodiment, by varying the operation amplitude of the circuit in accordance with the power supply voltage, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
The operation of the circuit of
Any voltage value at the respective terminals other than the values shown in
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
The operation of the circuit of
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
The operation of the circuit of
Further, in accordance with this embodiment, it is possible to set the low level of CHN at a negative value so that the gate-source voltage of PMOS can be further increased which permits the operation at a further reduced voltage. For example, if the low level of CHN is set at -0.5 V, with the gate-source voltage of 0.8 V which allows a normal operation, the data line voltage amplitude can be reduced to 0.3 V which is lower than the threshold voltage of the transistors in the sense amplifier.
Further, also in this embodiment, during the precharting time, the data lines are short-circuited and precharged by the precharging signal PC as in the embodiment of e.g.
In this way, in accordance with this embodiment, even if the voltage amplitude of the data lines is smaller than the threshold voltage of the transistors in the sense amplifier for driving the data lines, the gate-source voltage thereof in driving can be made sufficiently higher than the threshold voltage, which makes it possible to realize the high speed operation and reduced power consumption. Thus, in accordance with this embodiment, a memory circuit which can operate at a substantially low power supply voltage without injuring the speed performance thereof can be provided. Further, the gist of the present invention is that by decreasing the voltage amplitude of signal lines (data lines in this embodiment) with large load capacitance, the circuit for driving the signal lines is driven with a voltage amplitude which is sufficiently larger than the operating threshold voltage of the elements constituting the sense amplifier. Therefore, the idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided. Moreover, by optimizing the combination of a small or large voltage amplitude and a threshold voltage, an LSI with the performances of high speed operation and reduced power consumption can be provided. For example, by using depletion type MOS-FETs for a part of Q1 to Q4, further high speed operation can be realized.
The operation of
Accordingly, in accordance with this embodiment, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided. Incidentally, the gist of the present invention is that means of detecting the operation threshold voltage of the elements is provided and the threshold voltage is controlled by an output from the means so that it is an optimum value for circuit operation and so the circuit arrangement should not be limited to the arrangement mentioned above.
The present invention has been explained in relation to DRAM, but may be applied to an LSI in any form including a random access memory (RAM) (dynamic or static), a read only memory (ROM), a logic LSI such as a microcomputer, etc. Further, the elements or devices to be used may be bipolar transistors, MOS transistors, the combination thereof, or transistors made of the material e.g. GaAs other than Si.
Accordingly, in accordance with the present invention, a memory circuit which can operate at a comparatively low power supply voltage without injuring the speed performance can be realized. This memory circuit can be used as a memory for battery back-up or battery operation. The idea in this embodiment can also be applied to the circuit components other than the sense amplifiers whereby an LSI memory with the performances of a high operation speed and reduced power consumption can be provided. Further, without being limited to the memory LSI, the other LSI such as a logic LSI which can operate at a comparatively low power supply voltage can also be provided.
Further, in accordance with the present invention, one chip ULSI which can operate in accordance with a wide range of power supply voltage can be realized. Also, the ULSI with reduced power consumption can be accomplished. One chip ULSI which can correspond to a number of input/output levels can also be realized.
It is further understood by those skilled in the art that the foregoing description is preferred embodiments of the disclosed devices and that various changes and modifications may be made in the invention without departing from the spirit and scope thereof.
Itoh, Kiyoo, Etoh, Jun, Tanaka, Hitoshi, Nakagome, Yoshinobu, Kume, Eiji, Kawajiri, Yoshiki
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Jun 10 1998 | Hitachi, Ltd. | (assignment on the face of the patent) | / | |||
| Jun 10 1998 | Hitachi ULSI Systems Co., Ltd. | (assignment on the face of the patent) | / | |||
| Jun 14 2006 | Hitachi, LTD | Elpida Memory, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 018563 | /0278 | |
| Jun 14 2006 | HITACHI ULSI SYSTEMS CO , LTD | Elpida Memory, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 018563 | /0278 | |
| Apr 10 2012 | Elpida Memory, Inc | Apple Inc | SECURITY AGREEMENT | 028209 | /0477 | |
| Jul 26 2013 | PS4 LUXCO S A R L | ELPIDA MEMORY INC | SECURITY AGREEMENT | 032414 | /0261 | |
| Jul 26 2013 | Elpida Memory, Inc | PS4 LUXCO S A R L | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 032899 | /0588 | |
| Jan 14 2014 | Apple, Inc | Elpida Memory, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 032331 | /0637 |
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