Lead frame and semiconductor device

Abstract

A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.

Description

illustrating a portion

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The lead frame and semiconductor device according to embodiments of the present invention will now be described in conjunction with the drawings.

FIG. 1 is a partial perspective view of the lead frame according to an embodiment of the present invention, and FIG. 2 is a pad-hanging pad supporting leads 3 (FIG. 1) and the chip pad 1, and is sealed with the resin plastic portion 5 and is then cut away from the outer frame to which it had been coupled.

The semiconductor chip 4 is composed of silicon (Si) whose coefficient of linear expansion α is about 3×10^-6/°C C. The lead frame is usually composed of a 42 alloy (Fe-42Ni) (α=5×10^-6/°C C.) or a copper alloy (α=17×10^-6/°C C.). The plastic 5 has a coefficient of linear expansion α of 20 to 30×10^-6/°C C. In this embodiment, the chip pad 1 is divided into has a generally circular central island portion 1a and a an outer peripheral annular portion 1b. Symbol 1c denotes leads the to couple the island portion 1a and the annular peripheral portion 1b together. As is obvious from FIG. 24, furthermore, the adhesive 18 is applied onto the island portion 1a only.

In the conventional semiconductor device, the constituent materials have dissimilar coefficients α of linear expansion. Therefore, the chips constructed in a large size are accompanied by such problems as cracking resulting from the step of die bonding for joining mounting the chip and on the chip pad together or due to temperature aging after the die bonding and cracking in the plastic at the lower edge of the chip pad due to cooling after the semiconductor device is sealed with plastic or due to temperature cycle testing. Furthermore, if the a semiconductor device left to stand in the air for extended periods of time is mounted on the surface of the a substrate, cracks often develop in the plastic (hereinafter referred to as crack in during the solder reflow). Contents of the defective modes will now be described.

The thermal stress is generated at the time of die bonding since the semiconductor chip and the chip pad material have dissimilar coefficients of linear expansion. If the adhesive yields, therefore, tensile stress results on the surface of the element chip due to temperature aging after the die bonding.

In the case of the copper (Cu) lead frame and the adhesive composed of a 95 Pn-5 Sn solder, the tensile stress becomes as shown in FIG. 35. The tensile stress increases with the increase in the chip size, and often exceeds the breaking strength of the chip. It is therefore attempted to use a lead frame material of the Fe-Ni type having a small coefficient of expansion and to use a die bonding agent having a very small elasticity, to decrease the stress that results in the chip.

The cracks develop in the plastic at the lower corner of the chip pad during the temperature cycle testing cycling since the stress developed is concentrated at the lower corner of the chip pad due to difference in the coefficient of linear expansion between the lead frame material and the plastic material. In particular, if the plastic peels off from the chip pad of the side opposite to the chip, the stress at the lower corner of the chip pad increases stepwisely as shown in FIG. 36. The stress increases so rapidly with the increase in the chip pad siz size (chip size) that cracks develop in the plastic. A curve i represents peeling between the chip pad and the plastic, which exhibits relative slippage, and a curve ii represents whole-surface adhesion without relative slippage. To prevent the cracks from developing in the plastic at the lower corner of the chip pad, holes are formed (referred to as dimple formation) in the chip pad on the side opposite to the chip, and the plastic is charged into the holes thereby preventing the relative slippage caused by the peeling between the chip pad and the plastic portion.

To mount the semiconductor device on the substrate practically, the solder connection portion of the lead and the connection portion of the substrate are tentatively adhered together with a solder paste or the like, and the whole substrate is heated up 200°C to 250°C C. for several tens of seconds to several minutes, for example, by an infrared ray reflow equipment or by a vapor phase reflow equipment. The semiconductor device is thus joined with the solder and is mounted on the substrate. This is called a reflow soldering process.

In fact, however, cracks develop in the plastic during the reflow soldering process if the above-mentioned reflow is carried out using the semiconductor device that is left to stand in the atmosphere for extended periods of time or using the semiconductor device that is preserved in an environement environment having a relatively high humidity even for a short period of time.

This is due to the following reasons. That is, the plastic absorbs moisture in the air while the semiconductor device is being preserved, and the moisture remains in the plastic or in a small gap between the plastic portion and the surface of the chip pad on which the plastic is adhered. If the semiconductor device that has absorbed moisture is subjected to the reflow soldering process, the moisture on the interface between the plastic and the chip pad turns into vapor and expands due to quick heating, and a an excessive stress is generated in the plastic as a result of the vapor pressure. Even if there is no moisture on the interface of adhesion, the moisture contained in the plastic diffuses and is condensed on the interface of adhesion giving rise to the generation of stress in the plastic in a manner as described above.

Thus, there develop reflow cracks as designated at 10 in FIG. 6.

According to this the embodiment as shown in FIGS. 23 and 24, however, the chip pad 1 is divided into an has a generally circular island portion 1a and an annular outer peripheral portion 1b. At the time of die bonding, therefore, the adhesive 18 is applied to the island portion 1a only, and the annular outer peripheral portion 1b plays the role of a stabilizer plate for stably placing the chip on the chip pad 1. First, discussed below is an effect for improving chip cracks that in many cases develop at the center of the long side of the chip. Therefore, if it is presumed that the long side chip has a size of 9 mm □ square which is a representative size of the chip and if the chip is adhered over a central area of 2 mm □ square only, then the stress that is generated is in the chip can be reduced to 60% in light of the value shown in FIG. 35, compared with that of the conventional chip that is adhered over its entire surface.

After the die bonding, the package is prepared through the step of molding. Next, discussed below are cracks that develop in the plastic at the lower corner of the chip pad due to the temperature cycle testing. The plastic cracks at the lower corner of the chip pad develop in many cases at the center in of the short long side of the chip pad. Therefore, a chip pad width of 4.2 mm is selected. In FIG. 36, the chip pad is presumed to have a width of 4.2 mm. If the relative slippage is eliminated according to the embodiment of the invention, then the plastic stress at the lower edge of the chip pad can be reduced to 38% compared with that of when there exists the prior art in which a relative slippage occurs between the chip pad on the side opposite to the chip and the plastic of the prior art.

Finally, the effect for the reflow soldering is calculated. In using the conventional chip pad having a size of 4.3 mm×9.3 mm, it is presumed that the back surface of the chip and the plastic interface are peeled off from each other in the embodiment of the invention, the length of the short side of the peeled portion being 2.4 mm, and the length of the long side being 2.6 mm. In compliance with the equation (1), therefore, B=0.5 and a=4.2 mm in the case of the conventional chip pad, and B=0.33 and a=2.4 mm in the case of the chip pad of the embodiment of the invention. According to the embodiment of the present invention, therefore, a maximum stress σ_max of the semiconductor devices decreases to about 22% compared with that of the conventional device. If the breaking strength of the plastic remains the same, resistance against the pressure increases by 4.6 times.

According to the embodiment of the invention as described above, the strength can be strikingly increased against the propensity for chip cracks, against plastic cracks at the lower corner of the chip pad caused by the temperature cycle testing cycling, and against reflow cracks.

As for the plastic cracks at the lower corner of the chip pad caused by the temperature cycle testing cycling, the relative slippage between the chip pad of the side opposite to the chip and the plastic is prevented by the plastic 20 that is charged into the portions holes formed by punching the chip pad. Therefore, generation of the stress can be suppressed at the lower corner of the chip pad, and plastic cracks are prevented from developing.

The coefficient of linear expansion of the plastic is greater than that of the chip pad. When subjected to a high temperature at the time of reflow soldering, therefore, the plastic being charged into perforated portions as designated at 20 in FIG. 24 is pressed onto the side peripheral surfaces 21 of the holes in the chip pad. Moreover, since the side peripheral surfaces of the chip pad prepared have been made rugged, the side surfaces of the chip pad designated at 21 in FIG. 24 prevent the plastic from swelling toward the lower side of the chip pad even in the case where the adhesive bonding force is insufficient between the plastic designated at 22 in FIG. 24 and the chip. In FIG. 24, the side peripheral surfaces 21 serve as fixed fulcrums. Therefore, the length a in the equation (1) becomes sufficiently small compared with that of the conventional chip pad, generation of the stress is further suppressed, and increased resistance is exhibited against the reflow cracks.

FIGS. 25 to 34 illustrate further embodiments. Referring to FIG. 25, the chip pad is tapered in the direction of the thickness thereof as designated at 23 to more reliably prevent propensity for the plastic from swelling beyond the chip pad. Referring to FIG. 26, a groove 19 is formed to surround the adhesive-mounting in the island portion 1a to prevent the adhesive from flowing out. The groove should have a size of, for example, about 0.2 mm in width and 0.2 mm in depth.

Referring to FIGS. 27 and 28, a step 24 of a height δ is provided between the surface of the chip support island portion 1a and the surface of the adhesive-mounting outer peripheral portion 1b. This makes it possible to minimize the gap between the chip and the chip support outer peripheral portion 1b. The height δ should be from about 10 μm to about 50 μm.

Referring to FIGS. 29 and 30, a dent 25 is formed in a portion of the chip support outer peripheral portion 1b for supporting the chip, to facilitate the positioning of the chip.

With reference to FIGS. 31 and 32, the lead of the adhesive-mounting island portion 1a has a thickness 26 smaller than the thickness of the support portion 1b. This makes it possible to further decrease the stress that generates in the chip.

With reference to FIGS. 33 and 34, there are provided two chip mounting island portions 1a. In this way, the chip-mounting island portions 1a may be provided in a plural number as required.

The aforementioned embodiments may be put into practice individually or in suitable combinations.

According to the aforementioned embodiments, only a central portion of the chip is joined in die-bonding the chip and bonded to the chip pad together . Therefore, the stress that is generated in the chip as a result of the die bonding or as a result of the subsequent temperature aging is suppressed, and the chip is prevented from breaking.

Since the plastic is charged into a through hole formed in the chip pad to form a protrusion of the plastic, there develops no relative slippage in the adhering portion between the plastic and the chip pad of on the side thereof opposite to the chip. Therefore, the plastic stress that would otherwise result at the lower edge of the chip pad decreases significantly, and so that the life of the device increases greatly against the temperature cycle.

Furthermore, since side surfaces an inner peripheral surface of the through hole formed in the chip pad prevent the plastic from swelling despite the vapor pressure at the time of reflow soldering, the resistance increases greatly against the reflow cracks.

Claims

1. In a lead frame comprising a unitary structure of a chip pad for mounting a semiconductor chip on a chip-mounting surface thereof and a group of chip pad supporting leads connected to said chip pad along said chip pad , the improvement wherein a through hole is formed in at least a portion of said chip pad, said through hole being projected in a direction which having an inner peripheral surface at least a part of which is tilted relative to a direction from normal to the plane of the chip-mounting surface of said chip pad.

2. A lead frame according to claim 1, wherein said through hole in its entirety is tilted relative to a direction of thickness of said chip pad.

3. A lead frame according to claim 1, wherein said through hole is characterized as having a relatively narrower opening within the chip pad itself than at either the chip-mounting surface through hole opening end or at the through hole opening end at an opposing surface thereof.

4. A lead frame according to claim 1, wherein said through hole has an area on opening end in the chip-mounting surface of said chip pad that lies over a range of from 24% of the area of the chip-mounting surface of the entire chip pad itself to , said opening end being of an area less than 80% of the actual chip-mounting surface area required of said chip pad to which for said semiconductor chip is to be adhered to thereto, and said through hole has a minimum opening area greater than 24% of the area of said chip-mounting surface.

5. A lead frame according to claim 1, wherein a groove is formed in the chip-mounting surface of said chip pad to surround the through hole.

6. In a lead frame comprising a unitary structure of a chip pad for mounting a semiconductor chip on a chip-mounting surface thereof, and a group of chip supporting leads connected to said chip pad along said chip pad , the improvement wherein a through hole is formed in at least a portion of said chip pad, said through hole having an a first opening on end in the chip-mounting surface of said chip pad that is , said first opening end being greater in area than the area corresponding to an a second opening thereof on end of said through hole in a surface of said chip pad opposing opposite to the chip-mounting surface thereof.

7. A lead frame according to claim 6, wherein the area of said first opening end of said through hole corresponding to an opening on in the chip-mounting surface of said chip pad lies over a range of from 24% of the chip-mounting surface of the entire chip pad itself to is less than 80% of the actual chip-mounting surface area required of said chip pad to which for said semiconductor chip is to be adhered to thereto, and the area of said second opening end is greater than 24% of the area of said chip-mounting surface.

8. A lead frame according to claim 6, wherein a groove is formed in the chip-mounting surface of said chip pad to surround the through hole.

9. In a semiconductor device comprising a semiconductor chip, a chip pad having a chip-mounting surface for mounting said semiconductor chip, a group of leads electrically connected to said chip pad as a unitary structure along said chip pad, and having inner leads disposed within said group of leads ends, and a plastic portion for sealing the semiconductor chip, said chip pad and said inner leads, the improvement wherein a through hole is formed in at least a portion of said chip pad, said through hole being projected in a direction having an inner peripheral surface at least a part of which is tilted relative to a direction from normal to the plane of the chip-mounting surface of said chip pad.

10. A semiconductor device according to claim 9, wherein said through hole in its entirety is angularly tilted with respect to the direction of thickness of said chip pad.

11. A semiconductor device according to claim 9, wherein said through hole is characterized as having a relatively narrower opening within the thickness of the chip pad itself than at either the chip-mounting surface through hole opening end or at the through hole opening end at an opposing surface thereof.

12. A semiconductor device according to claim 9, wherein said through hole has an opening on end in the chip-mounting surface of said chip pad, said opening end being of an area that is greater than the area of an opening end of said through-hole on in the surface of said chip pad opposing opposite to the chip-mounting surface thereof.

13. A semiconductor device according to claim 9, wherein said through hole has an area on a first opening end in the chip-mounting surface of said chip pad that lies over a range of from 24% of the chip-mounting surface of the entire chip pad itself to , said first opening end being of an area smaller than 80% of the actual chip-mounting surface area required of said chip pad to which for said semiconductor chip is to be adhered to thereto, and said through hole has a second opening end disposed in the surface of said chip pad opposite to said chip-mounting surface and having an area greater than 24