An electrochemical etching step in a semiconductor device fabrication process increases the radius of curvature of edges of metal lines deposited on the semiconductor device. The metal lines are fabricated by forming a mask, electrodepositing the metal, and removing the mask, and the electro-chemical etching step in performed subsequently. The increased radius of curvature of the metal lines simplifies subsequent planarization and decreases line-to-line capacitance, thereby enhancing device performance. In an apparatus for performing the fabrication process, wires sown into a gasket which secures the semiconductor wafer and prevents electrolyte leakage, allows the gasket to function also as a component of the cathode. A more uniform metal deposition is created by a virtual anode, i.e., a metal plate having an aperture and being located between the anode and the cathode.
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3. An apparatus for electrodeposition of metal onto a semiconductor having an electrically conducting layer, comprising:
an anode, a cathode wire, a cell body, a anode gasket for sealing said anode to said cell body adapted to prevent leakage of an electrolyte, a cathode gasket for sealing said semiconductor to said cell body adapted to prevent leakage of said electrolyte and providing contact between said cathode wire and said electrically conducting layer, means for securing said semiconductor to said cathode gasket to exclude said electrolyte from contacting said cathode wire, means for exposing a selected area of said semiconductor to said electrolyte, a virtual anode located between said anode and said electrically conducting layer for creating a more uniform current distribution to said electrically conducting layer, and a virtual anode gasket for sealing said virtual anode to said cell body to adapted to prevent leakage of said electrolyte.
1. Apparatus for electrodeposition of a conducting metal onto a semiconductor, said apparatus comprising:
diffusion barrier deposition process means to provide a diffusion barrier layer on said semiconductor having contacts and vias, and to prevent metal diffusion into said semiconductor, an electrically conducting nucleation layer deposition process means to provide an electrically conducting nucleation layer on said diffusion barrier layer and a sufficient adhesion surface for electrodeposition of said metal, inert metal mask process means to place a first metal mask layer onto said nucleation layer, selective electrodeposition process means to selectively electrodeposit said metal onto said nucleation layer while simultaneously completely filling a contact or via, electrochemical etching means to increase a radius of curvature of edges of said metal, thereby facilitating planarization and decreasing line-to-line capacitance, and a virtual anode disposed between a cathode and an anode for improving primary current distribution to improve uniformity in a thickness of said metal electrodeposited on said semiconductor.
2. The apparatus as in
0. 4. The apparatus of
0. 5. The apparatus of
0. 6. The apparatus of
0. 7. The apparatus of
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The present application is
Reference will now be made in detail to the preferred embodiment of the invention, in example of which is illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiment, it will be understood that it is not intended to limit the invention to that embodiment. On the contrary, it is intended to cover alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
In this process, deposition of metal (copper for instance) occurs by the electrolysis of a copper ion containing aqueous electrolyte. The physical laws governing this reaction were explained by Faraday in 1833. Simply stated, by passing 96,487 coulombs (an electrical unit of charge) through the two electrodes immersed in the electrolyte, one gram-equivalent of metal is stripped from the anode and deposited on the cathode.
When a direct current (DC) voltage is imposed on the two electrodes, electrons travel from the voltage source into the cathode and out of the anode into the voltage source.
Positive copper ions are attracted to the cathode where they combine with electrons yielding neutral copper which is plated onto the electrode.
At the anode, electrons are removed from the copper which releases soluble copper ions into the solution.
The rate of the cathode reaction is exactly the same as the anode reaction rate, for each copper ion dissolved from the anode, one is plated onto the cathode.
Modifications of this simple procedure are done to improve certain properties of the electrodeposited film. Other ionic species can be added to the electrolyte (sulfuric acid) to improve its conductivity which affects thickness uniformity. Small quantities of additives can modify the film morphology, change the film stress and improve the step coverage. How the voltage or current is applied, temperature, fluid dynamics and cell geometry are other relevant variables.
By using a photoresist patterned wafer for the cathode, metal can be selectively deposited. The wafer will only have plated metal where the resist is not present, electrodeposition cannot occur on the (electrically insulating) photoresist covered areas. The result is a patterned metal layer from the pair of photolithographic and deposition steps compared to the standard deposition, photolithographic and etch steps. This fact has favorable implications in terms of processing complexity and economic considerations (easier and cheaper).
One of the complexities of the process flow according to the present invention is to selectively form a metal line while simultaneously filling a contact or via. Selective line formation process has been previously documented (see the list of references on selective gold plating). The contact or via must be filled with excellent step coverage, a void cannot be tolerated during this step (FIG. 1A). If a void forms (FIG. 1B), it would be filled with electrolyte which could lead to reliability problems due to corrosion or explosion upon heating due to the conversion of the liquid to a gas. This is not a concern with LPCVD because a void would be filled with a gas, not a liquid. This gas would not contribute to corrosion or cause any explosion mechanisms to occur.
The use of an additive (TECHNI-COPPER U additive form Technics Inc.) is one which could be used to allow the step coverage problem to be overcome. The additive promotes what is referred to as micro-levelling in the printed circuit board industry. Micro-levelling is a phenomenon which promotes the growth rate of depressed areas (scratches or surface anomalies in the printed circuit board industry or contacts in this application) and hinders the growth of raised area (flat metal surface or the top perimeter of contacts in this application), it levels the surface.
Micro-levelling also refers to a scale much smaller than lines or vias on printed circuit boards, more similar to the geometries encountered in semiconductor processing. It was developed to promote a smooth metal surface despite the roughness of the substrate. it saves processing time by eliminating a polishing, step. When micro-levelling occurs, contacts or vias are filled at a faster rate than the surrounding flat metal areas yielding excellent step coverage (no voids), the contact or via fills up with metal before the metal line is completely formed.
Geometric-leveling (the ability to fill a contact or via by obtaining equal deposition rates from all exposed surfaces hence filling a void, often characterized as 100% step coverage in a LPCVD process) and a control of the deposition conditions (no mass transport limitation of the metal ions) also contribute to the excellent step coverage properties of this process. The result is step coverage in excess of 100%, something not able to be done with LPCVD techniques. In summary, the use of micro-levelling agents, geometric levelling and the control of the mass transport properties during electrodeposition allow the simultaneous filling of contacts or vias or well as photoresist defined metal lines. The results are metal lines with completely filled contacts or vias and no voids, formed without the aid of plasma metal etching.
improved device performance (less time delay and smaller IR voltage drop) due to lower metal resistance for a given thickness compared to higher resistivity metals
excellent thermal conduction allows possibility of heat-sink metal layer
economical process allows possibility of thin ground plane metal layers
selective metal electrodeposition simplifies the small geometry metal etch step
improved and simplified metal linewidth control
decreased line-to-line capacitance
simplified planarization processing
simplified room temperature process compared to elevated temperature processes
potential simplification of packaging due to TAB process compatibility with copper and soldering
simplified planarization processing following metallization due to the reduced metal thickness for a given resistance compared to higher resistivity metals
simplified task of increasing the number of metal layers because of the simplified planarization processing
potential economic and throughput advantages compared to present and proposed metallization schemes
potential environmental advantages due to efficient use of recyclable electrolyte compared to LPCVD and metal etch gases and their by-products.
As with any advanced semiconductor process, integration of the new step into the overall process flow requires as much engineering attention as the new step itself. Some older steps are deleted (such as aluminum sputtering in this instance), some are left unchanged (contact etch), some slightly modified (second dielectric deposition) and some new steps added (adhesion layer deposition).
Following is a general description of the relevant part of a silicon process flow using selective metal electrodeposition. Table II is a schematic of that process flow. It utilizes the selective metal electrodeposition process according to the present invention for the first metal layer (most process flows use at least two metal layers). It would be essentially unchanged for second (or third) metal applications.
Cross sections of a typical wafer surface are shown in
Processing up to and including first dielectric contact etch is shown in
An optional platinum silicide Schottky Diode formation step may then be done. This would form a thin silicide at the bottom of the contacts.
The next step is the diffusion barrier deposition process. This layer has two functions. The first is to provide an electrically conducting layer to allow uniform metal electrodeposition across the entire wafer surface. The second is to prevent any interaction of the electrodeposited metal (copper for instance) with the silicon at the bottom of the contacts or the dielectric oxide. If silver was to be used instead of copper, the diffusion barrier would not need to prevent interaction with the silicon due to the inactivity of silver with silicon. A typical process would include titanium sputter deposition followed by rapid thermal nitridation in nitrogen or ammonia. Excellent ohmic contact is made to the active device while titanium nitride forms on the top surface.
Any other diffusion barrier process which forms good ohmic contact to the silicon, does not degrade the metal resistivity by alloying and inhibits species in the metallization layer from interacting with the silicon at the bottom of the contact or under the first dielectric (reactive sputtered TiN, LPCVD, TiN, reactive sputtered TiW+N, rapid thermal nitridation of TiW . . . ) may be utilized for the diffusion barrier process. The diffusion barrier must also be compatible with present etching technology. The thickness of this layer depends on several variables such as step coverage, diffusion barrier properties end metallization composition with a typical value being 1000A.
The next step is the nucleation layer deposition process (FIG. 3). F is the diffusion barrier end nucleation layer. Platinum is sputtered on top of the diffusion barrier.
This process must provide excellent ohmic contact to the diffusion barrier, provide an excellent nucleating surface for the electrodeposited metal, not adversely react with the electrodeposited metal to ruin its excellent resistivity (by forming alloys), be compatible with present etching technology end be chemically inert to the following masking steps. Other nobel metals, such as platinum, iridium, osmium, or palladium, are also candidates for the nucleation layer. The thickness depends on the step coverage into the recesses of the contacts or vias.
Because only several monolayers are required for good-nucleation properties, a thickness of only 250A has been successfully used. If the surface of the diffusion barrier can be treated so that it provides e proper nucleating surface, the nucleation deposition step may be deleted. Chemical etching or e chemical exchange reaction are two possible techniques to achieve this process simplification.
The first metal mask process follows. Photoresist spin (
Various bake steps are usually performed during the masking process to optimize specific photoresist properties. Those relating to improving the etch selectivity or the etch profile are not necessary with this process flow since the resist is never subjected to e plasma etch process (no etching of the electrodeposited metal is performed). An additional complexity compared to standard processing is that resist is now present at the bottom of contacts and vias, something that does not occur when the mask follows metal deposition.
It is essential that the develop step completely remove this resist to ensure good ohmic contact of the selective electrodeposited metal to the nucleation layer/diffusion barrier.
Selective metal electrodeposition follows (FIG. 6). H is the electrodeposited metal. This process step uses the hardware described below and shown in
Photoresist removal is the next step (FIG. 7). Plasma or wet photoresist strip can be utilized. It must not significantly attack the selectivity deposited metal, the nucleating layer or the diffusion barrier.
The electrochemical metal etch step can be done next. By reversing the direction of the electrodeposition current, metal ions leave the electrodeposited metal H predominantly at the edges and corners of the metal lines H where the electric filed is strongest, thereby increasing the radius of curvature of the edges and corners (FIG. 7b). Advantages include simplified planarization processing and decreased line to line capacitance (a device performance enhancement).
The nucleation layer and diffusion barrier blanket etch step is next (FIG. 8). Plasma or wet etching techniques may be used. The process must not etch or undercut the electrodeposited metal or etch the underlying dielectric. A typical process would wet etch the platinum (the titanium nitride and electrodeposited metal would be inert in this aqueous solution) end dry etch the remaining titanium nitride (the oxide and electrodeposited metal would not etch significantly in this plasma process).
The second dielectric deposition process follows. A thin silicon nitride layer (approximately 500A) is deposited followed by whatever silicon dioxide is required for second layer dielectric planarization. Planarization of this layer would proceed similarly to standard processing. The nitride acts as diffusion barrier and adhesion layer to the electrodeposited metal (copper or silver).
This complexity (compared to standard processing) is proposed because copper and silver are known to diffuse rapidly in silicon dioxide as well as exhibit poor adhesion properties to silicon dioxide. For non-volatile memory applications, the silicon nitride must also be UV transparent. This may be achieved by properly controlling the deposition conditions to yield the proper composition and stoichiometry.
The second dielectric via mask and etch steps are next. The via etch process will have to be slightly modified (compared to standard processing of silicon dioxide dielectrics) to properly etch the thin silicon nitride present at the bottom of the vias. Selectivity of the etch to the electrodeposited metal must be high, similar to that of presently used metals such as aluminum.
An alternative to the above process flow inserts a selective tungsten plug process after contact etch and preceding diffusion barrier deposition. This essentially creates a flat surface for metallization.
This alternative process flow has the advantage of not requiring the selective metal deposition step to have good step coverage properties into contacts or vias. The metal resistivity is that of the electrodeposited metal, a distinct advantage. Disadvantage include higher costs and slower throughput due to the tungsten step. No aluminum is involved so electromigration concerns are minimized.
Another potential disadvantage is the concern that selective tungsten plugs may cause Junction leakage when applied to a first metal process.
In
References in the printed circuit board literature imply that there is an optimum anode current density utilizing the acid copper bath for proper anode passivation. This will depend on the exposed area of the wafer (area without photoresist) as well as the deposition current density. This may not prove to be as important a parameter with this process due to the thinner nature of the deposited layer compared to printed circuit board application thicknesses (0.5 microns compared to 25 microns).
Masking part of the anode could, be used to decrease the area of the anode exposed to the electrolyte if a specific (larger) anode current density is necessary.
The anode gasket 2 seals the anode to the cell body 10 preventing leakage of the electrolyte. This gasket must be inert with respect to the electrolyte. For acid copper plating, Viton or PTFE (teflon) materials are excellent choices. Other electrolyte and metal systems must be addressed accordingly. The anode 1 is secured firmly to the anode gasket 2. Since the anode is not changed for a multitude of wafers, it is secured in a permanent manner to the cell (using clamps or bolts).
The cathode gasket 3 has the same inertness requirements as the anode gasket 2. Its function is to seal the cathode to the cell and prevent electrolyte leakage.
Cathode wires 4 (A,B,C and D) are sewn into cathode gasket 3 as shown in FIG. 10A. In order to maximize the exposed area of wafer 5 to the electrolyte, the cathode gasket 3 is not round, it follows the circumference of the wafer which has flat regions oriented with specific crystallographic orientations.
By matching the shape of the gasket to the wafer, a uniform displacement of the cathode wires 4 from the edge of the wafer is achieved while preventing electrolyte leakage between cathode gasket 3 and wafer 5 due to water flats. Obviously, the wafer must be properly oriented when placed on wafer gasket 3.
Referring back to
This concept may be extended to include even more cathode wires if desired. After this check has been made, all cathode wires 4 (A,B,C and D) are connected to together to act as a single cathode wire making multiple contacts to the wafer 5.
The wafer is the cathode 5 with the active side facing the cathode gasket 3 (the side with photoresist and nucleation layer metal shown in FIG. 5). The area of the cathode 5 encircled by the cathode gasket 3 is exposed to the electrolyte. The fraction of this area that is not covered by photoresist (exposed nucleation layer metal) is the actual plating area. The edge of the cathode 5 in contact with the cathode gasket 3 and the back of the wafer are not exposed to the electrolyte. Neither are the cathode wires 4 that are woven into the cathode gasket 3.
Wafer clamp 6 applies pressure to the back of the cathode 5 to secure the wafer firmly against the cathode gasket 3 and make good contact to cathode wires 4. If must seal the cathode, 5 well enough to prevent electrolyte from leaking between the cathode 5 and cathode gasket 3 and the cathode gasket 3 and cell body 10. This will also ensure that cathode wires 4 do not contact the electrolyte.
Its configuration must be such that it is compatible with moving wafers on and off the cathode gasket 3 with the wafer handling apparatus. Another requirement of the wafer clamp 6 is that it apply a uniform force to the cathode 5. If any bending (non-uniform) force is applied to the wafer, this extrinsic stress will be added to the intrinsic stress of the electrodeposited metal. The probable result will be undesirable and non-uniform stress in the metal layer. A more desirable approach is to not apply extrinsic stress with wafer clamp 6 and to deposit a low stress film resulting in a metal layer of low and uniform total stress.
The virtual anode 7 is so named due to its manipulation of the cell geometry to create a primary current distribution that does not coincide with the real anode and cathode geometry, but with an anode that approximately coincides with the opening in the virtual anode 7. The advantage of this is that it creates a more uniform primary current distribution which has beneficial consequences on the deposited metal thickness uniformity.
A comparison of the cross-sections of the cells shown in
Alternatively, by using a virtual anode, the acid content of the electrolyte can be decreased if more photoresist inertness is desired without degrading the metal thickness uniformity. Another potential advantage is that a higher current density (growth rate) can be used with a virtual anode to achieve a desired thickness uniformity.
Also, the fluid dynamics of the anode compartment and cathode compartment can be individually optimized. In addition, any particulate generation from the anode can be partially isolated from the cathode compartment by the virtual anode. The size and shape of the virtual anode opening, the wafer size, the nucleating layer/diffusion barrier sheet resistance, the electrolyte conductivity, the anode to virtual anode distance and the cathode to virtual anode distance are manipulated to optimize the uniformity of the primary current distribution.
Virtual anode gaskets 8 seal the virtual anode 7 to the cell body 10 preventing electrolyte leakage. Different virtual anodes can be easily exchanged to optimize the primary current distribution using this configuration.
Electrolyte inlets and outlets 9 establish proper fluid dynamic conditions in the anode compartment and cathode compartment. A single pump and filtration system may feed both compartments, or two separate systems may be employed to optimize each compartment.
The number and geometry of these inlets and outlets are chosen to provide a controlled and uniform electrolyte boundary layer thickness over the entire exposed cathode and anode surfaces. This is critical for achieving proper film properties such as film morphology, stress and step coverage on the cathode as well as establishing a proper passivation layer on the anode.
Filtration of the electrolyte in the anode compartment also needs to be optimized to minimize any particulates (generated by the anodic corrosion process from entering the cathode compartment.
The pump 11, filtration system 12, temperature controller 13, reservoir 14 and fluid tubing 15 complete the cell as shown in FIG. 12. Their function is to provide a clean, constant temperature, controlled flow of electrolyte 16 to the cell, while minimizing any external contamination or evaporation.
The electronics 17 (shown schematically in
The use of a coulometer along with the knowledge of the exposed area of the wafer (area without photoresist) and the coulombic efficiency (very close to 100% with the acid copper process) will allow the average thickness of the film to be monitored during the deposition process, typically impossible with present deposition techniques.
The complete cell and electronics may comprise a part of a total system that includes wafer handling, wafer cleaning, other wafer processing (such as a resist strip) and laminar gas flow. There may also be a multitude of cells and electronics if multiple wafers are to be processed simultaneously to improve throughput.
Table I compares current and proposed metallization processes with the selective metal electrodeposition scheme. Each currently used process has some significant disadvantage when used in an advanced semiconductor process. The present invention has no apparent major disadvantage.
compatibility with present state of the art process flows with respect to economics and performance. Compatible with salicide. Schottky diodes, sub-micron contacts and vias and GaAs processes. It may be employed for first metal or any subsequent metal layer.
this process may be employed to form heat sink layers between active metal layers or as ground plates between metal layers. The possibility or performing both functions simultaneously also exists.
employs a diffusion barrier which conducts electrons to all parts of the cathode surface allowing uniform metal electrodeposition as well as providing a barrier to metal species interfering with properties of the underlying active devices.
uses a nucleation layer for optimum electrodeposition film morphology. This does not hinder device performance while only increasing process completely slightly.
an inverted metal mask is required as compared to present masking technology. The requirement of removing resist from the bottom of contacts or vias to ensure good ohmic contact between the electrodeposited metal and the nucleation layer/diffusion barrier is added. This is a consequence of the mask step proceding the metal deposition instead of following it as is the case with standard metal processing.
improved linewidth control is a result of the resist profile defining the metal linewidth without bias from the standard metal etch step which is essentially eliminated (a blanket nucleation layer/diffusion barrier etch does not significantly affect metal linewidth).
decreased line-to-line capacitance.
simplified planarization processing.
experimental operating conditions:
electrolyte temperature 20°C-25°C C.
12 ounces/gallon of water CuSO4.5H2O
10% by volume concentrated sulfuric acid
50 parts per million (PPM) chloride ion from hydrochloric acid
TECHNI-COPPER U additive 0.4% by volume (this is a product of Technic Inc. P.O. box 965, Providence, R.I. 02901)
a small cell of approximately 42 milliliters with two electrolyte inlets and two electrolyte outlets was employed. The flow rate was approximately 1.5 liters per minute. No virtual anode was employed.
cathode current density of 5 mA/cm2 (DC)
film thickness of 5000A
any other set of above conditions which meet the requirements for metal thickness uniformity, film morphology, film resistivity, step coverage and throughput will also be acceptable.
the control of micro-levelling, geometric levelling and mass transport conditions allows the formation of a metal line with void-free contacts or vias in a single deposition step (step coverage in excess in 100%).
An alternative process flow utilizing selective tungsten plugs removes the requirement for excellent step coverage of the selective metal electrodeposition process while keeping the advantages of low resistivity metal and no electromigration concerns.
The standard metal etch step is much simplified to a blanket etch step only having to remove the nucleation layer and diffusion barrier between electrodeposited metal areas. No plasma etching of the electrodeposited metal is required.
a modified second dielectric deposition process is employed to avoid complications due to the rapid diffusion of copper or silver in silicon dioxide and adhesion complexities. A slight modification of the second dielectric via etch process will also have to be made to compensate for the (thin) silicon nitride at the bottom of the vias.
system allows execution of selective metal electrodeposition process in a semiconductor wafer process flow meeting all future metallization requirements while providing economical and reliable alternatively to presently considered processes.
system prevents electrolyte from contacting back surface of wafer (cathode) as well as cathode wires due to unique cathode gasket and cathode wire configuration.
Wafer is secured against cathode gasket in a uniform manner preventing complications from added extrinsic stress.
system is sealed and minimizes external contamination electrolyte and evaporation.
the virtual anode improves the primary current distribution improving the metal thickness uniformity while allowing process variables to be optimized for other electrodeposited film properties (film morphology, stress and step coverage). It also allows independent optimization of the fluid dynamic conditions in the cathode compartment and the anode compartment. It allows the possible particulate generation problem from the anode to be minimized as well.
virtual anode gaskets prevent electrolyte leakage and make it a simple and rapid process to change the geometry of the virtual anode. This is done to optimize the primary current distribution for different diffusion barrier sheet resistances and electrolyte compositions.
the electrolyte inlets and outlets along with the cell geometry, pump, pumping rate and electrolyte tubing establish the proper fluid dynamic conditions for uniform diffusion layers on the anode and cathode. This is essential for achieving uniform and reproducible electrodeposited film properties and a property passivated anode.
the associated electronics applies the desired potential or current, measures cell potentials, currents and charge. It provides the unique features of allowing the average film thickness to be measured during the deposition process.
this described cell is part of a system that incorporates wafer handling and other components common to semiconductor processing equipment (laminar flow, computer for human interfacing . . . ).
| TABLE I | |||||
| COMPARISON OF PRESENT AND PROPOSED | |||||
| METALLIZATION PROCESSES | |||||
| RESIST- | |||||
| IVITY | STEP | ||||
| (micro- | COVER- | ECON- | THROUGH- | RELIA- | |
| PROCESS | ohm-cm) | AGE | OMICS | PUT | BILITY |
| sputtered | good | poor | good | good | fair |
| aluminum | 3.0 | ||||
| LPCVD | good | excellent | fair | fair | fair |
| aluminum | 3.0 | ||||
| hot | good | good | fair | fair | fair |
| aluminum | 3.0 | ||||
| reflowed | good | good | fair | fair | fair |
| aluminum | 3.0 | ||||
| LPCVD | fair | excellent | fair | fair | excellent |
| W | 8.0 | ||||
| W plugs/ | good | excellent | fair | fair | fair |
| aluminum | 3.0 | ||||
| SELEC- | excellent | excellent | excellent | excellent | excellent |
| TIVE | 2.0 | ||||
| COPPER | |||||
| TABLE I | |||||
| COMPARISON OF PRESENT AND PROPOSED | |||||
| METALLIZATION PROCESSES | |||||
| RESIST- | |||||
| IVITY | STEP | ||||
| (micro- | COVER- | ECON- | THROUGH- | RELIA- | |
| PROCESS | ohm-cm) | AGE | OMICS | PUT | BILITY |
| sputtered | good | poor | good | good | fair |
| aluminum | 3.0 | ||||
| LPCVD | good | excellent | fair | fair | fair |
| aluminum | 3.0 | ||||
| hot | good | good | fair | fair | fair |
| aluminum | 3.0 | ||||
| reflowed | good | good | fair | fair | fair |
| aluminum | 3.0 | ||||
| LPCVD | fair | excellent | fair | fair | excellent |
| W | 8.0 | ||||
| W plugs/ | good | excellent | fair | fair | fair |
| aluminum | 3.0 | ||||
| SELEC- | excellent | excellent | excellent | excellent | excellent |
| TIVE | 2.0 | ||||
| COPPER | |||||
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