Final testing of an lcd panel or the like is performed after preliminary testing for short circuit defects. During final testing, the panel is exposed to signals at the shorting bars and the resulting display pattern is imaged. The resulting image data then is processed at a computer system to determine whether the resulting display pattern differs from an expected display pattern. If differences are present then an open circuit or pixel defect is present. The applied test signals and the pattern or differences determine the type of defect present. For an open circuit defect along a gate line, a partial row (column) of the resulting display pattern does not activate. For an open circuit along a drive line, a partial column (row) of the resulting display does not activate. Pixel shorts are identified by applying test signals to the shorting bars during a first test cycle, then imaging the display during a second test cycle after at least one of the test signals is removed. Pixels which remain active that should be inactive have short circuit defects.
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1. A method for testing an lcd panel having a plurality of drive lines oriented in a first direction and a plurality of gate lines oriented in a second generally orthogonal direction creating row/column intersections, each drive line which terminates along a first edge of the panel being shorted together by a first shorting means, each gate line which terminates along a second edge of the panel being shorted together by a second shorting means, said method comprising the steps:
applying a first test signal to said first shorting means and a second test signal to said second shorting means to generate a first resulting display pattern; comparing said first resulting display pattern to an expected display pattern, a difference between the resulting display pattern and the expected display pattern signifying that the panel has a defect.
5. An apparatus for testing an lcd panel, the panel having a plurality of drive lines oriented in a first direction and a plurality of gate lines oriented in a second generally orthogonal direction creating row/column intersections, each drive line which terminates along a first edge of the panel being shorted together by a first shorting means, each gate line which terminates along a second edge of the panel being shorted together by a second shorting means, said apparatus comprising:
means for applying a first test signal to said first shorting means and for applying a second test signal to said second shorting means to generate a resulting display pattern; means for imaging the resulting display pattern to generate sensed image data; means for comparing the sensed image data to expected image data, a difference between the sensed image data and the expected image data signifying that the panel has a defect.
3. A method for testing an lcd panel having a plurality of drive lines oriented in a first direction and a plurality of gate lines oriented in a second generally orthogonal direction creating row/column intersections, each drive line which terminates along a first edge of the panel being shorted together by a first shorting means, each drive line which terminates along a second opposing edge of the panel being shorted together by a second first shorting means, each gate line which terminates along a third edge of the panel being shorted together by a third shorting means, each gate line which terminates along a fourth edge of the panel being shorted together by a fourth shorting means, said method comprising the steps:
applying a first test signal to said first shorting means, a second test signal to said second shorting means, a third test signal to said third shorting means and a fourth test signal to said fourth shorting means to generate a resulting display pattern; comparing said resulting display pattern to an expected display pattern, a difference between the resulting display pattern and the expected display pattern signifying that the panel has a defect.
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This invention is related to commonly-assigned U.S. patent application Ser. No. 07/557,257, filed July 24, 1990 of the same inventor for METHOD AND APPARATUS FOR TESTING AN LCD PANEL ARRAY USING A MAGNETIC FIELD SENSOR.
This invention relates to testing of liquid crystal display (LCD) panel arrays, and more particularly to a method and apparatus for testing LCD panel arrays for open circuit and pixel defects by applying test signals to panel shorting bars.
LCD panels typically are formed with a liquid crystal material sandwiched between an active plate and a ground plate. Polarizers, colorizing filters and spacers also are included between the plates. During fabrication, many active
Referring to
During final testing of the LCD panel 10, the electro-static discharge shorting bars are present. As shown in
For a high density monochrome LCD panel, the pixel array includes 640×480 pixels (307,200 pixels). Each pixel corresponds to a single array element. By controlling the voltage levels of the test signals applied to shorting bars, the pixels are driven to correspond to white, black, or various gray levels in between.
For a high density RGB color panel there are three pixels for every one pixel of the monochrome panel. Thus, the RGB panel array includes 640×480×3 pixels (921,600 pixels). By activating a combination of the three pixels alternative colors are achieved for an array element. By activating all three pixels, a white color is achieved. According to one embodiment of an RGB interdigitated panel, each color pixel corresponds to a separate element. Thus, the drive lines for the red, blue and green pixels are connected to alternating shorting bars (28, 32), while the gate lines are also connected to alternate shorting bars (30,34).
Referring to
Referring to
Upon completion of preliminary short circuit testing, the open circuit testing procedure is performed.
To identify whether panel 10 has any open circuit or pixel defects, respective test signals are applied to shorting bars 28, 30, 32, 34. Under normal operation, a pixel 12 is addressed by applying an active signal to the gate line 16 and drive line 14 connected to the drive element 18 of the pixel 12. However, during testing the shorting bars 28, 30, 32, 34 are connected to respective pluralities of drive lines or gate lines. As a result, individual pixels 12 can not be addressed. For an interdigitated panel a combination of four test signals are applied to generate an expected display pattern.
Table A below lists a set of test signal combinations, along with descriptions of the expected display pattern corresponding to such test signals:
TABLE A | |||||
FIG. | SB-28 | SB-30 | SB-32 | SB-34 | Expected Display |
4a | Black | On | Black | On | All pixels off |
4b | White | On | White | On | All pixels on |
4c | White | On | Black | On | Horizontal Stripes |
4d | Black | On | White | On | Inverse Horizontal |
Stripes | |||||
4e | White | Off | White | On | Vertical Stripes |
4f | White | On | White | Off | Inverse Vertical Stripes |
4g | White | On | Black | Off | Checkerboard Cycle 1 |
4h | Black | Off | White | On | Checkerboard Cycle 2 |
4i | White | Off | Black | On | Inverse Checkerboard |
Cy. 1 | |||||
4j | Black | On | White | Off | Inverse Checkerboard |
Cy. 2 | |||||
SB-28, SB-30, SB-32, and SB-34 correspond respectively to shorting bars 28, 30, 32 and 34. The test signals which are applied to the shorting bars 28, 32 are referred to as being "White" (e.g., logic high; active) or "Black" (e.g., logic low; inactive). The test signals which are applied to the shorting bars 30, 34 are referred to as being "On" (e.g., logic high; active) or "Off" (e.g., logic low; inactive). For achieving a gray level in a monochrome panel, intermediate voltage levels between those for black and white are applied to the drive line shorting bars 28, 32.
For an interdigitated monochrome panel, the striped and checkerboard expected display pattern of
According to the pixel short circuit testing procedure, short circuits in the drive elements 18 and in the pixel elements 12 are detected. Each drive element 18, according to a preferred embodiment of the panel 10, is an FET transistor having a gate, a source and a drain. The gate is coupled to a gate line 16. The source is coupled to a drive line 14. The drain is coupled to a pixel 12. Testing for cross shorts from gate to source is performed during preliminary short circuit testing. Testing for short circuits from gate to drain is done during either preliminary short circuit testing or final open circuit and pixel defect testing.
To detect a short circuit across the gate and drain of a drive element 18, test signals are applied, for generating the all dark display pattern of FIG. 4a. If any pixels 12 become active while such test signals are applied there is a short circuit defect at the drive element 18 of the active pixel 12.
To test for a short circuit in the pixel 12 itself, test signals are applied during a first cycle which correspond to the fully active (e.g. all white) display pattern of FIG. 4b. Next, during a second test cycle, the test signals at shorting bars 30, 34 are switched off. If any pixels remain active, then such pixels have a short circuit defect.
To test for open circuit defects, one or more of the test signal combinations in Table A (other than the "all pixels off" test signal combination) are applied to the shorting bars 28, 30, 32, 34 to generate a resulting display pattern. If an open circuit defect is present, the resulting display varies from the corresponding expected display pattern. For example, an open circuit along a drive line 14 causes all pixels 12 coupled to the drive line 14 beyond the open circuit not to be activated. As a result, for a fully active expected display pattern (FIG. 4b), a line segment of inactive pixels 12 appears where active pixels 12 should appear.
According to alternative embodiments, test signals are applied to the shorting bars 28, 30, 32, 34 in one or more of the combinations listed in Table A. According to a preferred embodiment, test signals are applied corresponding to the expected display pattern of
For both open circuit testing and pixel defect testing, a resulting display pattern corresponds to an expected display pattern when there are no defects present. If however, the resulting display pattern does not correspond to the expected display pattern, then a defect is present.
According to a preferred embodiment, the resulting display is imaged at TV camera 39 and sent to the computer system 37 for processing. Typically, the TV camera 39 generates analog video signals. The analog signals are then converted to digital image signals by an Analog to Digital converter (not shown) at either the camera 39, the computer system 37 or between the camera 39 and the computer system 37. The digital sensed image data then is processed at computer system 37 by comparing the sensed image data to expected image data. The expected image data is determined according to the expected display pattern.
A resulting display pattern is imaged by the TV camera 39 while test signals are applied to the shorting bars 28, 30, 32 and 34. Resulting image signals are converted to digital image data, then processed and stored at the computer system 37. The computer 37 processes the sensed image data to determine whether the resulting display pattern corresponds to the expected display pattern. The computer 37 identifies which sensed image data differs from the expected image data to locate the differences between the resulting and the expected display patterns.
According to one example, three different tests are performed. First, test signals are applied corresponding to the all dark pattern of FIG. 4a. Any differences from the expected display correspond to short circuit pixel drive elements. Second, test signals are applied corresponding to the all active expected display pattern of FIG. 4b. Any differences from the expected display pattern correspond to an open circuit drive line, gate line, or pixel depending on the pattern of the differences. Third, a two cycle test in which test signals are applied corresponding to the all active expected display pattern of
Other tests also may be performed in which test signals corresponding to other expected display patterns (i.e., those in
The TV camera 39 or other optical sensing instrument used to image the resulting display pattern, in effect, scans the panel array 10 or a portion of the panel array 10. The TV camera 39 resolution or digital sampling may correspond to the panel pixels on a one to one basis or on an `n` to one basis where `n` is greater than one. Typically, a group of sensed image data corresponds to one pixel. Thus, a group size for the sensed image data may be one (e.g., one memory data item per pixel) or larger (e.g., several memory data items per pixel). For a grouping of several data items per pixel, all the data items corresponding to one pixel are summed to generate a value corresponding to the luminous intensity of the pixel. Each intensity sums is compared to specification limits for the LCD panel array according to whether the test signals applied correspond a dark pixel, a white pixel or some intermediate gray level pixel. Accordingly, gray scale testing also may be performed as part of the comparison with the expected display pattern data. For a color panel, not only the intensity, but the color of each pixel also is compared.
Although a preferred embodiment of the invention has been illustrated and described, various alternatives, modifications and equivalents may be used. For example, although a TV camera 39 is described as the apparatus for imaging the display panel, a video camera, line-scan camera or other optical sensing instrument may used instead. Therefore, the foregoing description should not be taken as limiting the scope of the invention which is defined by the appended claims.
Henley, Francois J., Barton, Stephen
Patent | Priority | Assignee | Title |
10733923, | Dec 16 2016 | HKC CORPORATION LIMITED; CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO , LTD | Display panel test detection method and device for storing a picture for detection in a source driver circuit board |
6987400, | May 20 2003 | Panelvision Technologies | Testing flat panel display plates using high frequency AC signals |
7145539, | Sep 30 2000 | LG DISPLAY CO , LTD | Liquid crystal display device and method of testing the same |
7259865, | Sep 27 2004 | SNAPTRACK, INC | Process control monitors for interferometric modulators |
7289256, | Sep 27 2004 | SNAPTRACK, INC | Electrical characterization of interferometric modulators |
7299681, | Sep 27 2004 | SNAPTRACK, INC | Method and system for detecting leak in electronic devices |
7343080, | Sep 27 2004 | SNAPTRACK, INC | System and method of testing humidity in a sealed MEMS device |
7359066, | Sep 27 2004 | SNAPTRACK, INC | Electro-optical measurement of hysteresis in interferometric modulators |
7369252, | Sep 27 2004 | SNAPTRACK, INC | Process control monitors for interferometric modulators |
7388704, | Jun 30 2006 | SNAPTRACK, INC | Determination of interferometric modulator mirror curvature and airgap variation using digital photographs |
7403323, | Sep 27 2004 | SNAPTRACK, INC | Process control monitors for interferometric modulators |
7415186, | Sep 27 2004 | SNAPTRACK, INC | Methods for visually inspecting interferometric modulators for defects |
7417735, | Sep 27 2004 | SNAPTRACK, INC | Systems and methods for measuring color and contrast in specular reflective devices |
7453579, | Sep 27 2004 | SNAPTRACK, INC | Measurement of the dynamic characteristics of interferometric modulators |
7545556, | Dec 21 2006 | SNAPTRACK, INC | Method and apparatus for measuring the force of stiction of a membrane in a MEMS device |
7570865, | Sep 27 2004 | SNAPTRACK, INC | System and method of testing humidity in a sealed MEMS device |
7582952, | Feb 21 2006 | SNAPTRACK, INC | Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof |
7618831, | Sep 27 2004 | SNAPTRACK, INC | Method of monitoring the manufacture of interferometric modulators |
7619436, | Jun 10 2005 | SAMSUNG DISPLAY CO , LTD | Display substrate and apparatus and method for testing display panel having the same |
7619810, | May 05 1994 | SNAPTRACK, INC | Systems and methods of testing micro-electromechanical devices |
7623752, | Sep 27 2004 | SNAPTRACK, INC | System and method of testing humidity in a sealed MEMS device |
7636151, | Jan 06 2006 | SNAPTRACK, INC | System and method for providing residual stress test structures |
7688452, | Jun 30 2006 | SNAPTRACK, INC | Determination of interferometric modulator mirror curvature and airgap variation using digital photographs |
7843208, | Jun 10 2005 | SAMSUNG DISPLAY CO , LTD | Display substrate and apparatus and method for testing display panel having the same |
7894076, | Sep 27 2004 | SNAPTRACK, INC | Electro-optical measurement of hysteresis in interferometric modulators |
7941237, | Apr 18 2006 | Multibeam Corporation | Flat panel display substrate testing system |
7955899, | Feb 21 2006 | SNAPTRACK, INC | Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof |
7978953, | Sep 27 2004 | SNAPTRACK, INC | Methods for visually inspecting interferometric modulators for defects |
8319232, | Feb 21 2006 | SNAPTRACK, INC | Method for providing and removing discharging interconnect for chip-on-glass output leads and structures thereof |
8385714, | Sep 27 2004 | SNAPTRACK, INC | Methods for visually inspecting interferometric modulators for defects |
8466858, | Feb 11 2008 | SNAPTRACK, INC | Sensing to determine pixel state in a passively addressed display array |
9035673, | Jan 25 2010 | Xerox Corporation | Method of in-process intralayer yield detection, interlayer shunt detection and correction |
9322707, | Jun 04 2010 | JDI DESIGN AND DEVELOPMENT G K | Method for measuring luminance of light-emitting display panel |
Patent | Priority | Assignee | Title |
4368523, | Dec 20 1979 | Tokyo Shibaura Denki Kabushiki Kaisha | Liquid crystal display device having redundant pairs of address buses |
4507605, | May 17 1982 | TESTAMATIC INCORPORATED | Method and apparatus for electrical and optical inspection and testing of unpopulated printed circuit boards and other like items |
4631576, | Nov 13 1984 | Hazeltine Corporation | Nonuniformity correction system for color CRT display |
4776022, | Apr 09 1985 | AOI INDUSTRIES, INC | System for printed circuit board defect detection |
4819038, | Dec 22 1986 | AU Optronics Corporation | TFT array for liquid crystal displays allowing in-process testing |
4820222, | Dec 31 1986 | LG DISPLAY CO , LTD | Method of manufacturing flat panel backplanes including improved testing and yields thereof and displays made thereby |
4825201, | Oct 01 1985 | Mitsubishi Denki Kabushiki Kaisha | Display device with panels compared to form correction signals |
4870357, | Jun 03 1988 | Apple Inc | LCD error detection system |
4899105, | Sep 02 1987 | Tokyo Electron Limited | Method of testing electrical characteristics of LCD with probe device |
5017755, | Oct 26 1988 | Kabushiki Kaisha Toshiba | Method of repairing liquid crystal display and apparatus using the method |
5034683, | Jul 13 1987 | Hamamatsu Photonics K.K. | Voltage detecting device |
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