An image control device for use in a computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.
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0. 8. A monitor, comprising:
a video memory; a display device; a write controller that controls writing of an image signal into the video memory through a first port of the video memory; a first read controller that controls reading of a first image signal from a second port of the video memory according to a synchronizing signal so that the display device displays a first image based on the first image signal and the synchronizing signal; and a second read controller that controls reading of a second image signal from a third port of the video memory while the first read controller executes the reading of the first image signal.
0. 6. A computer system, comprising:
a video memory; a display device; a write controller that controls writing of an image signal into the video memory through a first port of the video memory; a first read controller that controls reading of a first image signal from a second port of the video memory according to a synchronizing signal so that the display device displays a first image based on the first image signal and the synchronizing signal; and a second read controller that controls reading of a second image signal from a third port of the video memory while the first read controller executes the reading of the first image signal.
0. 7. An image processing device for use in a computer system having a display device, comprising:
a video memory; a write controller that controls writing of an image signal into the video memory through a first port of the video memory; a first read controller that controls reading of a first image signal from a second port of the video memory according to a synchronizing signal so that the display device displays a first image based on the first image signal and the synchronizing signal; and a second read controller that controls reading of a second image signal from a third port of the video memory while the first read controller executes the reading of the first image signal.
0. 5. An image control device for use in a computer system having a video memory and a display device, the image control device comprising:
a write controller that controls writing of an image signal into the video memory through a first port of the video memory; a first read controller that controls reading of a first image signal from a second port of the video memory according to a synchronizing signal so that the display device displays a first image based on the first image signal and the synchronizing signal; and a second read controller that controls reading of a second image signal from a third port of the video memory while the first read controller executes the reading of the first image signal.
3. A computer system comprising:
a microprocessor; a bus coupled to said microprocessor; a video memory coupled to said bus; a display device; write control means coupled to said bus for controlling line writing of an image signal into said memory be supplying a write address to said video memory; first read control means coupled to said video memory and said display device, for controlling the reading of an image signal of a motion picture out of said video memory in synchronism with a synchronizing signal which is supplied to said display device along with said motion picture image signal; and second read control means coupled to said video memory and said bus, for controlling the reading of an image signal out of said video memory while said first read control means executes the reading of said motion picture image signal.
1. An image control device for use in a computer system having a microprocessor, a bus coupled to said microprocessor, a video memory coupled to said bus, and a display device, said image control device comprising:
write control means coupled to said bus for controlling the writing of an image signal into said video memory by supplying a write address to said video memory; and first read control means coupled to said video memory and said display device, for controlling the reading of an image signal of a motion picture out of said video memory in synchronism with a synchronizing signal which is supplied to said display device along with said motion picture image signal; and second read control means coupled to said video memory and said bus, for controlling the reading of an image signal out of said video memory while said first read control means executes the reading of said motion picture image signal.
2. An image control device in accordance with
a first output buffer, coupled to said video memory and said display device, for temporarily storing said motion picture image signal read out of said video memory before transferring said motion picture image signal to said display device; and a second output buffer, coupled to said video memory and said bus, for temporarily storing said image signal read out of said video memory before transferring said image signal to said microprocessor.
4. A computer system in accordance with
a first output buffer, coupled to said video memory and said display device, for temporarily storing said motion picture image signal read out of said memory before transferring said motion picture image signal to said display device; and a second output buffer, coupled to said video memory and said bus, for temporarily storing said image signal read out of said video memory before transferring said image signal to said microprocessor.
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This is a Division of application Ser. No. 08/452,012 filed on May 26, 1995, now U.S. Pat. No. 5,680,178 which is a continuation of application Ser. No. 08/294,402, filed on Aug. 23, 1994, now U.S. Pat. No. 5,469,221, which is a continuation of application Ser. No. 08/185,155, filed on Jan. 24, 1994, now U.S. Pat. No. 5,387,945, which is a continuation of application Ser. No. 08/039,708, filed on Mar. 31, 1993,
The present invention will be described in detail in the following in connection with one embodiment thereof with reference to the accompanying drawings.
These control data outputted from the CPU control unit 600 are those for achieving the luminance signal LSMON according to an object and are controlled by the CPU control unit 600.
Next,
This image processing system has a structure, in which the extended slot card 704 is interposed between the personal computer body 700 and the personal computer monitor 701.
The extended slot card 704 is connected with the tuner 710 and inserted into the (not-shown) extended slot of the personal computer body 700, as shown in FIG. 3.
The image corresponding to the luminance signal LSTV outputted from the tuner 710 is displayed together with the image corresponding to the luminance signal LSPC, with an arbitrary size, at an arbitrary timing in an arbitrary position of the image corresponding to the luminance signal LSPC and displayed by the personal computer monitor 701, by the operation of the keyboard 702 or the mouse 703.
Next,
Moreover, numeral 210 designates an ADC for digitizing the luminance signal LSTV; and numeral 220 designates a digitize control unit for controlling the ADC 210 and so on on the basis of the synchronizing signal SSTV.
Moreover, numeral 310 designates a three-port video memory having one write port and two read ports; numeral 320 designates a video data selector for selectively outputting either the luminance signal LSTV outputted from the ADC 210 or the luminance signal LSPC outputted from the (not-shown) personal computer; numeral 330 designates a video memory control signal selector for selectively outputting either a video memory control signal WETV outputted from the digitization control unit 220 or a video memory control signal WEPC outputted from a write control unit 340; this write control unit 340 is used for controlling the luminance signal LSPC outputted from the personal computer in the three-port video memory 310; numeral 350 designates a read control unit; numeral 360 designates a first-in/first-out type FIFO memory for storing the luminance signal LSMEM stored by the three-port video memory 310; and numeral 370 designates a FIFO read control unit for controlling the read of the luminance signal LSMEM coming from the three-port video memory 310.
On the other hand, numeral 410 designates a DAC; numeral 420 designates a superimpose control unit for controlling the three-port video memory 310, the DAC 410 and an AND circuit 530 by inputting a synchronizing signal HSPC and a vertical synchronizing signal VSPC outputted from the personal computer; numeral 510 designates a video switch for outputting either of the luminance signal LSPC coming from the personal computer or the luminance signal LSMEM coming from the three-port video memory 310 as the luminance signal LSMON of the personal computer monitor; numeral 520 designates a mixing control unit; numeral 540 designates a voltage comparator for comparing a reference voltage Vr and the luminance signal LSPC coming from the personal computer; and numeral 620 designates a CPU in the personal computer body.
Next,
Here, the audio signal ASTV can be outputted to a headphone 717 or a (not-shown) speaker through a plug 716 connected with an output connector 715.
The tuner 710 outputs the audio signal ASTV and video signal VSTV of specified channels of the signals it receives from the antenna 711 and the antenna terminal, to the audio signal selector 110 and the video signal selector 130, respectively, through the output connectors 713 and 714.
In this case, the tuning is accomplished by controlling the CPU 620.
On the other hand, the audio signal ASEX and the video signal VSEX are outputted from a (not-shown) video device such as a video deck or a laser disc, respectively, to the audio signal selector 110 and the video signal selector 130.
The audio input selector 110 is controlled by the CPU 620 to select and output the audio signal ASTV or ASEX to the volume control circuit 120.
This volume control circuit 120 is controlled by the CPU 620 to amplify the audio signal ASTV outputted from the audio signal selector 110 and to output it as the audio signal ASMON in the personal computer monitor cable to the audio signal terminal 102.
The audio signal ASTV is outputted to the output connector 714.
The video signal selector 130 is controlled by the CPU 620 to select and output the video signal VSTV or VSEX to the video signal decoder 140.
The display area is assigned by mouse cursor 301 using mouse 703. The image obtained from tuner 710 is displayed in the assigned display area.
Thanks to this packaging, the utility software can be run to observe the image from the TV set or the video deck in a preferable position and with a preferable size by a simple keyboard operation no matter what application software is operating on the OS.
The video signal decoder 140 separates the video signal VSTV, which is outputted from the video signal selector 130, into the luminance signal LSTV and the synchronizing signal SSTV and outputs them to the ADC 210 and the digitize control unit 220 respectively, as shown in FIG. 4.
Here the synchronizing signal SSTV is composed of the vertical synchronizing signal VSTV and a horizontal synchronizing signal HSTV.
In response to a clock signal CKAD outputted from the digitize control unit 220, the ADC 210 converts the luminance signal LSTV outputted from the video signal decoder 140 into a digital signal and outputs it through the video data selection unit 320 to the three-port video memory 310.
The digitization control unit 220 outputs not only the clock signal CKAD to the ADC 210 but also the video memory control signal WETV through the video memory control signal selection unit 330 to the three-port video memory 310.
Thus, the three-port video memory 310 stores the updated luminance signal LSTV under the condition controlled by the CPU 620.
Here is omitted the video memory control signal selector 330. In the present embodiment, the three-port video memory 310 is exemplified by the product CSK1206 of SONY and the product MB81C1501 of FUJITSU.
Incidentally, the following description will be made by using only the read ports of the three-port video memory 310.
The characteristic timing chart is disclosed on pp. 21 to 26 of the Data Sheet 71215-ST of SONY.
The three-port video memory 310 is constructed to have a capacity of 960 columns×306 rows×4 bits.
As a result, one effective horizontal scanning period can be quantized with the numerical value of 960.
On the other hand, the three-port video memory 310 is accessed for the columns at the unit of block and for the rows at the unit of line.
In the three-port video memory 310: reference characters DIN0 to DIN3 designate data inputs for inputting the luminance signal LSTV; characters ADD0 to ADD3 designate address inputs; characters CKW0 designate a port-0 shift signal; characters INC0 designate a port-0 line increment signal; characters HCLR0 designate a port-0 horizontal clear signal; characters VCLR0 designate a port-0 vertical clear signal; and characters WE (i.e., negative logic) designate a port-0 write enable signal.
These signals CKW0, YCLR0, HCLR0, INC0 and WE (i.e., negative logic), ADD0 and DIN0 to DIN3 are dichroic video signals of 4 bits, i.e., 16 gradations.
Here, even color luminance signals of 4 bits or more could naturally be likewise handled by connecting a plurality of three-port video memories 310 in parallel.
In FIG. 8: reference numeral 140 designates the video signal decoder for separating the video signal VSTV into the horizontal synchronizing signal HSTV, the vertical synchronizing signal VSTV and the luminance signal LSTV to output them; numeral 221 designates a dot clock generator for outputting a horizontal write dot clock signal HDCK and a basic synchronizing signal BSYNC; numeral 222 designates a horizontal write starting counter for outputting a horizontal write starting signal HWS and an HCLR0 signal; numeral 223 designates a horizontal write number counter for outputting a horizontal write number signal HWT; numeral 224 a vertical write line clock generator for outputting vertical write line clock signal VWLCK; numeral 225 designates a vertical write starting counter for outputting a vertical write starting signal VWS; numeral 226 designates a vertical write number counter for outputting vertical write number signal VWT; numeral 227 designates a vertical write offset counter for outputting a vertical write offset signal YWOFT for designating the vertical write position of the three-port video memory 310 and the port-0 line increment INC0; numeral 228 designates an OR circuit for outputting either the vertical write line clock signal VWLCK or the vertical write offset signal VWOFT as the port-0 line increment INC0; numeral 229 designates an AND circuit for taking the logical product of the inverted outputs of the horizontal write dot clock signal HDCK, the horizontal write starting signal HWS and the horizontal write number signal HWT and the inverted outputs of the vertical write starting signal VWS and the vertical write number signal VWT to output a write enable signal WENBL; and numeral 230 designates a NOR circuit for taking the output of AND 810, the HCLR0 signal, the output signal of the OR circuit 228 and the write enable signal WENBL outputted from the AND circuit 229 to output the port-0 write enable signal WE.
Incidentally for the color display, the luminance signal LSTV is composed of individual R, G and B luminance signals RLSTV, GLSTV and BLSTV.
The video signal decoder 140 separates the video signal VSTV outputted from the video signal selector 130, into the horizontal synchronizing signal HSTV, the vertical synchronizing signal VSTV and the luminance signal LSTV.
The horizontal synchronizing signal HSTV is outputted to the dot clock generator 221, the horizontal write starting counter 222, the horizontal write number counter 223 and the vertical write starting counter 225.
The vertical synchronizing signal VSTV is outputted to the vertical write line clock generator 224, the vertical write starting counter 225, the vertical write number counter 226, the vertical write offset counter 227, the port-0 vertical clear terminal VCLR0 of the three-port video memory 310, and the NOR circuit 230.
Moreover, the luminance signal LSTV is outputted to the ADC 210.
This ADC 210 digitizes the luminance signal LSTV1 in response to the horizontal write dot clock signal HDCK, which is inputted as the clock signal CKAD, to output the digitized the luminance signal LSTV to the three-port video memory 310.
The dot clock generator 221 generates the horizontal write dot clock signal HDCK having a period of 1/N (N: a positive integer) in synchronism with the horizontal synchronizing signal HSTV, i.e., the period 63.5 μs of the horizontal synchronizing signal HSTV. The horizontal write dot clock signal HDCK is outputted to the ADC 210, the horizontal write starting counter 222, the horizontal write number counter 223 and the AND circuit 229.
In case the block unit of the address preset of the three-port video memory 310 is 60 dots whereas one effective horizontal scanning period of the vertical synchronizing signal VSTV is 50 (μs), the horizontal write dot clock signal HDCX has its frequency calculated, as follows:
By this horizontal write dot clock signal HDCK, one effective horizontal scanning period can be quantized with 60 dots.
Since the three-port video memory 310 is constructed to have sixteen blocks (=960 dots for 60 dots composing one block), the luminance signal LSTV of one effective horizontal scanning period can be written at the unit of block, as follows:
Thus, the dot clock generator 221 outputs the horizontal write dot clock signal HDCK having the frequency based upon the value of the block B.
Here, the value of the block B can be set by the CPU 620.
Moreover, the dot clock generator 221 generates a basic synchronizing signal BSYNC to be used as the clock of the port-0 shift signal terminal CKW0 (for incrementing the horizontal write address of the three-port video memory 310 at the unit of dot) of the three-port video memory 310.
As a result, the image corresponding to the luminance signal LSTV is enlarged when the period of the clock signal CKAD for digitizing the luminance signal LSTV is longer than that of the basic synchronizing signal BSYNC for incrementing the horizontal write address of the three-port video memory 310 at the unit of dot. When, on the contrary, the period of the clock signal CKAD is smaller than that of the basic synchronizing signal BSYNC, the image corresponding to the luminance signal LSTV is reduced.
The basic synchronizing signal BSYNC is one of synchronizing the individual control circuits basically and is outputted to the horizontal write starting counter 222, the horizontal write number counter 223, the vertical write line clock generator 224, the vertical write starting counter 225, the vertical write number counter 226, the vertical offset counter 227 and the three-port video memory 310.
The vertical write line clock generator 224 is synchronized with the vertical synchronizing signal VSTV to output the vertical write line clock signal VWLCK having a frequency an N times as high as that of the vertical synchronizing signal VSTV to the vertical write number counter 226 and the OR circuit 230.
Incidentally, the value of N can be set by the CPU 620. The value of N is determined on the basis of an aspect ratio suitable for the dot clock generator 221.
The horizontal write starting counter 222 is reset by the horizontal synchronizing signal HSTV to count the clock number of the horizontal write dot clock signal HWDCK thereby to output the horizontal write starting signal HWS starting the quantization of the luminance signal LSTV at the S1-th clock for the effective horizontal scanning period of the video signal VSTV.
The horizontal write starting counter 222 outputs one clock of the port-0 horizontal clear signal HCLR0 together with the horizontal write starting signal HWS to the AND circuit 229.
The horizontal write time counter 223 starts the counting of the clocks of the horizontal write dot clock signal HWDCK, when it is reset by the horizontal synchronizing signal HSTV to output the horizontal write starting signal HWS, to output the horizontal write number signal HWT allowing the quantization of the luminance signal LSTV only for the period of the E1 clocks of the effective horizontal scanning period of the luminance signal VSTV.
Thus, the horizontal write number counter 223 controls the effective horizontal scanning period.
The vertical write starting counter 225 is reset by the vertical synchronizing signal VSTV to count the clock number of the horizontal synchronizing signal HSTV thereby to output the vertical write starting signal VWS allowing the quantization of the luminance signal LSTV of the effective horizontal scanning from the S2-th clock of the vertical effective scanning period of the video signal VSTV.
The vertical write number counter 226 starts the counting of the clocks of the vertical write line clock signal VWLCK, when the vertical write starting signal VWS is outputted, to output the vertical write number signal VWT allowing the quantization of the luminance signal LSTV for the period of the clocks E2 of the vertical effective scanning period of the video signal VSTV.
Thus, the vertical write number counter 226 controls the vertical effective scanning period.
The write position in the horizontal direction, i.e., in the COLUMN direction of the three-port video memory 310 with respect to the display frame is determined by a block designation, in which the sixty bits of the quantized luminance signal LSTV is one block, in accordance with an address preset mode.
This block designation is accomplished at sixteen steps in response to address input signals ADD0 to ADD3.
These address input signals ADD0 to ADD3 can be set by the CPU 620.
The vertical write position of the three-port video memory 310 is set by the vertical write offset counter 227.
The vertical write offset counter 227 is reset by the vertical synchronizing signal VSTV and the counter outputs the vertical write offset signal VWOFT for offsetting the vertical write position of the three-port video memory 310 in synchronism with the basic synchronizing signal BSYNC thereby to control the vertical write position of the three-port video memory 310.
Here, these values of S1, E1, S2, E2 and S3 are set by the CPU 620.
Next, the operations of the digitize control unit 220 and its peripheral circuits shown in
(1) When the vertical synchronizing signal VSTV takes a high level "H" (as shown at (a) in FIG. 9), the vertical write starting counter 225, the vertical write number counter 226 and the vertical write offset counter 227 are reset to set the vertical write starting signal VWS and the vertical write number signal VWT at a low level "L" (as shown at (d) and (e) in FIG. 9).
(2) The vertical write offset counter 227 outputs basic synchronizing signal BSYNC as the vertical write offset signal VWOFT for the period of the S3 clocks (as shown at (h) in FIG. 9).
The vertical write offset signal YWOFT is outputted through the OR circuit 228 to the port-0 line increment signal terminal INC0 so that the three-port video memory 310 has its vertical address incremented by the S3 times.
(3) When the clock number of the vertical synchronizing signal VSTV takes the value S2, on the other hand, the vertical write starting counter 225 raises the vertical write starting signal VWS to the high level "H" to allow the quantization of the vertical effective scanning period (as shown at (d) in FIG. 9).
(4) The three-port video memory 310 has its vertical write offset, when it receives the clocks of the vertical write offset signal YWOFT so that the horizontal synchronizing signal HSTV takes the high level "H". Then, the horizontal write starting counter 222 and the horizontal write number counter 223 are reset to drop the horizontal write starting signal HWS and the horizontal write number signal HWT to the low level "L" (as shown at (n) and (o) in FIG. 9).
On the other hand, the dot clock generator 221 outputs the horizontal write dot clock signal HWDCK (as shown at (m) in FIG. 9).
In response to the output of the horizontal write dot clock signal HWDCK, the ADC 210 uses the horizontal write dot clock signal HWDCK as the sampling hold signal and the data latch signal to sample the luminance signal LSTV.
The horizontal write starting counter 222 counts the number of cycle of the horizontal write dot clock signal HWDCK to raise the horizontal write starting signal HWS to the high level "H", when the counted value reaches S1, thereby to allow the quantization of the effective horizontal scanning period (as shown at (n) in FIG. 9).
Simultaneously with this, the horizontal write start counter 222 outputs one clock of the port-O horizontal clear signal HCLR0 of the three-port video memory 310 to prepare the writing operations.
At this time, the AND circuit 229 takes the logical product condition among the horizontal write starting signal HWS at the high level "H", the inverted horizontal write number signal HWT at the low level "L", the vertical write starting signal VWS at the high level "H" and the inverted vertical write number signal VWT at the low level "L" to output the horizontal write dot clock signal HWDCK as the write enable signal WENBL to the NOR circuit 230.
Then, this NOR circuit 230 takes the NOT-OR condition among the port-O horizontal clear signal HCLR0 at the high level "H", the write synchronizing signal VSTV at the high level "H", the vertical write offset signal YWOFT or the vertical write line clock signal VWLCK at the high level "H" and the write enable signal WENBL to output the write enable signal WE to the write enable signal terminal WE of the three-port video memory 310.
In response to the output of the write enable signal WE, the three-port video memory 310 writes the luminance signal LSTV outputted from the ADC 210.
Simultaneously with this, the horizontal write number counter 223 counts the clock number of the horizontal write dot clock signal HWDCK to allow the write of the luminance signal LSTV till the counted value reaches E1.
When this counted value reaches E1, the horizontal write number counter 223 raises the horizontal write number signal HWT to the high level "H" to inhibit the write (as shown at (o) in FIG. 9).
While the luminance signal LSTV is being written, the line addresses in the common vertical direction are written in the horizontal direction till the vertical write line clock generator 224 outputs the vertical write line clock signal VWLCK.
When the vertical write line clock generator 224 outputs the vertical write line clock signal VWLCK as the port-0 line increment signal terminal INC0 of the three-port video memory 310, the write line address of the three-port video memory 310 in the vertical direction advances by 1.
When the clock number of the vertical write line clock signal VWLCK outputted to the vertical write number counter 226 from the vertical write line clock generator 224 reaches the value E2, the vertical write number counter 226 raises the vertical write number signal VWT to the high level "H" to interrupt the writing of the three-port video memory 310 for the vertical effective scanning period (as shown at (e) in FIG. 9).
This interruption of writing is continued till the vertical synchronizing signal VSTV takes another round of the high level "H".
In the present embodiment thus far described, the smart image can be realized, although difficult in the prior art, by controlling the control signals to be outputted to the ADC 210 and the three-port video memory 310, with respect to the single signal flow.
Incidentally, the active logic is effected by the high level "H" in the aforementioned operations but may be likewise accomplished by the low level "L".
According to the present embodiment, the imaging techniques such as the arbitrary resolution of the video signal VSTV, the arbitrary aspect ratio, the window display of the arbitrary region or the multi-strobo still image can be easily controlled by the CPU 620, and the production cost can be easily dropped for home appliances. Therefore, the image processing system can be used in not only a video device such as a personal computer TV set, an intelligence terminal, a TV telephone or a smart TV set but also an area designated monitor system using a video monitor camera and is indispensable in a future machine associated with images.
The three-port video memory 310 accomplishes the following operations in case the CPU 620 writes video data.
First of all, the CPU 620 controls a change-over control signal CC of the write control unit 340 to switch the video data selection unit 320 and the video memory control signal selection unit 330.
As a result of this switching, the three-port video memory 310 receives not a write control signal WCTV outputted from the digitize control unit 220 but a write control signal WCPC outputted from the write control unit 340.
The luminance signal LSPC outputted from the CPU 620 is inputted through the write control unit 340 and the video data selection unit 320 to the three-port video memory 310.
The three-port video memory 310, is written with that luminance signal LSPC in response to the write control signal WCPC outputted from the write control unit 340.
Next, the three-port video memory 310 transfers the luminance signal to FIFO memory 360 the by the DMA transfer.
Here, the FIFO memory 360 has a storage capacity equal to or more than that of the three-port video memory 310.
Here will be described the operations in which the CPU 620 reads out the stored luminance signal LSMEM of the three-port video memory 310 by the DMA.
First of all, the read control unit 350 controlled by the CPU 620 outputs the scanning line information or the offset value of the scanning line, which is to be read out from the three-port video memory 310, to the three-port video memory 310.
The FIFO read control unit 370 subjects the three-port video memory 310 to the direct memory access (which will be shortly referred to the "DMA") with the luminance data LSMEM of the canning line to transfer the luminance signal LSMEM to the input port of the asynchronous I/O or the FIFO memory 360.
The CPU 620 reads in the luminance signal LSMEM thus transferred to the FIFO memory 360, from the output port of the FIFO memory 360 through the read control unit 350 and the CPU bus 610.
Incidentally, the present invention can naturally be embodied if the personal computer body and the personal computer monitor are integrated, although the present embodiment has been described in the case of the personal computer body and the personal computer monitor being separated.
Next, the operations of the DMA circuit shown in
(b 1) When the FIFO DMA control unit 370 outputs the horizontal clear signal HCLR, which is used to reset the horizontal address of the three-port video memory 310, through a luminance data bus 371 to the three-port video memory 310 (as shown at (b) in FIG. 11), the three-port video memory 310 is set at a 0 address.
When, on the other hand, the FIFO read control unit 370 outputs the address reset signal FRR (i.e., the signal inverted from the horizontal clear signal HCLR by a NOT circuit 372) of the FIFO memory 360 to the FIFO memory 360 simultaneously with the output of the horizontal clear signal HCLR (as shown at (d) in FIG. 11), the write address of the FIFO memory 360 is set at the 0 address.
(2) Each time the clock signal CLK outputted from the FIFO DMA control unit 370 rises after the setting of the three-port video memory 310 (as shown at (a) in FIG. 11), this three-port video memory 310 outputs the luminance signal LSMEM (as shown at (c) in
(3) Each time the clock signal CLK rises (as shown at (a) in FIG. 11), the addresses of both the three-port video memory 310 and the FIFO memory 360 are incremented one by one so that the reading of the luminance signal LSMEM from the three-port video memory 310 and the writing of the luminance signal LSMEM in the FIFO memory 360 are repeatedly executed.
(4) When the reading and writing of the luminance signal LSMEM are accomplished by the N times (i.e., the maximum number of repetitions), the FIFO DMA control unit 370 outputs the horizontal clear signals HCLR and FRR to set the addresses of the three-port video memory 310 and the FIFO memory 360 to the 0 address so that the aforementioned operations are repeated.
Since, in this case, the clock signal CLK outputted from the FIFO DMA control unit 370 is given a frequency no less than 10 MHz by the specifications of the reading condition of the three-port video memory 310, it is used as the refresh timing of the three-port video memory 310.
Next,
The operations of this offset circuit will be described with reference to the timing chart of FIG. 13.
(1) The CPU 620 sets the read offset value N of the FIFO memory 360 in the read control unit 350 through the CPU bus 610.
(2) If the CPU outputs an FIFO read memory set signal RR at the high level "H" (as shown at (b) in
In response to the output of the FIFO read memory reset signal RR, moreover, an FIFO read offset starting signal CST for starting the clock in the read control unit 350 and an FIFO offset ending signal CEND for ending the clock are dropped to the low level "L" so that the CPU 620 the clock signal CLK of the N clocks to the FIFO memory 360 and the FIFO read control unit 350.
(3) After the clock signal CLK has been outputted by the N clocks (as shown at (a) in FIG. 13), the FIFO read control unit 350 raises the FIFO read offset ending signal CEND to the high level "H" (as shown at (d) in
At this time, the FIFO memory 360 outputs an N-address luminance signal LSFIFO as the DATA signal at its output portion.
The FIFO read offset ending signal CEND is outputted to the CPU 620, too, so that the CPU 620 reads in the DATA signal in response to the high level "H" of a chip select/read signal RD/CS.
(4) When this chip select/read signal RD/CS takes the low level "L", the FIFO memory 360 has its address incremented by 1.
The Read cycle of CPU 620 is approximately 1 MHZ, while the frequency of the clock signal CLK is 10 MHZ or more. When the offset position is determined by using the clock signal CLK, only {fraction (1/10)} of the time of the CPU Read cycle is used, thus achieving substantial performance improvement.
Since the output portion of the three-port video memory 310 can be operated with a frequency of 10 (MHz) or higher, as has been described hereinbefore, the clock signal CLK can be used as the refresh timing of a dynamic memory of the three-port video memory 310.
Thus, the transfer of the luminance signal LSMEM from the three-port video memory 310 to the DAC 410 is not interrupted so that the a superimposed image is always outputted as the luminance signal LSMON to the personal computer monitor.
Therefore, the present invention can be applied to the promising video appliances such as the personal computer TV set, the intelligent terminal or the TV telephone.
Incidentally, the logics of the timing chart shown in
Moreover, the transfer of the luminance data has been described in the present embodiment in the state having the personal computer body and monitor separated from each other but could be accomplished in case the body and monitor are integrated into one personal computer.
Next, the superimpose control unit 420 outputs the read control signal and the clock signal CKDA to the three-port video memory 310 and the DAC 410 on the basis of the conditions controlled by the CPU 620.
In response to the read control signal, the updated luminance signal LSMEM is read out from the three-port video memory 310.
The DAC 410 converts the luminance signal LSMEM, which is read out from the three-port video memory 310, into the analog signal LSDA and outputs it to the video switch 510.
The AND circuit 530 takes an AND condition between the superimpose starting signal outputted from the superimpose control unit 420 and the multiplex super impose starting signal outputted from the mixing control unit 520 controlled by the CPU 620.
The video switch 510 switched on the basis of the output signal of the AND circuit 530 to superimpose the luminance signal LSMEM outputted from the DAC 410 on the personal computer body side luminance signal LSPC.
Next,
Moreover, the three-port video memory 310 is exemplified by the aforementioned product CXK1206 of SONY or MB81C1501 of FUJITSU, and the read port of its three input/output ports is used.
The timing chart is disclosed on pp. 27 to 31 of the data sheet No. 71215-ST of the CXK1206 of SONY. The port used is the read port 1 appearing on pp. 2.
In the three-port video memory 310; a memory drive clock signal HDCK is inputted to a port-1 shift signal CKR1; a memory vertical/horizontal reset signal MRST is inputted to a port-1 vertical clear VCLR1; a horizontal reset signal HRST is inputted to a port-1 horizontal clear HCLR1; a vertical offset signal VOFT or a vertical line clock signal VLCK is inputted to a port-1 line increment INC1; and a port-1 output enable RE1 (i.e., negative logic) is inputted to a port-1 output enable RE1 (i.e., negative logic).
Moreover, the luminance signal LSMEM is read out from port-1 data outputs DO10 to DO13.
The luminance signal LSMEM having its read controlled by those port-1 shift signal CKR1, port-1 vertical clear signal VCLR1, port-1 horizontal clear signal HCLR1 port-1 line increment signal INC1, port-1 output enable RE1 (i.e., negative logic) and port-1 data outputs DO10 to DO13 is a dichroic luminance signal having 4 bits, i.e., sixteen gradations.
Here, it is needless to say that the luminance signal having 4 bits or more or the color luminance signal could likewise be processed.
In FIG. 14: reference numeral 310 designates a three-port video memory for storing the luminance signal LSMEM; numeral 410 designates a DAC for converting the luminance signal LSMEM to analog prior to outputting luminance signal LSDA; numeral 510 designates a video switch for outputting the input at a point A or B from a common point C in response to a change-over signal CNT inputted to the change-over input terminal; numeral 620 designates a CPU for outputting the horizontal synchronizing signal HSPC or the vertical synchronizing signal VSPC; numeral 610 designates a CPU bus; numeral 421 designates a horizontal reference read dot clock generator for outputting a horizontal reference read dot clock signal HBDCK; numeral 422 designates a horizontal read starting counter for outputting a horizontal read starting A signal HRSA and a horizontal read direction reset signal HRST; numeral 423 designates a horizontal 64-clock counter for outputting a horizontal read starting B signal HRSB; numeral 424 designates a horizontal read number counter for outputting a horizontal read number signal HRT; numeral 425 designates a horizontal read dot clock generator for outputting a horizontal read dot clock signal HDDA; Numeral 426 designates a memory vertical read offset counter having a function capable to set the count number of the horizontal reference read dot clock generator 421 at will by the CPU 620 to output a vertical read offset signal VROFT; numeral 427 designates a vertical blanking number counter for outputting vertical blanking ending signal; numeral 428 designates a vertical read starting counter for outputting a vertical read starting signal VRS; numeral 429 designates a vertical read number counter for outputting a vertical read number signal VRT; numeral 430 designates a vertical read line clock generator for outputting a vertical read line clock signal VRLCK; numeral 431 designates an AND circuit for outputting a superimpose starting signal; numeral 432 designates an OR circuit for outputting either a vertical read offset signal VROFT or a vertical read line increment signal VRLCK as a vertical read clear signal VCLR1; numeral 433 designates a NOR circuit for outputting a read enable signal RE1; numerals 434 and 435 designate tri-state circuits; and numeral 436 designates an inverter circuit.
The luminance signal LSPC outputted by the personal computer is inputted to the point A of the video switch 510.
Moreover, the horizontal synchronizing signal HSPC is inputted to the horizontal reference read dot clock generator 421, the horizontal read starting counter 422, the horizontal 64-clock counter 423, the horizontal read number counter 424, the horizontal read dot clock generator 425, the vertical blanking number counter 427, the vertical read starting counter 428, the vertical read number counter 429, the vertical read line clock generator 430 and the (not-shown) personal computer monitor.
The horizontal read starting counter 422, the horizontal 64-clock counter 423 and the horizontal read number counter 424 have their individual count values reset by the horizontal synchronizing signal HSPC.
Moreover, the vertical synchronizing signal VSPC is inputted to the port-1 vertical clear VCLR1 of the three-port video memory 310, the NOR circuit 433, the vertical read offset counter 426, the vertical blanking number counter 427, the vertical read starting counter 428, the vertical read number counter 429, the vertical read line clock generator 430 and the personal computer monitor.
The vertical read offset counter 426, the vertical blanking number counter 427, the vertical read starting counter 428 and the vertical read number counter 429 have their individual count values reset by the vertical synchronizing signal VSPC.
The horizontal reference read dot clock generator 421 is constructed of a PLL circuit, which is synchronized with the horizontal synchronizing signal HSPC to output a signal having a frequency several hundreds times as high as that of the horizontal synchronizing signal HSPC, to output the horizontal reference read dot clock signal HBDCK corresponding to the horizontal dot clock signal of the personal computer monitor.
The horizontal reference read dot clock signal HBDCK is outputted as the clock signal HDCK of the three-port video memory 310 to the port-1 shift signal terminal CKR1 of the three-port video memory 310 through the horizontal read starting counter 422, the horizontal 64-clock counter 423, the horizontal read number counter 424, the vertical read offset counter 426 and the tri-state circuit 435.
The vertical read dot clock generator 425 is constructed of a PLL circuit, which is synchronized with the horizontal synchronizing signal HSPC to output a signal having a frequency of N1 times as high as that of the horizontal synchronizing signal HSPC, to output the horizontal read dot clock signal HDDA.
The horizontal read dot clock signal HDDA is outputted as the clock signal HDCK of the three-port video memory 310 through the tri-state circuit 434 to the port-1 shift signal terminal CKR1 of the three-port video memory 310 and the DAC 410 so that it is used as the read clock signal of the luminance signal LSMEM and the conversion clock signal of the DAC 410.
The vertical read line clock generator 430 is constructed of a PLL circuit, which is synchronized with the vertical synchronizing signal VSPC to output a signal having a frequency of N2 times as high as that of the vertical synchronizing signal VSPC, to output the vertical read line clock signal VRLCK.
The vertical read line clock signal VRLCK is synchronized with the clock signal HDCR of the three-port video memory 310 and is outputted to the port-1 output enable RE1 (i.e., the negative logic) through not only the port-1 line increment INC1, which is used to advance the line address, i.e., the vertical address of the three-port video memory 310 through the OR circuit 432, but also the OR circuit 432 and the NOR circuit 433.
The basic timings of the superimpose circuit 420 is obtained by those horizontal reference read dot clock signal HBDCK, horizontal read dot clock signal HDDA and vertical read line clock signal VRLCK.
In order to determine the read starting offset point of the three-port video memory 310, the vertical read offset counter 426 outputs the vertical offset signal VOFT for summing the vertical line addresses of the three-port video memory 310, while being synchronized with the horizontal reference read dot clock signal HBDCK, after the counted value has been reset by the vertical synchronizing signal VSPC.
The vertical blanking number counter 427 outputs the vertical blanking ending signal VBE when the (not-shown) counter for eliminating the vertical back porch region of the LSPC counts the clock number of the horizontal synchronizing signal HSPC so that the vertical back porch region is passed.
In response to the output of the vertical blanking ending signal VBE or the starting signal outputted from the vertical blanking number counter 427, the vertical read starting counter 428 counts the clock number of the horizontal synchronizing signal HSPC to output the vertical read starting signal VRS or the vertical read starting signal coming from the three-port video memory 310.
In response to the output of the luminance signal VRS or the starting signal outputted from the vertical read starting counter 428, the vertical read number counter 429 counts the clock number of the horizontal synchronizing signal HSPC to output the vertical read number signal VRT or the vertical read period coming from the three-port video memory 310.
This three-port video memory 310 is vertically controlled by the vertical read offset counter 426 the vertical blanking number counter 427, the vertical read starting counter 428 and the vertical read number counter 429.
Here, the clock number of the horizontal reference read dot clock signal HBDCK counted by the vertical read offset counter 426, the clock number of the horizontal synchronizing signal HSPC counted by the vertical blanking number counter 427, the clock number of the horizontal synchronizing signal HSPC counted by the vertical reading starting counter 428, and the clock number of the horizontal synchronizing signal HSPC counted by the vertical read number counter 429 can be set at individual arbitrary values by the CPU 620.
Moreover, the horizontal read starting counter 422 counts the clock number of the horizontal reference read dot clock signal HBDCK, which is outputted by the horizontal reference read dot clock generator 421, to output the horizontal read starting A signal HRSSA or the horizontal read starting signal of the three-port video memory 310.
In response to the output of the horizontal read starting A signal HRSA or the starting signal outputted from the horizontal read starting counter 422, a horizontal 64 clock counter 423 counts the clock number of the reference dot clock signal HBDCK, which is outputted from the horizontal reference read dot clock generator 421, to output the horizontal read starting B signal HRSB when the counted value reaches the 64 clocks or the characteristics at the time of the reading operation of the three-port video memory 310.
The horizontal read number counter 424 counts the clock number of the reference dot clock signal HBDCK, which is outputted from the horizontal reference read dot clock generator 421, to output the horizontal read number signal HRT or the horizontal reading period starting signal of the three-port video memory 310.
This three-port video memory 310 is horizontally controlled by the horizontal read starting counter 422, the horizontal 64 clock counter 192 and the horizontal read number counter 424.
Here, the clock number of the horizontal reference read dot clock signal HBDCK counted by the horizontal read starting counter 422 and the clock number of reference dot clock signal HBDCK counted by the horizontal read number counter 424 can be set at individually arbitrary values by the CPU 620.
Next, the operations of the superimpose control unit 420 will be described with reference to
First of all, the vertical read starts of the three-port video memory 310 will be described in the following with reference to FIG. 15.
When the vertical synchronizing signal VSPC takes the high level "H" (as shown at (a) in FIG. 15), the vertical blanking number counter 427, the vertical read starting counter 428 and the vertical read number counter 429 are reset to drop the vertical blanking ending signal VBE, the vertical read starting signal VRS and the vertical read number signal VRT to the low level "L" (as shown at (d), (d) and (f) in FIG. 15). When the vertical blanking number counter 427 counts the clock number of the horizontal synchronizing signal HSPC to pass the vertical back porch region, the vertical blanking ending signal VBE is raised to the high level "H" (as shown at (d) in FIG. 15).
When the vertical blanking ending signal VBE takes the high level "H", the vertical read starting counter 428 starts to count the clock number of the horizontal synchronizing signal HSPC.
When the vertical read starting counter 428 counts the set value of the CPU 620, the vertical read starting signal VRS is raised to the high level "H" (as shown at (e) in FIG. 15).
When the vertical read starting signal VRS takes the high level "H", the three-port video memory 310 is allowed to start the reading of the luminance signal LSMEM in the vertical direction so that the vertical read number counter 429 starts to count the clock number of the horizontal synchronizing signal HSPC.
When the vertical read number counter 429 counts the set value of the CPU 620, the vertical read number signal VRT is raised to the high level "H" (as shown at (f) in FIG. 15).
When the horizontal read starting B signal HRSB is at the high level "H" whereas the horizontal read number signal HRT is at the low level "L", the AND circuit 431 outputs the superimpose starting signal SENBL while the vertical reading starting signal VRS is at the high level "H" whereas the vertical read number signal VRT is at the low level "L".
On the basis of the horizontal read start, therefore, the three-port video memory 310 reads out the luminance signal LSMEM.
Next, the vertical offsets of the three-port video memory 310 will be described in the following with reference to FIG. 16.
When the vertical synchronizing signal VSPC takes the high level "H" (as shown at (a) in FIG. 16), the vertical read offset counter 426 is reset to start the counting of the clock number of the reference dot clock signal HBDCK.
The vertical read offset counter 426 outputs the vertical read offset signal VROFT, while counting the set value of the CPU 620, through the OR circuit 432 to the port-1 line increment INC1 of the three-port video memory 310 (as shown at (c) in
Since, at this time, the vertical synchronizing signal VSPC and the vertical read offset signal VROFT are inputted to the NOR circuit 433, the read enable signal RE1 (i.e., the negative logic) is also outputted to the read enable RE1 (i.e., the negative logic) of the three-port video memory 310.
Next, the horizontal read starts of the three-port video memory 310 will be described in the following with reference to FIG. 17.
When the horizontal synchronizing signal HSPC, the horizontal read starting counter 422, the horizontal 64-clock counter 423 and the horizontal read number counter 424 are reset to drop the horizontal read starting A signal HRSA, the horizontal read starting B signal HRSB and the horizontal read number signal HRT to the low level "L" (as shown at (d), (e) and (f) in FIG. 17).
When the horizontal read starting counter 422 counts the clock number of the reference dot clock signal HBDCK, which is outputted by the horizontal reference read dot clock generator 421, so that the counted value takes the set value of the CPU 620, it raises the horizontal read starting A signal HRSA to the high level "H" (as shown at (d) in FIG. 17).
When the horizontal read starting A signal HRSA takes the high level "H", the horizontal 64-clock counter 423 starts to count the clock number of the reference dot clock signal HBDCK. When this counted value reaches 64, the horizontal read starting B signal HRSB is raised to the high level "H" (as shown in FIG. (e) in FIG. 17).
Incidentally, the horizontal 64-clock counter 423 need not its value to 64 because this number is caused from the characteristics of the three-port video memory 310.
When the horizontal read starting B signal HRSB takes the high level "H", the horizontal read of the three-port video memory 310 is started so that the horizontal read number counter 424 starts the counting of the clock number of the reference dot clock signal HBDCK. When the counted value reaches the set value of the CPU 620, the horizontal read number signal HRT is raised to the high level "H" (as shown at (f) in FIG. 17).
When the vertical read starting signal VRS is at the high level "H" whereas the vertical read number signal VRT is at the low level "L", the AND circuit 431 outputs the superimpose starting signal SENBL at the high level "H", while the horizontal read starting B signal is at the high level "H" whereas the horizontal read number signal HRT is at the low level "L".
On the basis of the vertical read start, therefore, the three-port video memory 310 reads out the luminance signal LSMEM.
Next, the horizontal reading operations of the three-port video memory 310 will be described in the following with reference to FIG. 18.
The superimpose starting signal SENBL takes the high level "H" (as shown at (c) in FIG. 18), and the read enable signal RE1 shown is one when the luminance signal LSMEM is read out from the three-port video memory 310 and when the DAC 410 is subjected to the analog conversion on the basis of the horizontal read dot clock signal HDDAS outputted from the horizontal red dot clock generator 425 (as shown at (b) in FIG. 18).
The luminance signal LSPC of the personal computer is inputted to the point A of the video switch 510.
Moreover, the luminance signal LSDA read out from the three-port video memory 310 and converted to analog by the DAC 410 is inputted to the point B of the video switch 510.
As a result of the switching of the video switch 510, the luminance signal LSMON or the output of the video switch 510 is outputted as the luminance signal LSMON corresponding to the image, which is formed by superimposing the image corresponding to the analogly converted luminance signal LSDA upon the image corresponding to the luminance signal LSPC outputted from the personal computer.
Together with the output of the luminance signal LSMON, the horizontal synchronizing signal HSPC and the vertical synchronizing signal VSPC are also outputted to the personal computer monitor.
Incidentally, the timing charts thus far described are presented merely as one example, and the aforementioned operations can be achieved no matter whether the individual signals might be positive or negative logics.
As shown in
By using the superimpose control unit 420 in the intelligent terminal and home TV set, according to the present invention, the image of the TV telephone or the interphone can be easily superimposed to realize monitorless TV telephone or interphone. Thus, one step is advanced to realize a new software computer, in which the image can be freely controlled in the computer, such as a baseball game capable of being enjoyed on a common monitor while operating the word processor in the personal computer TV, an educational program on a real video by the CAI, stress preventing measures for the VDT workers, or a monitor system using motion pictures on the computer.
Next,
The luminance signal LSPC outputted from the personal computer is outputted to the video switch 510 and the voltage comparator 540.
This voltage comparator 540 outputs comparison signals COMP at the high level "H" and at the low level "L", respectively, when the luminance signal LSPC is higher and lower than the reference voltage vr.
On the other hand, the superimpose control unit 420 outputs the starting signal CENBL for making the comparison signal COMP effective to the NAND circuit 450.
This NAND circuit 450 outputs the starting signal NENBL at the low level "L" only when the comparison signal COMP is at the high level "H" and the starting signal CENBL is at the high level "H".
An AND circuit 451 is fed with: the starting signal read out from the three-port video memory 310 for starting the superimpose of the luminance signal LSDA converted by the DAC 410 upon the luminance signal LSPC; the starting signal SSENBL for starting the superimpose of the luminance signal LSDA upon the luminance signal LSPC; and the starting signal NENBL outputted from the NAND circuit 450.
In response to the change-over signal CNT outputted from the AND circuit 451, the video switch 510 superimposes the video signal LSDA upon the luminance signal LSPC.
If the level of the luminance signal LSPC is generated when the luminance signal LSDA is superimposed upon the luminance signal LSPC, the output signal COMP of the voltage comparator 540 takes the high level "H".
If, at this time, the superimpose control unit 420 outputs the starting signal CENBL to the NAND circuit 450, this NAND circuit 450 outputs the starting signal NENBL at the low level "L" so that the change-over signal CNT outputted from the AND circuit 451 takes the low level "L" only for the period of the level time of the luminance signal LSPC.
As a result, the luminance signal LSPC in the luminance signal LSDA is superimposed upon the luminance signal LSMON of the personal computer monitor.
Incidentally, the starting signal SENBL and the starting signal CENBL are set at the high level "H".
The luminance signal LSMON (as shown at (i) in
Here, it is needless to say that the aforementioned operations can hold no matter whether the logics might be positive or negative.
Moreover, the AND circuit 451 and the NAND circuit 450 are circuits which can be easily realized for all the switches having the switches function such as the OR circuit, the multiplexer or the analog switch.
Although it is general to superimpose the luminance signal LSDA upon the luminance signal LSPC, it takes a remarkably long time to superimpose the luminance signal LSPC upon the luminance signal LSDA, and the superimposition is impossible in case the luminance signal LSDA relates to motion pictures.
In the present invention, however, the letters or special shapes to be displayed in the luminance signal LSDA are outputted to the luminance signal LSPC in the common position of the luminance signal LSDA so that the superimposition of the luminance signal LSDA is released only at the portion at the level of the luminance signal LSPC. This raises none of the problems of the prior art even in the motion pictures of the luminance signal LSDA and by a remarkably simple circuit. Therefore, the present invention is indispensable in the future image processing circuit.
Next, the operation in case the video still pictures are to be outputted will be described in the following.
The video signal decoder 140 outputs the vertical synchronizing signal VSTV from the luminance signal LSTV to an AND circuit 810. On the other hand, the CPU 620 outputs an ON/OFF signal for turning on and off the video still pictures to the AND circuit 810.
By outputting the ON/OFF signal at the low level "L" for turning on the still pictures to the AND circuit 810, the vertical synchronizing signal VSTV is not outputted from the video signal decoder 140 to the vertical write line clock generator 224, the vertical write starting counter 225, the vertical write number counter 226, the vertical offset counter 227 and the three-port video memory 310.
When the vertical synchronizing signal VSTV is not outputted, the vertical write line clock generator 224, the vertical write starting counter 225, the vertical write number counter 226, the vertical offset counter 227 and the three-port video memory 310 are not set up by the vertical synchronizing signal VSTV.
As a result, the three-port video memory 310 has its writing operation naturally interrupted because the vertical control system is not reset.
Thus, the CPU 620 can output the control signals of the still picture at any time to enter another job.
In case the still picture is to be turned off, on the other hand, the CPU 620 can output the control signals, if necessary, to the AND circuit 810.
There will be required a high-speed processing, in which the CPU 620 performs multi-purpose jobs multiplexly, and a loss as high as several tens mS adversely affects the throughput or turn-around to raise a serious problem.
As a result, the simplified circuit structure according to the present invention can eliminate the loss of several tens mS.
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