Filter circuit for communication

Abstract

The present invention has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption. The function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.

Description

FIELD OF THE INVENTION

The present invention relates to a filter circuit for communication, especially to a matched filter effective for a spread spectrum communication system for the mobile cellular radio and wireless LAN.

BACKGROUND OF THE INVENTION

A matched filter is a filter for judging the identification between two signals. In the spread spectrum communication, each user who receives a signal processes a received signal by a matched filter using spreading code allocated for the user to as to find a correlation peak for acquisition and holding.

Here, assuming that a spreading code is d(i), sampling interval is Δt, a length of spreading code is N, a received signal before a time t is x(T-iΔt), a correlation output y(t) of matched filter is as in formula (1). In formula (1), d(i) is a data string of 1 bit data. $\begin{array}{cc}y\⁡\left(t\right)=\underset{i=0}{\overset{N-1}{\∑}}\⁢d\⁡\left(i\right)\⁢x\⁡\left(t-i\⁢\⁢\mathrm{\Δ}\⁢\⁢t\right)& \left(1\right)\end{array}$

A conventional matched filter circuit is described here. In an accumulation circuit of a digital matched filter in FIG. 16, digitized input signal X is held in a shift register SFT-REG and shifted, then, a multiplier registered in a register REG is multiplied to the input signal on the predetermined sample timing by a plurality of digital multiplying portions DM. The outputs of multiplying portions are added by the digital adder DAD. These operations correspond to the formula (1). For the acquisition, double or higher order of sampling is necessary. In such a case, the circuit in FIG. 16 is plurally structured. Consequently, the size of the whole circuit was large and consumed much electric power. It is a serious defect. Though a circuit of SAW device was used, the total circuits cannot be incorporated within one LSI and S/N ratio was low.

The applicant of the present invention proposes a matched filter circuit by an analog circuit in FIG. 17. The electric power consumption was reduced by a circuit with a multiplier and an adder of voltage driven type using a capacitive coupling. However, a digital output is also necessary as an output of a matched filter because conventional digital communication will be also used for the present.

SUMMARY OF THE INVENTION

The present invention solves the above conventional problems and has an object to provide a filter circuit for communication generative an effective digital output as well as an analog output in a filter circuit of low electric power consumption.

In a matched filter circuit according to the present invention, the function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition.

It is possible to use a circuit of rather low speed as an A/D converting circuit by the matched filter circuit according to the present invention. Therefore, it is profitable considering the cost, yield and electric power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a matched filter circuit according to the present invention.

FIG. 2 shows a sampling and holding circuit in the first embodiment of the present invention.

FIG. 3 shows a shows one sampling and holding circuit in a sampling and holding circuit.

FIG. 4 shows a circuit of the first type switch in the embodiment.

FIG. 5 shows a circuit of the second type switch in the embodiment.

FIG. 6 shows a circuit of the third type switch in the embodiment.

FIG. 7 shows a circuit of an A/D converter in the embodiment.

FIG. 8 shows a circuit of the A/D converter in FIG. 7.

FIG. 9 shows a shows an accumulation circuit in the embodiment.

FIG. 10 shows a sampling and holding circuit in the accumulation circuit in FIG. 9.

FIG. 11 shows a circuit of an inverted amplifying portion included in the embodiment.

FIG. 12 shows a circuit of a multiplexer in the sampling and holding circuit if FIGS. 8 and 10.

FIG. 13 shows a circuit of the first addition circuit in the accumulation circuit in FIG. 9.

FIG. 14 shows a circuit of the second addition circuit in the accumulation circuit in FIG. 9.

FIG. 15 shows a circuit of the third addition circuit in the accumulation circuit in FIG. 9.

FIG. 16 shows a block diagram of conventional digital matched filter.

FIG. 17 shows a block diagram of proposed analog matched filter.

FIG. 18 shows a timing chart of the timing of action of the sampling and holding circuit.

FIG. 19 shows a timing chart of the timing of another action of the sampling and holding circuit.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

Hereinafter, the first embodiment of a matched filter according to the present invention is described with reference to the attached drawings.

In FIG. 1, a matched filter includes a sampling and holding circuit "S/H3" for holding an analog output signal of the circuit "MF" for addition and multiplication and A/D converting portion "A/D" for digitizing an analog output signal Aout from the sampling and holding circuit at the next stage to the circuit "MF" in FIG. 17. The sampling and holding circuit is controlled by a peak detector "PD". Accumulating portion outputs a clock signal C1 for deciding the time of holding data of an inside sampling and holding circuit and a reset signal RST for showing the timing of holding data of the first sampling and holding circuit to the peak detector PD. The peak detector controls S/H3 according to the signals.

The peak detector outputs a clock C2 corresponding to C1 and a signal N indicating a number of a datum to be held (i in the formula (1)) by the sampling and holding circuit S/H3. A plurality of Ns can be output up to a predetermined number, for example three. Each number is once registered in a register in the sampling and holding circuit (not shown in FIG. 1), a register selecting signal RSEL for the registration is input from PD to S/H3.

In FIG. 2, the sampling and holding circuit S/H3 includes a plurality of sampling and holding circuits SH21, SH22 and SH23 for holding Aout of an output of accumulating portion by an appropriate timing. The outputs of the sampling and holding circuits are connected to switches SB2, SB3 and SB4, respectively. When a supply voltage is Vdd, the reference voltage Vr of Vdd/2 is input to each sampling and holding circuit, and Vr is input to a switch SB1 arranged in parallel with the switches above. Outputs of SB1 to SB4 are input to a capacitance S21 in parallel, and an output of a capacitance C21 is input to an inverted amplifier INV2. An output of the inverted amplifier INV2 is fed back to the input through a capacitance C22. The outputs of SB1 to SB4 are output as analog output signal Ao2 with a good linearity.

SH21 to SH23 and SB1 to SB4 are controlled by controlling signal CF1 CF13, Ao13 of an output of INV13 is expressed as in the formula (2) $\begin{array}{cc}{\mathrm{Ao}}_{13}=-\frac{C_{131}\⁢{\mathrm{Ai}}_{131}+C_{132}\⁢{\mathrm{Ai}}_{132}+C_{133}\⁢{\mathrm{Ai}}_{133}}{{\mathrm{CF}}_{13}}& \left(2\right)\end{array}$

Here, Ai131 to Ai133 and Ao133 Ao13 are the voltage referencing the reference voltage Vr, and it is settled that C131=C132=C133=CF13/3. A normalized output of inverse value of addition can be obtained as in formula (3). It is prevented that the maximum voltage exceeds the supply voltage by the normalization. $\begin{array}{cc}{\mathrm{Ao}}_{13}=-\frac{{\mathrm{Ai}}_{131}+{\mathrm{Ai}}_{132}+{\mathrm{Ai}}_{133}}{3}& \left(3\right)\end{array}$

As in FIG. 14, an addition portion AD92 includes a capacitive coupling CP14 comprehending capacitances of the number corresponding to the number of connected sampling and holding circuits, C141 and C142. An output of CP14 is connected to INV14 which is the same as INV2, and is output to an output of INV14 with good linearity.

Assuming input voltages of capacitances C141 and C142 to be Ai141 and Ai142, and a feedback capacitance of INV14 to be CF14, an output Ao14 of INV14 is expressed as in the formula (4) $\begin{array}{cc}{\mathrm{Ao}}_{14}=-\frac{C_{141}\⁢{\mathrm{Ai}}_{141}+C_{142}\⁢{\mathrm{Ai}}_{142}}{{\mathrm{CF}}_{14}}& \left(4\right)\end{array}$

Here, Ai141, Ai142 and Ao14 are the voltage referencing the reference voltage Vr, and it is settled that C141=C142=CF14/2. A normalized output of inverse value of addition can be obtained by it as in formula (5). It is prevented that the maximum voltage exceeds the supply voltage by the normalization. $\begin{array}{cc}{\mathrm{Ao}}_{14}=-\frac{{\mathrm{Ai}}_{141}+{\mathrm{Ai}}_{142}}{2}& \left(5\right)\end{array}$

As in FIG. 15, an addition portion AD93 includes a capacitive coupling CP15 comprehending capacitances of the number corresponding to the number of circuits connected to AD93, two AD91p, two AD91m and AD92, C151, C152 and C153. An output of CP15 is connected to INV15 which is the same as INV2, and is output to an output of INV1 with good linearity.

Assuming input voltages (referencing Vr) of capacitances C151 to C153 to be Ai151, Ai152 and Ai153, and a feedback capacitance of INV15 to be CF15, Ao13 Ao15 of an output of INV15 is expressed as in the formula (6) $\begin{array}{cc}{\mathrm{Ao}}_{15}=-\frac{C_{15}\⁢{\mathrm{Ai}}_{151}+C_{152}\⁢{\mathrm{Ai}}_{152}+C_{153}\⁢{\mathrm{Ai}}_{153}}{{\mathrm{CF}}_{15}}& \left(6\right)\end{array}$

It is settled that C151=C152=C153/2+C15/2. A normalized output of inverse value of addition can be obtained by it as in formula (7). It is prevented that the maximum voltage exceeds the supply voltage by the normalization. The weight of C153 is twice as weights of C151 and C152 in order to reduce the influence of the normalization of AD92. The output of C153 is adjusted to be balanced with unnormalized Ao13 and Ao14. $\begin{array}{cc}{\mathrm{Ao}}_{15}=-\frac{{\mathrm{Ai}}_{151}+{\mathrm{Ai}}_{152}+2\⁢{\mathrm{Ai}}_{153}}{2}& \left(7\right)\end{array}$

Generalizing the calculation of AD91p, AD91m, AD92 and AD93, Ao14 of the output of AD92 and Ao15(t) of the output of AD93 are expressed in formulas (8) and (9), respectively, in which assuming a signal CTRL9 for i-th S/H9i to be CTRL 9(i) and its inversion to be ICTRL9(i). $\begin{array}{cc}\mathrm{Ao14}=\frac{1}{N}\⁢\underset{i=0}{\overset{N-1}{\∑}}\⁢\frac{\mathrm{ICTRL9}\⁡\left(i\right)+1}{2}\⁢V\⁡\left(t-i\⁢\⁢\mathrm{\Δ}\⁢\⁢t\right)& \left(8\right)\\ \mathrm{Ao15}\⁡\left(t\right)=-\frac{1}{N}\⁢\left\{{\mathrm{NA}}_0\⁢14-\underset{i=0}{\overset{N-1}{\∑}}\⁢\frac{\mathrm{ICTRL9}\⁡\left(i\right)+1}{2}\⁢V\⁡\left(t-i\⁢\⁢\mathrm{\Δ}\⁢\⁢t\right)\right\}& \left(9\right)\end{array}$

That is, it is the same that formula (10) is executed. $\begin{array}{cc}\mathrm{Ao15}\⁡\left(t\right)=\frac{1}{N}\⁢\underset{i=0}{\overset{N-1}{\∑}}\⁢\frac{\mathrm{CTRL9}\⁡\left(i\right)\⁢V\⁡\left(t-i\⁢\⁢\mathrm{\Δ}\⁢\⁢t\right)-\mathrm{ICTRL}\⁡\left(i\right)\⁢V\⁡\left(t-i\⁢\⁢\mathrm{\Δ}\⁢\⁢t\right)}{2}& \left(10\right)\end{array}$

Here,

CTRL9(i)=1 or CTRL9(i)=-1,

when CTRL9(i)=-1, ICTRL9(i)=-1,

when CTRL9(i)=-1, ICTRL9(i)=1.

Switches SA1 to SA12, SB1, SB7 to SB14 are for refreshing the circuit, and can cancel an offset voltage caused by a leak of electric charge or others. The switch of supply voltage SWS is for stopping supply voltage of the sampling and holding circuit etc. when possible for reducing electrical consumption. Even when the switch for refreshing is omitted, the output is usually enough accurate.

In a matched filter circuit according to the present invention, the function speed of an A/D converting circuit is minimized by intermittently holding an analog output signal according to an experience that peak detection can be performed by partially sampling the signal after the acquisition. Therefore, it is possible to use a circuit of rather low speed as an A/D converting circuit by the matched filter circuit according to the present invention. Therefore, it is profitable considering the cost, yield and electric power consumption.

Claims

1. A filter circuit for communication comprising:

i) a means for addition and multiplication for

a) sequentially holding an analog input signal by a plurality of a first sampling and holding circuits at a plurality of holding points,

b) performing a weighted addition by PN code of said analog input signal on at each of said holding point points, and

c) outputting an addition result as an analog output signal,

i ii) a peak detecting portion for deciding a timing to take said signal according to a peak of said analog output signal; and

iii) a second sampling and holding circuit for holding the analog input signal only on said timing to take said signal; and

ii iv) an A/D converter for converting said analog output signal into a digital signal, comprising:

a) a second sampling and holding circuit for holding a signal only on said timing to take said signal, and

b) a quantizing portion for digitizing an output of said second sampling and holding circuit.

2. A filter circuit for communication as claimed in claim 1, wherein said second sampling and holding circuit comprises:

i) a plurality of third sampling and holding circuits corresponding to a plurality of peaks ;

ii) a plurality of switches for alternatively outputting one of outputs of said third sampling a and holding circuits or a reference voltage; and

iii) a controller for controlling a holding timing of said third sampling and holding circuits and a timing of opening and closing of said switches.