A semiconductor integrated circuit of registers and combinational logic circuits connected between the registers is generated by a top-down design technique. When performing the logic synthesizing of such a semiconductor integrated circuit by making use of data of register transfer level, a combinational logic circuit with a critical path is driven with power from a high-voltage source, a combinational logic circuit without a critical path is driven with power from a low-voltage source, and a level converter capable of converting an input signal of low voltage level into a high-voltage-level output is arranged in a register located upstream of a combinational logic circuit with a critical path. Compared with a technique in which only critical paths are driven with power from a high-voltage source, it becomes easier to determine where to arrange level converters. Additionally, the number of level converters required can be reduced, thereby facilitating design work. Each combinational logic circuit with a critical path is driven by the high-voltage source, so that the power consumption increases in comparison with a case where only critical paths are driven by the high-voltage source. However, the ratio of the number of combinational logic circuits with a critical path to the total number of combinational logic circuits contained in the whole semiconductor integrated circuit is negligible, and other combinational logic circuits without a critical path are driven by the low-voltage source. The entire power consumption of the semiconductor integrated circuit can be reduced.
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0. 20. A semiconductor integrated circuit according to any of claims 13, 15, 18, and 19 wherein:
said level converter is formed by two PMOS transistors and two NMOS transistors; one of said two PMOS transistors has a gate and a drain, said gate and said drain respectively being connected with a drain and a gate of the other PMOS transistor, and sources of said two PMOS transistors are connected to the high-voltage source; one of said two NMOS transistors has a gate at which one of a pair of complementary signals from said slave latch is applied, and the other NMOS transistor has a gate at which the other of said pair of complementary signals is applied, and drains of said two NMOS transistors are connected to the drains of said two PMOS transistors, and sources of said two NMOS transistors are connected to ground; and a potential at each of the drains of said two NMOS transistors is provided in the form of a signal.
0. 1. A logic synthesis method for synthesizing, based on connection information of logic cells, a semiconductor integrated circuit of a plurality of registers and a plurality of combinational logic circuits connected between said registers, said logic synthesis method comprising:
a first step for mapping, when there exists among said plural combinational logic circuits a combinational logic circuit with a signal propagation delay time below a design delay upper limit, such a combinational logic circuit into a combinational logic circuit of a first type driven by a low-voltage source, and for mapping, when there exists among said plural combinational logic circuits a combinational logic circuit with a signal propagation delay time above the design delay upper limit, such a combinational logic circuit into a combinational logic circuit of a second type driven by a high-voltage source; a second step for determining which of said combinational logic circuits of the first type outputs to a combinational logic circuit of the second type and for remapping a combinational logic circuit of the first type, determined to output to a combinational logic circuit of the second type, into the second-type; and a third step for determining which of said registers generates a signal to a combinational logic circuit of the second type, for mapping a register, determined to generate a signal to a combinational logic circuit of the second type, into a register driven by the high-voltage source, and for mapping a register, determined not to generate a signal to a combinational logic circuit of the second type, into a register driven by the low-voltage source.
0. 10. A semiconductor integrated circuit having a plurality of registers and a plurality of combinational logic circuits connected between said registers wherein:
part of said plural combinational logic circuits are formed by respective combinational logic circuits of a first type driven by a low-voltage source and the remaining part of said plural combinational logic circuits are formed by respective combinational logic circuits of a second type driven by a high-voltage source; and of said plural registers a register that has a combinational logic circuit of the first type on its input side and a combinational logic circuit of the second type on its output side is a circuit that has a temporary data storage driven by the low-voltage source and a level converter which is driven by the high-voltage source and which converts a low-voltage-level output signal, received from said temporary data storage, into a high-voltage-level output.
0. 21. A semiconductor integrated circuit according to any of claims 13, 15, 18, and 19 wherein said level converter includes two PMOS transistors and two CMOS inverters;
each said CMOS inverter being formed by a PMOS transistor and an NMOS transistor connected in series wherein gates of said PMOS and NMOS transistors together serve as an input terminal and an in-series connection between said PMOS transistor and said NMOS transistor serves as an output terminal; said input terminal of one of said two CMOS inverters being fed one of a pair of complementary signals from said slave latch, and said input terminal of the other CMOS inverter being fed the other of said pair of complementary signals from said slave latch; said two PMOS transistors having drains connected to sources of said PMOS transistors of said CMOS inverters, and said sources being connected to the high-voltage source; sources of said NMOS transistors of said two CMOS inverters being connected to ground; said output terminal of each said CMOS inverter being connected to a gate of a PMOS transistor not connected in series therewith; and a potential at each of said output terminals of said two CMOS inverters being provided in the form of a signal.
0. 24. A semiconductor integrated circuit comprising:
a first logic gate driven by a low-voltage source; a plurality of second logic gates driven by a high-voltage source; at least one of said plurality of second logic gates having multiple input ports for receiving distinct input signals; and a register adapted to receive a clock input, said register having an input port and an output port, said input port being coupled to said first logic gate and said output port being coupled to said plurality of second logic gates, said plurality of second logic gates forming a critical path, said register having level conversion means which receives and stores a low-voltage output signal from said first logic gate, converts the level of the stored low-voltage output signal into a level of a high-voltage signal and then outputs the high-voltage signal to said plurality of second logic gates.
0. 33. A semiconductor integrated circuit comprising a plurality of combinational circuits, each of said combinational circuits having one signal propagation path contained within said combinational circuit,
said plurality of combinational circuits including a first combinational circuit utilizing a low-voltage source as a voltage source thereof, and a second combinational circuit utilizing a high-voltage source as a voltage source thereof, wherein, the signal propagation paths contained in said second combinational circuit and a predetermined combinational circuit other than said first and second combinational circuits, share a portion, so that said second combinational circuit and said predetermined combinational circuit have at least one logic gate in common, said second combinational circuit and predetermined combinational circuit each providing a separate input to said common logic gate, each of said predetermined combinational circuit and said second combinational circuit includes at least one logic gate other than said common logic gate, which is disposed on a portion of the signal propagation path other than said portion shared by the signal propagation paths of said predetermined combinational circuit and said second combinational circuit, and at least said common logic gate and said portion shared by the signal propagation paths of said predetermined and second combinational circuits are driven by the high-voltage source.
0. 2. A logic synthesis method according to
evaluating a sum of a signal propagation delay time of a combinational logic circuit and a signal propagation delay time of a register driven by the low-voltage source; and mapping, when there exists a combinational logic circuit with respect to which said evaluation step yields a result below the design delay upper limit, such a combinational logic circuit into the first type, and mapping, when there exists a combinational logic circuit with respect to which said evaluation step yields a result above the design delay upper limit, such a combinational logic circuit into the second type.
0. 3. A logic synthesis method according to
mapping each said combinational logic circuit into the first-type; determining which of said combinational logic circuits has a signal propagation delay time above the design delay upper limit, and mapping a combinational logic circuit of the first type, determined to have a signal propagation delay time above the design delay upper limit, into the second type.
0. 4. A logic synthesis method according to
determining whether said first-to-second type remapping creates a layout in which a combinational logic circuit of the first type gives its output to a combinational logic circuit of the second type, and repeatedly remapping, if there still exists a combinational logic circuit of the first type that outputs to a combinational logic circuit of the second type, such a combinational logic circuit of the first type into the second type.
0. 5. A logic synthesis method according to
0. 6. A logic synthesis method according to claim wherein a net list describing logic cell connection information is input, and said logic cell connection information of said first step is generated from said input cell connection information.
0. 7. A logic synthesis method according to
0. 8. A logic synthesis method according to any of claims 5-7 wherein said logic cell connection information based on said register-transfer-level design data, on said net list, or on said schematic is optimized, and said optimized logic cell connection information serves as said logic cell connection information of said first step.
0. 9. A logic synthesis method according to any of claims 1-4 further including a step after said third step for verifying each timing of said registers.
0. 11. A semiconductor integrated circuit according to
of said plural registers a register that has combinational logic circuits of the first type on its input and output sides and a register that has a combinational logic circuit of the second type on its input side and a combinational logic circuit of the first type on its output side are circuits which are driven by the low-voltage source and which do not contain said level converter; and of said plural registers a register than has combinational logic circuits of the second type on its input and output sides is a circuit which is driven by the high-voltage source and which contains said level converter for converting a low-voltage-level output signal, received from said temporary data storage, into a high-voltage-level output.
0. 12. A semiconductor integrated circuit according to either
0. 13. A semiconductor integrated circuit according to
of said plural registers a register containing said level converter is formed by a flip-flop; said flip-flop including: a master latch and a slave latch which are driven by the low-voltage source and which are connected in series; an output buffer which is driven by the high-voltage source; and a level converter which is connected between said slave latch and said output buffer and which converts a low-voltage-level signal, received from said slave latch, into a high-voltage signal, to provide same to said output buffer.
0. 14. A semiconductor integrated circuit according to
of said plural registers a register not containing said level converter is formed by a flip-flop; said flip-flop including: a master latch and a slave latch which are driven by the low-voltage source and which are connected in series; and an output buffer which is driven by the low-voltage source and which receives an output signal of said slave latch.
0. 15. A semiconductor integrated circuit according to
of said plural registers a register containing said level converter is formed by a latch; said latch including: a latch section which is driven by the low-voltage source; an output buffer which is driven by the high-voltage source; and a level converter which is connected between said latch section and said output buffer and which converts a low-voltage-level signal, received from said latch section, into a high-voltage signal, to provide same to said output buffer.
0. 16. A semiconductor integrated circuit according to
of said plural registers a register not containing said level converter is formed by a latch; said latch including: a latch section which is driven by the low-voltage source; and an output buffer which is driven by the low-voltage source and which receives an output signal of said latch section.
0. 17. A semiconductor integrated circuit according to any of claims 10 and 11 wherein said plural registers are formed by respective flip-flops for scan testing.
0. 18. A semiconductor integrated circuit according to
a multiplexer which is driven by the low-voltage source and which selects one of a plurality of input data items according to an external control signal; a master latch and a slave latch which are driven by the low-voltage source, which receive signals from said multiplexer, and which are connected in series; an output buffer which is driven by the high-voltage source; and a level converter which is connected between said slave latch and said output buffer and which converts a low-voltage-level signal, received from said slave latch, into a high-voltage signal, to provide same to said output buffer.
0. 19. A semiconductor integrated circuit according to
a data input selector which is driven by the low-voltage source and which selects one of a plurality of input data items according to a clock signal; a master latch and a slave latch which are driven by the low-voltage source, which receive signals from said data input selector, and which are connected in series; an output buffer which is driven by the high-voltage source; and a level converter which is connected between said slave latch and said output buffer and which converts a low-voltage-level signal, received from said slave latch, into a high-voltage signal, to provide same to said output buffer.
0. 22. A semiconductor integrated circuit according to any of claims 10 and 11 wherein low and high voltages are provided from outside said semiconductor integrated circuit.
0. 23. A semiconductor integrated circuit according to any of claims 10 and 11 further including an area for input pads, and an internal core section within which a plurality of registers, a plurality of combinational logic circuits, and a memory cell section are arranged.
0. 25. The semiconductor integrated circuit of
0. 26. The semiconductor integrated circuit of
0. 27. The semiconductor integrated circuit of
0. 28. The semiconductor integrated circuit of
0. 29. The semiconductor integrated circuit of
0. 30. The semiconductor integrated circuit of
0. 31. The semiconductor integrated circuit of
0. 32. The semiconductor integrated circuit of
0. 34. The semiconductor integrated circuit of
0. 35. The semiconductor integrated circuit of
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This reissue application is a divisional of reissue application Ser. No. 09/076,703, filed on May 13, 1998, now U.S. Pat. No. RE37475, which was a reissue application of Ser. No. 08/375,413, filed on Jan. 18, 1995, which issued as U.S. Pat. No. 5,517,132.
This invention relates to a logic synthesis method for generating a semiconductor integrated circuit from data of register transfer level. This invention particularly pertains to a logic synthesis method for generating a low-power semiconductor integrated circuit and to a low-power semiconductor integrated circuit.
In recent years, a procedure known as a top-down design method has been used to lay out semiconductor integrated circuits. In the top-down design method, a targeted semiconductor integrated circuit is represented using functional descriptions of register transfer level (RTL). The processing of logic synthesis with the aid of RTL functional descriptions is carried out to generate targeted semiconductor integrated circuits.
The
When synthesizing a logic with the use of the
In a logic of
The power consumption P of the semiconductor integrated circuit can be found by:
where f is the operating frequency, C the load capacitance, and V the supply voltage. There are three ways of reducing the power consumption of the semiconductor integrated circuit. The first way is to reduce the operating frequency f. The second way is to reduce the load capacitance C. The third way is to reduce the supply voltage V. Of these three ways the third one is considered as the most effective way.
The third way, however, produces the problem that if the supply voltage is set low, this increases the delay time of a critical path that has the maximum delay time among a great many paths together forming a logic circuit.
With a view to providing a solution to the above-described problem, Japanese Patent Application, published under Pub. No. 5-299624,
Referring now to the accompanying drawing figures, a preferred embodiment of the present invention will be described below.
15 is a high-voltage source, e.g., a 3 V source, which is arranged outside. 16 is a low-voltage source, e.g., a 2 V source, which is also arranged outside. The image processor A has a high-voltage line 17 associated with the high-voltage source 15 and a low-voltage line 18 associated with the low-voltage source 16. In order to reduce the power consumption of the image processor A, the low-voltage source 16 serves as a voltage source for the first and second SICs 12 and 14 for image processing, and low voltage is applied through the low-voltage line 18 only to the first and second SICs 12 and 14. On the other hand, high-voltage is applied through the high-voltage line 17 to the ADC 10, to the DRAM 11, and to the micro computer 13. Since there is the need for increasing the interface voltages among the circuits 10-14, high voltage is also applied to the first and second SICs 12 and 14 via the high-voltage line 17.
The low-voltage source 16 may be an internal low-voltage source as a result of lowering the voltage of the high-voltage line 17 by its threshold voltage by means of an internal transistor. The structure of such an internal low-voltage source is shown in Japanese Patent Application, published under Pub. No. 4-96369, which eliminates the need for the provision of the low-voltage source 16.
The present invention is applied to functional blocks other than the functional block E, i.e., the functional blocks A, B, C, and D of the first SIC 12.
The functional block (i.e., a part of the SIC 12) as shown in
The flip-flops 2, 6, and 8 are 2 V flip-flops driven by the low-voltage source 16. The remaining flip-flop, i.e., the flip-flop 4, is a 2V/3 V flip-flop driven by both the low-voltage source 16 and the high-voltage source 15. The flip-flop 4 contains therein a level converter which will be described later. On the other hand, the flip-flops 2, 6, and 8 do not contain a level converter. The combinational logic circuits 1, 3, and 7 are 2 V combinational logic circuits driven by the low-voltage source 16 (i.e., the first-type combinational logic circuit). The combinational logic circuit 5, since it is required to operate at a high speed, is a 3 V combinational logic circuit driven by the high-voltage source 15 (i.e., the second-type combinational logic circuit).
9 is a 2 V clock buffer driven by the low-voltage source 16. This clock buffer 9 feeds a clock to each flip-flop 2, 4, 6, and 8.
The level converter 35 will be described in detail by making reference to
As described above, the flip-flop 2 has on its input and output sides the 2 V combinational logic circuits 1 and 3. In other words, the flip-flop 2 is formed by low-voltage (i.e., 2 V) circuits. On the other hand, the flip-flop 4 has the 2 V combinational logic circuit 3 on its input side and the 3 V combinational logic circuit 5 on its output side. In other words, the flip-flop 4 is formed by a low-voltage (i.e., 2 V) circuit and a high-voltage (3 V) circuit. The flip-flop 6 has the 3 V combinational logic circuit 5 on its input side and the 2 V combinational logic circuit 7 on its output side. In other words, the flip-flop 6 is formed by low-voltage circuits.
In the description above, each register r1, r2, r3, r4 is formed by a flip-flop, but they may be formed by a latch. Such a latch is illustrated in
Referring now to
The optimization section 63 has the following components: a state-transition-diagram optimization processing section 63a for optimizing a state transition diagram obtained; a state machine generator 63b for generating a circuit, i.e., a state machine, corresponding to the optimized state transition diagram; a timing-diagram comelier 63c for compiling a timing diagram obtained; a memory synthesis section 63d for the synthesizing of a memory according to memory specifications obtained; and an interface-section synthesis section 63e for the synthesizing of an interface section according to the compiled timing diagram and the synthesized memory. If the input section 61 inputs an RTL functional description, then the optimization section 63 performs, based on the obtained state machine, the obtained Boolean expression, and the synthesized interface section, the optimization of a logic in order to generate optimized logic cell connection information. On the other hand, if the input section 61 inputs either a net list or a schematic, then the optimization section 63 performs the optimization of a logic for the net list or the schematic. The optimization section 63 further has a logic optimization section 63f for generating connection information of a logic optimized.
The output section 67 provides either a net list representing the
The present invention pertains to the cell mapping section 64 as shown in FIG. 9. Cell mapping by means of the cell mapping section 64, i.e., an algorithm for the logic synthesizing of the
In a first procedure comprising steps S1 to S4, a combinational logic circuit, having a signal propagation delay time below a design delay upper limit, is mapped to a combinational logic circuit of a first type whose source of power is the low-voltage source 16. On the other hand, a combinational logic circuit, having a signal propagation delay time above the design delay upper limit, is mapped to a combinational logic circuit of a second type whose source of power is the high-voltage source 15.
The first procedure (S1-S4) proceeds as follows. In the first place, logic cell connection information is inputted from the logic optimization section 63f. Then, at step S1, by making use of signal propagation delay times of a 2 V flip-flop and a 2 V combinational logic circuit, a signal propagation delay time from the time a clock is inputted to an arbitrary flip-flop to the time data is inputted to the next-stage flip-flop is evaluated for every signal propagation path. Such an evaluation is made as follows. Information about logic circuits including AND, NOR, and NOT circuits (e.g., the type of logic, the number of inputs, and the number of logic stages) is extracted. Based on the extracted information as well as on the cell technology, a signal propagation delay time in mapping each logic into a cell is computed.
Step S2 determines whether or not the result of the evaluation is below the design delay upper limit. If found to be below the upper limit, then such a combinational logic circuit is mapped to a first-type combinational logic circuit stored in a low-voltage (2 V) logic cell library (hereinafter referred to as "lib") at step S3. On the other hand, if found to be above the upper limit, then the combinational logic circuit in question is mapped to a second-type combinational logic circuit stored in a high-voltage (3 V) logic cell library.
In a second procedure comprising steps S5 to S6, the following processing is executed. Step S5 determines whether or not there exists such an arrangement form that the output of a 2 V combinational logic circuit becomes the input of a 3 V combinational logic circuit. If step S5 says YES, then remapping is performed in order that the afore-said 2 V combinational logic circuit (i.e., the first-type combinational logic circuit) is replaced with a 3Vlib's combinational logic circuit (the second-type combinational logic circuit), at step S6.
Since what voltage-type of combinational logic circuits to be arranged on the input and output sides of a register has already been decided by the aforesaid logic synthesis, a third procedure comprising steps S7 to S9 is performed as follows. Checking is made to determine whether or not each register performs a level conversion from low to high voltage (i.e., from 2 V to 3 V). If the result is YES, then at step S8 a register (a flip-flop or latch), found to perform a low-to-high level conversion, is mapped into the
As described above, when some combinational logic circuits of the first type are found to have a signal propagation delay time above the design delay upper limit, these combinational logic circuits of the first type are mapped into combinational logic circuits of the second type of
A way of generating the
Next, at the second procedure (i.e., the combinational logic circuit remapping procedure), the combinational logic circuit 89 is remapped into a 3Vlib combinational logic circuit. Then, at the third procedure (i.e., the register (flip-flop) mapping procedure), the flip-flops 80, 81, 82, 83, and 84 are mapped into 2 V/3 V flip-flops while on the other hand the other flip-flops are mapped into 2 V flip-flops.
In the
The
The present invention has been described in terms of the functional block A. The present invention may be applied to the remaining functional blocks, i.e., the functional blocks B-D. The present invention may be applicable between the functional blocks A-D.
In accordance with the logic synthesis of the present invention, each combinational logic circuit with a critical path is designed in such a way as to receive drive power from the 3 V high-voltage source, and a level converter is arranged within a register provided upstream of such a critical-path-contained combinational logic circuit. This eliminates the need for individually determining where to place a level converter within a combinational logic circuit with a critical path when driving a critical path by the high-voltage source. Additionally, the number of level converters required can be reduced, therefore facilitating the SIC design work. Further, although each combinational logic circuit with a critical path is driven by power from the high-voltage source 15, the number of combinational logic circuits with a critical path is low in comparison with the total number of combinational logic circuits contained in the SIC. Therefore, the increase in power consumption is controlled, and the remaining combinational logic circuits without a critical path are driven by power from the low-voltage source 16, whereupon the entire SIC consumes less power. Low power SICs can be realized.
The
In the
In the present invention, two power sources, i.e., the low-voltage source 16 and the high-voltage source 15, are provided. The combinational logic circuit 3 without a critical path and the combinational logic circuit 5 with a critical path each have a signal propagation delay time of 18 ns, and delay from the time each flip-flop 2 and 4 receives a clock to the time each flip-flop 2 and 4 outputs data is 2 ns. Therefore, the maximum operating frequency of the SIC of the present embodiment is:
The same maximum operating frequency as accomplished by the conventional SIC can be obtained even when the combinational logic circuits 3 and 5 are driven by the low-voltage source 16.
Next, the conventional SIC and the present invention SIC are compared in power consumption. If the power consumption of the conventional SIC is P, a low- and high-voltage source (2 V and 3 V) are employed, the ratio of the critical path to the entire circuit is 10%, and an incremental power consumption due to a difference in circuit structure between the 2 V/3 V flip-flop of the present invention and the conventional flip-flop is 10%, then the power consumption of the SIC of the present invention is found by:
The present SIC consumes 49 percent less power than the conventional SIC.
If the ratio of the critical path to the entire circuit is 5%, then the power consumption of the SIC of the present invention is found by:
The present SIC consumes 52 percent less power than the conventional SIC.
Finally, the conventional SIC and the present invention SIC are compared in circuit size. If the circuit size of the conventional SIC is S, the ratio of the flip-flop to the entire SIC is 20%, the ratio of the critical path to the entire SIC is 10%, and an incremental area due to a difference in circuit structure between the 2 V/3 V flip-flop of the present invention and the conventional flip-flop is 10%, then the circuit size of the SIC of the present invention is found by:
The present SIC increases in size only by 0.2%.
If the ratio of the critical path to the entire circuit is 5%, then the circuit size of the SIC of the present invention is found by:
In this case, the present SIC increases in size only by 0.1%.
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