A variable frequency ring oscillator is controlled by a control signal and has an odd number of cascaded inverting gates. The inverting gates each have input terminals receiving an input signal. Except for the first of the cascaded inverting gates, each input signal on a gate is the output from the preceding inverting gate. The input terminal of the first of the inverting gates receives the output of the last of the inverting gates. At least one inverting gate is a cell having a gain variable as a function of a control signal. An output signal ext of the circuit is an inversion of an input signal inp and has a hysteresis that is a function of a control signal cont. The term "hysteresis" as used herein signifies, for example, a variable frequency signal remaining substantially in its current state for a certain length of time after which the variable frequency signal changes state with a magnitude that is a function of a control signal, upon change of state of an input signal.
|
0. 10. A cell for obtaining an output signal (ext) with a variable delay τ in response to an input signal (inp), the output signal (ext, ext') being connected to a control circuit having a control signal applied thereto for controlling a temporal profile of the output signal (ext), comprising:
an inverting amplifier having a gain controlled by a control signal (contr, contr'), wherein the output signal (ext) is inversely related to the value of the gain so as to cause the output signal (ext, ext') to remain substantially in its current logic state for a certain length of time after which the output signal (ext,ext') changes its logic state with a magnitude that is a function of the control signal (contr, contr') after a change of state of the input signal (inp).
0. 1. A process for obtaining a variable frequency output signal (U) from an oscillator having an odd number of serially connected inverter cells (16, 14, 15) comprising:
applying an input signal (en) having a logic state to a first inverter cell (16) of said serially connected inverter cells (16, 14, 15), said first of said serially connected inverter cells having a first output with a logic state which is inverted relative to the logic state of said input signal (en); receiving at each of said inverter cells (14, 15) successive to said first of said serially connected inverter cells (16, 14, 15) an input signal (inp, inp') having a logic state corresponding to a logic state of an output of a preceding one of said serially connected inverter cells (16, 14, 15) to provide an inverted output signal (ext, ext') at each of said serially connected inverter cells; feeding back the inverted output signal (ext, ext') of each of said inverter cells (14, 15) successive to said first of said serially connected inverter cells (16, 14, 15) to a corresponding control circuit and applying to said corresponding control circuit, a control signal (contr, contr') to derive from each control circuit a temporal profile of the output signal (ext, ext') which is applied to the corresponding inverter cell for delaying the output signal (ext, ext'), said delayed output signal having a delay T which is of a magnitude that is a function of the control signal (contr, contr'), wherein after a change in a value of the input signal corresponding to a first logic state of the input signal (inp, inp') said output signal (ext, ext') tends to maintain a value corresponding to its preceding value for a certain length of time after which the value of said output voltage signal abruptly changes to a second value corresponding to the second logic state; and applying the inverted output of a last of said serially connected inverter cells (16, 14, 15) to an input of the first of said serially connected inverter cells (16, 14, 15); and whereby the variable frequency output signal (U) is obtained from the first inverter cell of said serially connected inverter cells (16, 14, 15).
0. 25. A variable delay cell comprising:
an input for receiving an input signal, an output for providing an output signal with a variable delay in response to said input signal, a gain variable as a function of an analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal, one inverter connected between a high-potential node and a low-potential node and having an input connected to said input of the cell and an output node providing said output signal, a first p-type transistor having a drain connected to said high-potential node, a source connected to a fixed potential higher than the potential of said high-potential node and a gate connected to receive said analog control signal, and a second p-type transistor having a drain connected to a fixed potential equal to or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node.
0. 23. A variable delay cell comprising:
an input for receiving an input signal, an output for providing an output signal with a variable delay in response to said input signal, a gain variable as a function of an analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal, one inverter connected between a high-potential node and a low-potential node and having an input connected to said input of the cell and an output node providing said output signal, a first n-type transistor having a drain connected to said low-potential node, a source connected to a first fixed potential lower than the potential of said low-potential node, and a gate connected to receive the analog control signal, and a second n-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node.
0. 28. A variable delay cell comprising:
an input for receiving an input signal, an output for providing an output signal with a variable delay in response to said input signal, a gain variable as a function of a digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal, said digital control signal having bits, one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a plurality of first p-type transistors having drains connected to said high-potential node, sources connected to a fixed potential higher than the potential of said high-potential node and gates connected to receive the respective bits of the digital control signal, and a second p-type transistor having a drain connected to a fixed potential equal to or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node.
0. 26. A variable delay cell, comprising:
an input for receiving an input signal, an output for providing an output signal with a variable delay in response to said input signal, a gain variable as a function of a digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of the cell in response to predetermined steep edges of said input signal, said digital control signal having bits, one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a plurality of first n-type transistors having drains connected to said low-potential node, sources connected to a first fixed potential lower than the potential of said low-potential node, and gates connected to receive the respective bits of the digital control signal, and a second n-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node.
0. 19. A ring oscillator having a variable frequency controlled by an analog control signal, comprising an odd number of cascaded inverting gates,
each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and at least one inverting gate being constituted by a cell having a gain that is variable as a function of the analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including: one inverted connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a first p-type transistor having a drain connected to said high-potential node, a source connected to a first fixed potential higher than the potential of said high-potential node and a gate connected to receive the analog control signal, and a second p-type transistor having a drain connected to a fixed potential equal to or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node.
0. 17. A ring oscillator having a variable frequency controlled by an analog control signal, comprising an odd number of cascaded inverting gates,
each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and at least one inverting gate being constituted by a cell having a gain that is variable as a function of the analog control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including: one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a first n-type transistor having a drain connected to said low-potential node, a source connected to a first fixed potential lower than the potential of said low-potential node, and a gate connected to receive the analog control signal, and a second n-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node. 0. 22. A ring oscillator having a variable frequency controlled by a digital control signal in digital form having bits, comprising an odd number of cascaded inverting gates, each inverting gate having an input connected to receive an input signal which, except
for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and at least one inverting gate being constituted by a cell having a gain that is variable as a function of the digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including: one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a plurality of first p-type transistors having drains connected to said high-potential node, sources connected to a fixed potential higher than the potential of said high-potential node and gates connected to receive the respective bits of the digital control signal, and a second p-type transistor having a drain connected to a fixed potential equal or lower than the potential of said low-potential node, a source connected to said high-potential node and a gate connected to said output node. 0. 20. A ring oscillator having a variable frequency controlled by an analog control signal in digital form having bits, comprising an odd number of cascaded inverting gates,
each inverting gate having an input connected to receive an input signal which, except for the first of the cascaded inverting gates, corresponds to an output signal derived from a preceding inverting gate, the input of the first inverting gate being connected to receive the output signal of the last inverting gate, and at least one inverting gate being constituted by a cell having a gain that is variable as a function of the digital control signal for causing the output signal to remain substantially in its current logic state for a certain length of time after which the output signal abruptly changes to a logic state with a steep leading edge at the output of said at least one inverting gate in response to predetermined steep edges at the input of said at least one inverting gate, the cell including: one inverter connected between a high-potential node and a low-potential node and having an input connected to receive said input signal and an output node providing said output signal, a plurality of first n-type transistors having drains connected to said low-potential node, sources connected to a first fixed potential lower than the potential of said low-potential node, and gates connected to receive the respective bits of the digital control signal, and a second n-type transistor having a drain connected to a second fixed potential equal or higher than the potential of said high-potential node, a source connected to said low-potential node and a gate connected to said output node. 0. 2. The process for obtaining a variable frequency signal (U) according to
0. 3. A variable frequency oscillator operatively controlled by a control signal (contr, contr') comprising an odd number of cascaded inverting cells (14, 15, 16), a first inverting cell having an input connected to receive an input signal, each succeeding inverting cell of the cascaded inverting cells (14, 15, 16) having an input connected to receive an output signal (ext, ext') derived from a preceding inverting cell, the output signal (ext, ext') being connected to a control circuit (17, 18) having a control signal applied thereto for controlling a temporal profile of the output signal (ext, ext'), the input of the first inverting cell (16) being connected to receive an output of the last cell (15) of the cascaded inverting cells, at least one inverting cell (14, 15) being constituted by a cell having a gain that is variable as a function of the control signal (contr, contr') applied to said at least one inverting cell (14, 15) for causing the output signal (ext ext') from said at least one inverting cell (14, 15) to remain substantially in its current logic state for a certain length of time after which the output signal (ext, ext') from said at least one inverting cell abruptly (14, 15) changes to a logic state with a steep leading edge at the output of said at least one inverting cell (14, 15) for a change in logic state at the input of said at least one inverting cell (14, 15).
0. 4. The variable frequency oscillator according to
an inverting amplifier (1, 2) fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first transistor (3) having a source, drain and gate, the source being connected to a fixed potential lower than the potential of the low-potential node (5), the drain being connected to the low-potential node (5) and the gate being at the potential of the control signal (contr) in analog form, and a second transistor (12) having a source, drain and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential (5) and the gate being at the potential of the output node (4) such that the second transistor (12) conducts a current when the output node (4) is at a potential higher than the low-potential node (5).
0. 5. The variable frequency oscillator according to
an inverting amplifier (1, 2) fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first transistor (7) having a source, drain and gate, the source being connected to a fixed potential higher than the potential of the high-potential node (6) and the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a second transistor (11) having a source, drain and gate, the drain connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the second transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6).
0. 6. The variable frequency oscillator according to
a third transistor (7) having a source, drain and gate, the source being connected to a fixed potential higher than the potential of the high-potential node (6) and the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a fourth transistor (11) having a source, drain and gate, the drain connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the fourth transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6).
0. 7. The variable frequency oscillator according to
an inverting amplifier (1, 2) connected to be fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first plurality of transistors (31, 32, 33, 34) each having a source, drain and gate, the sources being connected to a fixed potential lower than the potential of the low-potential node (5), the drains being connected to the low-potential node (5) and each of whose rates is at a high or low potential of a bit of the control signal (contr) in digital form, and a second transistor (12) having a source, drain and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential node (5) and the gate being at the potential of the output node (4).
0. 8. The variable frequency oscillator according to
an inverting amplifier (1, 2) connected to be fed by a high-potential node (6) and a low-potential node (5), the output of which is constituted by an output node (4), a first plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6) and each of whose gates is adapted to be connected to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a second transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4).
0. 9. The variable frequency oscillator according to
a third plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6) and each of whose gates is adapted to be connected to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a fourth transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4).
0. 11. The cell according to
the inverting amplifier (1, 2) being connected to be fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first transistor (3) having a source, drain and gate, the source connected to a fixed potential lower than the potential of the low-potential node (5) the drain being connected to the low-potential node (5), and the gate adapted to be maintained at the potential of the control signal (contr) in analog form, and a second transistor (12) having a drain, source and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential node (5) and the gate being at the potential of the output node (4) such that the second transistor (12) conducts a current when the output node (4) is at a potential higher than the low-potential node (5).
0. 12. The cell according to
the inverting amplifier (1, 2) being connected to be fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first transistor (7) having a source, drain and gate, the source being connected to a fixed potential greater than the potential of the high-potential node (6), the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a second transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the second transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6).
0. 13. The cell according to
a third transistor (7) having a source, drain and gate, the source being connected to a fixed potential greater than the potential of the high-potential node (6) and the drain being connected to the high-potential node (6) and the gate being at the potential of the control signal (contr) in analog form, and a fourth transistor (11) having a source, drain and gate, the drain connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4) such that the fourth transistor (11) conducts a current when the output node (4) is at a potential lower than the high-potential node (6).
0. 14. The cell according to
the inverting amplifier (1, 2) being fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first plurality of transistors (31, 32, 33, 34) each having a source, drain and gate, the sources being connected to a fixed potential lower than the potential of the low-potential node (5), the drains being connected to the low-potential node (5) and each gate being at a high- or low-potential of a bit of the control signal (contr) in digital form, and a second transistor (12) having a source, drain and gate, the drain being connected to a fixed potential higher than the potential of the high-potential node (6), the source being connected to the low-potential node (5) and the gate being at the potential of the output node (4).
0. 15. A cell according to
the inverting amplifier (1, 2) being fed by a high-potential node (6) and a low-potential node (5), and having an output node (4) for supplying an output signal (ext), a first plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6), and each of the gates is adapted to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a second transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the being at the potential of the output node (4).
0. 16. A cell according to
a third plurality of transistors (71, 72, 73, 74) each having a source, drain and gate, the sources being connected to a fixed potential higher than the potential of the high-potential node (6), the drains being connected to the high-potential node (6), and each of the gates is adapted to receive an inverted low- or high-potential of a bit of the control signal (contr) in digital form, and a fourth transistor (11) having a source, drain and gate, the drain being connected to a fixed potential lower than the potential of the low-potential node (5), the source being connected to the high-potential node (6) and the gate being at the potential of the output node (4).
0. 18. A ring oscillator according to
a first p-type transistor having a drain connected to said high-potential node, a source connected to said second fixed potential and a gate connected to receive a signal varying inversely to the analog control signal, and a second p-type transistor having a drain connected to said first fixed potential, a source connected to said high-potential node and a gate connected to said output node.
0. 21. The ring oscillator according to
a plurality of first p-type transistors having drains connected to said high-potential node, sources connected to said second fixed potential and gates connected to receive respective signals of the bits of the digital control signal, and a second p-type transistor having a drain connected to said first fixed potential, a source connected to said high-potential node and a gate connected to said output node.
0. 24. The variable delay cell according to
a first p-type transistor having a drain connected to said high-potential node, a source connected to said second fixed potential and a gate connected to receive a signal varying inversely to the analog control signal, and a second p-type transistor having a drain connected to said first fixed potential, a source connected to said high-potential node and a gate connected to said output node.
0. 27. The variable delay cell according to
a plurality of first p-type transistors having drains connected to said high-potential node, sources connected to said second fixed potential and gates connected to receive respective signals of the bits of the digital control signal, and a second p-type transistor having a drain connected to said first fixed potential, a source connected to said high-potential node and a gate connected to said output node.
|
1. Field of the Invention
The invention relates to a ring oscillator that performs a process for obtaining a variable frequency signal and variable frequency oscillators embodied by means of a loop comprising an odd number of inverting cells connected in series, some of which are variable delay cells. The control of the delay acts directly on the value of the frequency. Cells of this type can be used in other applications such as signal synchronization.
2. Description of Related Art
According to the prior art, a control signal can be used to cause the variation of a leading edge of an input signal to a cell for changing the state of the output signal of the cell at the change of state of the input signal. A steep leading edge makes it possible to obtain a short delay. A leading edge with a gradual slope makes it possible to obtain a longer delay. An oscillating signal is obtained whose semi-oscillation is equal to the sum of the delays of each cell. When it comes to obtaining high frequencies, for example higher than 1 GHz, cells of this type present a drawback, because it is difficult to reduce the number of cells in a loop, while maintaining a frequency variation range which is sufficient to eliminate the problems of manufacturing tolerances and deviations in voltage and temperature. In effect, a minimal number of inverting cells is required to guarantee that the output signal of a cell reaches an extreme low or high level before its input signal is inverted. The minimum period obtained with the addition of the intrinsic delays of each cell therefore limits the maximum frequency that can be obtained.
The object of the invention is to provide a ring oscillator which produces an associated high-frequency oscillation which is variable within an appreciable range.
In order to obtain a variable frequency signal of this type, the invention offers a process which loops an inverted signal to an input of an oscillator with a delay controlled by a control signal, characterized in that an inversion of the inverted signal has a hysteresis with a magnitude that is a function of the control signal.
The invention is also embodied in a variable delay cell wherein the transition time between two states is minimal, whatever the delay controlled within an appreciable range, for example spanning from 1 to 16.
The invention offers a cell for obtaining a signal extracted with a variable delay from an input signal. An inverting amplifier having gain controlled by a control signal is used. Hysteresis is provided. The gain of the amplifier is controlled by feeding back the extracted signal, i.e., the output signal, so as to act on the gain of the amplifier thereby controlling the amplification of the input signal (inp).
Various refinements of the invention will emerge from the following description in reference to the figures.
The input signal inp introduced into the gate 21 is also introduced into a succession of two inverters 19, 20 so that it can externally output a signal U oscillating at the desired frequency.
The oscillator in
The transistors 1 and 2 are sized so as to have identical current-voltage characteristics. A value of the input signal inp close to the ground potential turns the transistor 1 on and the transistor 2 off. In the stable state, the node 4 is charged to a potential value equal to Vdd.
A value of the input signal inp close to the potential Vdd turns the transistor 1 off and the transistor 2 on. The value of the control signal contr is sufficiently positive for the transistor 3 to be on. In the stable state, the node 4 is discharged to a potential value equal to the ground potential.
When the input signal inp changes from a high value close to the potential Vdd to a low value close to the ground potential, the gate-source voltage of the transistor 1 becomes equal to its drain-source voltage, while the gate-source voltage of the transistor 2 turns off, thus turning off the transistor 2. A current is established between the drain and the source of the transistor 1 so as to charge the node 4 to a high potential value Vdd with a leading edge having a maximum rise f1 which is a function of the current-voltage characteristics of the transistor 1, essentially in the unsaturated state. For a low value of the input signal inp, the output signal ext reaches a high value. Thus, it is noted that the transistors 1 and 2 behave like an inverting amplifier whose transfer function of the first order is comparable in the first sequence to a minimal time constant filter τ1.
When the input signal inp changes from a value close to the ground potential to a value close to the potential Vdd, the grid-source voltage Vgs of the transistor 1 turns off, thus turning off the transistor 1, while the gate-source voltage Vgs of the transistor 2 becomes equal to its drain-source voltage Vds, placing the transistor 2 in an on state which is essentially unsaturated. Although the drain-source voltage Vds of the transistor 3 is substantially higher than the potential value of the control signal contr, the transistor 3 is in the saturated state and applies a current between the drain and the source of the transistor 2 as a function of its current-voltage characteristic for a given gate-source voltage, that is, a function of the value of the control signal contr. This has the effect of discharging the node 4 to a low potential value following a voltage ramp until the transistor 3 is desaturated. The node 4 then continues to discharge in order to reach the ground potential value with a residual time constant τ2. For a high value of the input signal inp, the output signal ext reaches a low value. The transistors 1, 2 and 3 behave like an inverting amplifier whose transfer function is comparable at the start of switching to a ramp. For values of the control signal contr close to Vdd, the transistor 3 does not function practically in the saturated state and the transfer function is of the first order comparable to a minimal time constant filter with a magnitude of τ1. The lower the value of the control signal contr, the lower the saturation current of the transistor 3, and thus the longer the ramped part and the more gradual the slope. The output signal ext has, on descent, a delay τ relative to the rise of the input signal inp. The delay τ is even more substantial the more gradual the slope of the ramp, that is, the weaker the control signal contr. Thus it is noted that it is possible to act on the delay of the cell in
By connecting the source of the transistor 2 directly to the ground and replacing the transistor 3 with a PMOS transistor having identical current-voltage characteristics between the source of the transistor 1 and the potential Vdd, for the sake of operational symmetry, a delay τ of the output signal ext at its rise would be observed relative to the descent of the input signal inp. It would then be possible to obtain a delay τ that varies according to the value of the control signal contr that is the delay is shorter the closer the value of the control signal contr on the gate of this PMOS transistor is to the ground potential, or longer, the closer the value of the control signal contr on the gate of this PMOS transistor is to the potential Vdd.
The two circuits proposed in the model in
Since the gate-source voltages of the transistors 7 and 9, applied by the node 8, are identical, the drain-source current of the transistor 7 in the on state is the image of the drain-source current of the transistor 9. The potential of the node 8 is naturally established at an operating point such that the drain-source current of the transistor 9 is equal to the drain-source current of the transistor 10. By sizing the transistors 9 and 10 so that they have similar current-voltage characteristics, a current behavior is obtained which is a function of the control signal contr and the drain-source voltage, which is identical for the transistors 3 and 7. Thus the same ramped part, and therefore the same delay τ, is observed on the rise as on the descent of the output signal ext, relative to the descent or the rise of the input signal inp.
The cell in
The operation of the transistors 3 and 12 will be better understood with the aid of
A steep leading edge of the change of the input signal inp to the potential Vdd, which is higher than the potential of the node 5, causes a rapid turn-on of the transistor 2 in the unsaturated state and the turn-off of the transistor 1. In this case, the high value of the control signal contr causes the transistor 3 to remain on its characteristic curve at Vgsmax. Two operating states of the transistor 12 can be seen in FIG. 8.
In the first state R1, the turn-on of the transistor 2 has the effect of causing the flow of a current I2 which is added to the current I12 of the transistor 12 so as to obtain the current I5. This has two effects. A first effect increases the voltage Vds3 of the transistor 3 in order to absorb the additional current I2. The operating points have a tendency to move toward the left of the figure. The second effect reduces the voltage of the node 4 and changes the transistor I2 to the characteristic curve of the state R1 by reducing its voltage Vgs. However, as seen in the figure, the current I2 equal to I5-I12 remains weak and the node 4 discharges slowly, remaining at a potential level close to Vdd. The operating points of the transistor 12 remain on characteristic curves close to that of Vgsmax by slightly reducing the current I12. The transistor 12 therefore causes an inverse feedback which acts in opposition to the potential reduction of the node 4. The result of this is to keep the extracted or output signal ext close to the high value.
In the second state R2, the change of the transistor 12 to lower characteristic curves of Vgs is accelerated. The tendency to move the operating points to the left reverses. The placing into saturation of the transistor 12 causes an avalanche effect which abruptly moves the operating points to the right, rapidly changing the voltage Vdd to the voltage Vds12 until the transistor 12 turns off.
The operating states presented in
A steep leading edge of the change of the input signal inp to the potential Vdd, which is higher than the potential of the node 5, causes a rapid turn-on of the transistor 2 in the unsaturated state and the turn-off of the transistor 1. In this case, the low value of the control signal contr causes the transistor 3 to remain at a practically constant current. Two operating states of the transistor 12 can be seen in FIG. 9.
In the first state R1, the turn-on of the transistor 2 has the effect of causing the flow of a current I2 which is added to the current I12 of the transistor 12 so as to obtain the current I5. This has two effects. A first effect increases the voltage Vds3 of the transistor 3 in order to absorb the additional current I2. The operating points have a tendency to be shifted to the left of the figure. The second effect reduces the voltage of the node 4 and changes the transistor 12 to the characteristic curve of the state R1 by reducing its voltage Vgs. However, as seen in the figure, the current I2 equal to I5-I12 remains weak and the node 4 discharges slowly, remaining at a potential level close to Vdd. The operating points of the transistor 2 remain on characteristic curves close to that of Vgsmax by slightly reducing the current I12. The transistor 12 then causes an inverse feedback which acts in opposition to the lowering of the potential of the node 4. This has the result of keeping the output signal ext close to the high value. The output signal ext is kept at its high value longer than in the example in
In the second state R2, the change of the transistor 12 to lower characteristic curves of Vgs accelerates more easily the nearer the latter are to the vicinity of the point 0 and the more preponderant the current I2 of the transistor 2 becomes relative to the current I12 of the transistor 12. The tendency to shift the operating points to the left is reversed. The placement into saturation of the transistor 12 causes an avalanche effect which abruptly shifts the operating points to the right, rapidly changing the voltage Vdd to the voltage Vds12 until the transistor 12 turns off.
The operating states presented in
For the sake of symmetry, the behavior of the transistors 1, 7 and 11 for the change of the output signal ext from the low state to the high state is identical to the behavior of the transistors 2, 3 and 12 for the change of the output signal ext from the high state to the low state. The explanations below remain valid when dealing with the characteristic curves for PMOS transistors, replacing the node 5 with the node 6 and the voltages Vds3, Vds12 with Vds7, Vds11.
In the preceding,
In a simplified way, the teaching of the preceding is the following. The change of the input signal inp from the low state to the high state turns off the transistor 1 and turns on the transistor 2, which then discharges the node 4 to bring it to the potential of the node 5. The transistor 12 causes a reaction which acts in opposition to the lowering of the potential of the node 4 directly to the ground potential through the transistor 3. In a first phase, the potential of the node 5 remains close to the value Vi, while the potential of the node 4 remains high enough to keep the transistor 12 on. However, the lowering of the potential of the node 4 reduces the conductivity of the transistor 12, which contributes to the lowering of the potential of the node 5. In a second phase, the potential of the node 4 is no longer high enough to maintain the consequent conductivity of the transistor 12, and the lowering of the potential of the node 4 toward the ground potential accelerates, causing the turn-off of the transistor 12.
The reaction of the transistor 12 causes a break in the descending leading edge of the output signal ext like that observed with the cell in
For the sake of symmetry in
With the cell in
In order to increase the delay in the change of state of the output signal ext at the change of state of the input signal inp, the control signal contr increases the value of the resistance of the transistors 3 and 7. The reaction provided by the transistors 11 and 12 therefore increases due to their fixed resistance value whose ratio to that of the transistors 3 and 7 decreases. The output signal ext remains close to the extreme value of the initial state for a longer time before varying rapidly toward the extreme potential value of the final state. The output signal ext is thus at intermediate potential values between the extreme potential values for less time. The leading edge of the change of state remains steep, even for obtaining substantial delays.
A steep leading edge of the change of the input signal inp to the potential Vdd, which is higher than the potential of the node 5, causes a rapid turn-on of the transistor 2 in the unsaturated state and the turn-off of the transistor 1. In this case, the high value of the control signal contr' (all the bits at 1) causes all the transistors 31, 32, 33, 34 to remain at the linear characteristic curve in bold lines. Two operating states of the transistor 12 are shown in FIG. 11.
In the first state R1, the turn-on of the transistor 2 has the effect of causing the flow of a current I2 which is added to the current I12 of the transistor 12 so as to obtain the current I5(R1). This has two effects. A first effect increases the voltage Vds3 of the node 5 in order to absorb the additional current I2. The operating points have a tendency to shift to the left of the figure. The second effect reduces the voltage of the node 4 and changes the transistor 12 to characteristic curves such as the characteristic curve R1 shown in a bold line, by reducing its voltage Vgs. However, as seen in the figure, the current I2 equal to I5(R1)-I12 remains weak and the node 4 discharges slowly, remaining at a potential level close to Vdd. The operating points of the transistor 12 remain on characteristic curves close to that of Vgsmax by slightly reducing the current I12. The transistor 12 then causes an inverse feedback which acts in opposition to the lowering of the potential of the node 4. This has the result of keeping the output signal ext close to the high value.
In the second state R2, the change of the transistor 12 to lower characteristic curves of Vgs is accelerated. It is evident from the characteristic curve R2 shown in a bold line, which indicates the current I12, that the difference I5(R2)-I12, is increasing. The tendency to shift the operating points to the left is reversed. The placement into saturation of the transistor 12 causes an avalanche effect which abruptly shifts the operating points to the right, rapidly changing the voltage Vdd to the voltage Vds12 until the transistor 12 turns off. This has the effect of bringing the output signal ext to its low value following a steep leading edge.
The operating states presented in
A steep slope of the change of the input signal inp to the potential Vdd, which is higher than the potential of the node 5, causes a rapid turn-on of the transistor 2 in the unsaturated state and the turn-off of the transistor 1. Here, the low value of the digital control signal contr' causes all of the transistors 31, 32, 33, 34 to remain on the linear characteristic curve Ids(Vds3) shown in a bold line having a low guide coefficient. Two operating states of the transistor 12 can be seen in FIG. 12.
In the first state R1, the turn-on of the transistor 2 has the effect of causing the flow of a current I2 which is added to the current I12 of the transistor 12 so as to obtain the current I5. This has two effects. A first effect increases the voltage Vds3 between the ground potential and the node 5, in order to absorb the additional current I2. The operating points have a tendency to shift to the left of the figure. The second effect reduces the voltage of the node 4 and changes the transistor 12 to the characteristic curve of the state R1 by reducing its voltage Vgs. However, as seen in the figure, the current I2 equal to I5-I12 remains weak and the node 4 discharges slowly, remaining at a potential level close to Vdd. The operating points of the transistor 12 remain on characteristic curves close to that of Vgsmax by slightly reducing the current I12. The transistor 12 therefore causes an inverse feedback which acts in opposition to the lowering of the potential of the node 4. This has the result of keeping the output signal ext close to the high value. The output signal ext is kept at its high value longer than in the example in
In the second state R2, the change of the transistor 12 to lower characteristic curves of Vgs accelerates more easily the closer the latter are to the vicinity of the point 0 and the more preponderant the current I2 of the transistor 2 becomes relative to the current I12 of the transistor 12. The tendency to shift the operating points to the left is reversed. The placement into saturation of the transistor 12 causes an avalanche effect which abruptly shifts the operating points to the right, rapidly changing the voltage Vdd to the voltage Vds12 until the transistor 12 turns off. It is evident in
The operating states presented in
For the sake of symmetry, the behavior of the transistors 1, 71, 72, 73, 74 and 11 for the change of the output signal ext from the low state to the high state is identical to the behavior of the transistors 2, 31, 32, 33, 34 and 12 for the change of the output signal ext from the high state to the low state. The explanations above remain valid when dealing with the characteristic curves for PMOS transistors, by replacing the node 5 with the node 6 and the voltages Vds3, Vds12 with Vds7, Vds11 respectively.
In the preceding,
The delay of a cell 14, 15 is controlled by a control signal contr which uses a control circuit 17, 18 to control the temporal profile of the extracted signal for a variation on a steep leading edge of the input signal. This profile breaks down into two parts. A first hysteresis part H tends to keep the extracted signal in its preceding state. A second leading edge part F rapidly brings the extracted signal to its new state. The delay of the output signal (ext) is of a magnitude that is a function of the control signal (contr), wherein after a change in a value of the input signal corresponding to a first logic state of the input signal (inp), the output signal (ext) tends to maintain a voltage value corresponding to its preceding value for a certain length of time after which the value of the output voltage signal physically changes to a second value corresponding to the second logic state.
In the case of
In the case of
While the preferred forms and embodiments of the invention have been illustrated and described, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made without deviating from the inventive concept and spirit of the invention as set forth above, and it is intended by the appended claims to define all such concepts which come within the full scope and true spirit of the invention.
Patent | Priority | Assignee | Title |
11349456, | Jul 21 2017 | Texas Instruments Incorporated | Ultra-low energy per cycle oscillator topology |
8120435, | Apr 27 2005 | Semiconductor Energy Laboratory Co., Ltd. | PLL circuit and semiconductor device having the same |
8547179, | Apr 27 2005 | Semiconductor Energy Laboratory Co., Ltd. | PLL circuit and semiconductor device having the same |
Patent | Priority | Assignee | Title |
5063311, | Jun 04 1990 | Semiconductor Components Industries, LLC | Programmable time delay circuit for digital logic circuits |
5208557, | Feb 18 1992 | Texas Instruments Incorporated | Multiple frequency ring oscillator |
5250914, | Jun 26 1991 | NEC Corporation | Oscillation circuit operating with stable oscillation frequency at a specific low power-supply voltage |
5459437, | May 10 1994 | Integrated Device Technology, inc | Logic gate with controllable hysteresis and high frequency voltage controlled oscillator |
5481207, | Mar 18 1993 | MAGNACHIP SEMICONDUCTOR LTD | High speed, low power input/output circuit for a multi-chip module |
5491456, | Dec 08 1994 | Texas Instruments Incorporated | Oscillator compensated for improved frequency stability |
5525938, | Apr 30 1993 | SGS-THOMPSON MICROELECTRONICS LIMITED | Ring oscillator using current mirror inverter stages |
5621360, | Aug 02 1995 | Intel Corporation | Voltage supply isolation buffer |
5666088, | Mar 07 1995 | SGS-THOMSON MICROELECTRONICS S R L | Wide frequency range VCO with low jitter |
EP601780, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Sep 14 2001 | Bull S.A. | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Feb 27 2007 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Mar 05 2007 | ASPN: Payor Number Assigned. |
Feb 24 2011 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Oct 14 2006 | 4 years fee payment window open |
Apr 14 2007 | 6 months grace period start (w surcharge) |
Oct 14 2007 | patent expiry (for year 4) |
Oct 14 2009 | 2 years to revive unintentionally abandoned end. (for year 4) |
Oct 14 2010 | 8 years fee payment window open |
Apr 14 2011 | 6 months grace period start (w surcharge) |
Oct 14 2011 | patent expiry (for year 8) |
Oct 14 2013 | 2 years to revive unintentionally abandoned end. (for year 8) |
Oct 14 2014 | 12 years fee payment window open |
Apr 14 2015 | 6 months grace period start (w surcharge) |
Oct 14 2015 | patent expiry (for year 12) |
Oct 14 2017 | 2 years to revive unintentionally abandoned end. (for year 12) |