A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.

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Patent
   RE38387
Priority
Dec 22 1994
Filed
Aug 17 2001
Issued
Jan 13 2004
Expiry
Dec 22 2015
Inventors
Costa, Raf…
Assg.orig
STMicroele…
Assg.curr
STMicroele…
Entity
Large
Referenced by
0
References
3
Maint.:
all paid
DETAILED DESCRIPTION…
22. A method of processing operands in a data processing system comprising:
generating partial result bits for combinations of one bit of a first operand with one bit of a second operand;
complementing only partial result bits for a most significant bit of the first operand or a most significant bit of the second operand using NOR-NOR logic circuits when the first operand or the second operand represents a two's complement value, respectively; and
forming a composite result by combining the partial result bits, including any complemented partial result bits.
11. A multiplier circuit for multiplying a first number and a second number, the first number and the second number having plural bits, the multiplier circuit comprising:
a plurality of groups of logic circuits for providing partial products, each logic circuit having a first input terminal for receiving a bit of the first number, the bit of the first number applied to a group being a same bit, the same bit of the first number applied to a group being different for each group, each logic circuit having a second input terminal for receiving a bit of the second number, the bit of the second number being different for each second input terminal for the logic circuits in a group, all the logic circuits of one group and at least one logic circuit of each other group having NOR-NOR logic circuits and at least a third input terminal for receiving one of a first and second control signal and being enabled to perform a two's complement multiplication of bits applied to the first and second terminals in response to at least one of the first and second control signals, the two's complement multiplication including complementing the partial product of the most significant bit of either or both of the first number and second number when either or both of the first number and second number are in two's complement form, each logic circuit having an output terminal;
a combinatorial network coupled to the output terminals of the logic circuits for adding the partial products; and
a plurality of logic gating circuits for providing plural logic control signals to said combinatorial network, the logic gating circuits each having first and second input terminals coupled to receive the first and second control signals, the logic gating circuits each having an output terminal coupled to said combinatorial network.
1. A circuit for generating partial products from a first number and a second number, the first number and the second number having plural bits, the circuit comprising:
a first group of logic circuits configured to generate a partial product, the first group of logic circuits having a first input terminal coupled to receive a most significant bit of the first number and a second input terminal coupled to receive a most significant bit of the second number, said first group of logic circuits having a third input terminal coupled to receive a first control signal and a fourth input terminal coupled to receive a second control signal, said first group of logic circuits is enabled to complement the partial product of the most significant bit of the first number and the second number when the first control signal has one of a first and second logic states and the second control signal has an other of the first and second logic states;
a second group of NOR-NOR logic circuits configured to generate at least one partial product, the second group of logic circuits having a first input terminal coupled to receive a bit of the first number other than a most significant bit and a second input terminal coupled to receive a most significant bit of the second number, said second group having a third input terminal coupled to receive the second control signal, said second group of NOR-NOR logic circuits is enabled to complement the partial product of the most significant bit of the first number when the second control signal has a first logic state; and
a third group of NOR-NOR logic circuits configured to generate at least one partial product, the third group of logic circuits having a first input terminal coupled to receive a most significant bit of the first number and a second input terminal coupled to receive a bit of the second number other than a most significant bit, said third group having a third input terminal coupled to receive the first control signal, said third group of NOR-NOR logic circuits is enabled to complement the partial product of the most significant bit of the first number when the first control signal has a first logic state.
6. A monolithically integrated circuit device comprising: at least one multiplier circuit for receiving a first number having a plurality of bits in the form of n electric signals each having a predetermined logic value and a second number having a plurality of bits in the form of m electric signals each having a predetermined logic value wherein n and m are integer numbers with any desired values, the multiplier circuit providing a product of the first and second numbers in the form of electric signals, the multiplier circuit including:
a plurality of logic gating circuits, including m groups of NOR-NOR logic gating circuits, each logic gating circuit having at least first and second input terminals and an output terminal, each of said logic gating circuits configured to perform a logic multiplication of input electric signals, one of the m signals related to the second number being applied to the first input terminal of all the m logic gating circuits in one group, the signal being a different one for each group, and one of the n signals related to the first number being applied to the second input terminal of each of the m logic gating circuits in one group, the signal being a different one for each logic gating circuit in one group, all the logic gating circuits of one of the m groups and at least one logic gating circuit in each one of the other (m-1) groups having at least third and fourth input terminals for which electric command signals are applied, whereby each of said m logic gating circuits can be enabled to also carry out a type of multiplication operation of the signals applied to the first and second input terminals that includes complementing the partial product of the most significant bit of either or both of the first and second numbers when either or both of the first and second numbers are in two's complement form;
a combinatorial network coupled to the output terminals of said logic gating circuits for performing addition of the output signals from said plurality of logic gating circuits; and
first, second and third additional logic gating circuits each having at least first and second input terminals and an output terminal for supplying the combinatorial network with output signals for addition to the output signals from the other logic gating circuits.
2. A multiplier circuit for receiving a first binary number having plural bits in the form of n electric signals each having a logic value and a second binary number having plural bits in the form of m electric signals each having a logic value wherein n and m are integer numbers with any desired values, the multiplier circuit providing a product of the first and second numbers in the form of electric signals each having a logic value, the multiplier circuit comprising:
a plurality of logic gating circuits, each logic gating circuit having at least first and second input terminals and an output terminal, the plurality of logic gating circuits configured to generate partial products from the input electric signals, the plurality of logic gating circuits including m groups of NOR-NOR logic gating circuits, one of the m signals related to the second number being applied to the first input terminal of all the logic gating circuits in one group, the signal being a different one for each group, and one of the n signals related to the first number being applied to the second input terminal of each of the logic gating circuits in one group, the signal being a different one for each logic gating circuit in one group, all the logic gating circuits of one of the m groups and at least one logic gating circuit in each one of the other (m-1) groups having at least third and fourth input terminals for which electric command signals are applied, and the electric command signals are selectively applied to one of the first and second terminals of the remaining m groups of NOR-NOR logic circuits, whereby each of said m logic gating circuits can be enabled to complementing a partial product of a most significant bit of either and both of the first and second numbers when either and both of the signals applied to the first and second input terminals is in two's complement form;
a combinatorial network coupled to the output terminals of said logic gating circuits for performing addition of the output signals from said plurality of logic gating circuits; and
first, second and third additional logic gating circuits each having at least first and second input terminals and an output terminal for supplying the combinatorial network with output signals for addition to the output signals from the other logic gating circuits.
3. A multiplier circuit according to claim 2 wherein logic gating circuits with only two input terminals are of AND type, and the first, second, and third additional logic gating circuits are of OR, AND and exclusive OR types, respectively, and the predetermined logic values of the electric signals are of a first and a second type.
4. A multiplier circuit according to claim 2 wherein logic gating circuits having third and fourth terminals can be enabled to carry out a two's complement logic multiplication operation of signals applied to the first and second input terminals.
5. A multiplier circuit according to claim 4 wherein the logic gating circuit with third and fourth input terminals has the most significant bit signals of the two binary numbers applied to the first and second input terminals thereof is enabled to carry out a two's complement logic multiplication operation when the predetermined logic values of the electric signals applied to the third and fourth input terminals are of a first type and a second type, respectively, and further wherein logic gating circuits having third and fourth input terminals and the most significant bit signal of the first binary number applied to one of the first and second input terminals thereof are enabled to carry out a two's complement logic multiplication operation when an electric signal having a logic value of the first type is applied to their third input terminal and an electric signal of the second type is applied to their fourth input terminal, and further wherein logic gating circuits having third and fourth input terminals and the most significant bit signal of the second binary number applied to one of the first and second input terminals thereof, are enabled to carry out a two's complement logic multiplication operation when an electric signal of the first type is applied to their fourth input terminal.
7. A monolithically integrated circuit device according to claim 6 wherein the circuit device comprises a microprocessor.
8. A monolithically integrated circuit device according to claim 6 wherein the circuit device comprises a microcontroller.
9. A monolithically integrated circuit device according to claim 6 wherein the circuit device comprises an electrically erasable integrated memory.
10. A monolithically integrated circuit device according to claim 9 wherein the multiplier circuit performs a computation of scalar multiplication of two integer vectors.
12. A multiplier circuit according to claim 11 wherein a first group of NOR-NOR logic circuits that has at least a third input terminal has the first input terminal coupled to receive the most significant bit of the first number and the second input terminal coupled to receive the most significant bit of the second number, the third input being coupled to receive the first control signal, and further including a fourth input terminal being coupled to receive the second control signal.
13. A multiplier circuit according to claim 12 wherein said first group is enabled to perform a two's complement multiplication operation on the bits applied to the first and second input terminals when the first control signal has one of a first and second logic states and the second control signal has an other of the first and second logic states.
14. A multiplier circuit according to claim 11 wherein a second group of logic circuits that has at least a third input terminal has the first input terminal coupled to receive a bit of the first number other than a most significant bit and the second input terminal coupled to receive a most significant bit of the second number, the third input terminal being coupled to receive the second control signal.
15. A multiplier circuit according to claim 14 wherein said second group is enabled to perform a two's complement multiplication operation on the bits applied to the first and second input terminals when the second control signal has a first logic state.
16. A multiplier circuit according to claim 11 wherein a third group of logic circuits that has at least a third input terminal has the first input terminal coupled to receive a most significant bit of the first number and the second input terminal coupled to receive a bit of the second number other than a most significant bit, the third input terminal being coupled to receive the first control signal.
17. A multiplier circuit according to claim 16 wherein said third group is enabled to perform a two's complement multiplication operation on the bits applied to the first and second input terminals when the first control signal has a first logic state.
18. A multiplier circuit according to claim 11 wherein said plurality of logic gating circuits comprises first, second, and third logic gating circuits.
19. A multiplier circuit according to claim 18 wherein said first logic gating circuit comprises an AND gate.
20. A multiplier circuit according to claim 18 wherein said second logic gating circuit comprises an OR gate.
21. A multiplier circuit according to claim 18 wherein said third logic gating circuit comprises an exclusive OR gate.
23. A method according to claim 22, further comprising providing mode compensation bits for use in forming a composite result.
24. A method according to claim 23 wherein the act of providing mode compensation bits comprises providing three mode compensation bits.
25. A method according to claim 22 wherein the complementing only partial result bits further comprises generating an uncomplemented partial result bit for a combination of the most significant bit of the first operand and the most significant bit of the second operand when the first operand represents a two's complement value and the second operand represents a two's complement value.
26. A method according to claim 22 wherein the partial result bits represent an AND function of the operand bits.
27. A method according to claim 22 wherein the composite result represents a multiplicative product of the first and second operands.
DETAILED DESCRIPTION OF THE INVENTION

Many of the known multiplier circuits use factor re-coding techniques, such as Booth's algorithm, to provide high-performance capabilities.

Such re-coding techniques allow the multiplication operation to be greatly simplified in that they allow the number of the partial products entering the computation to be reduced preliminarily, thereby reducing the time required for the multiplication, or the physical size of the multiplier circuit.

In accordance with the invention, the multiplier circuit has instead an iterative structure of a standard type, which is matched to the four product types involved by appropriate logic circuits effective to serve functions of partial product complementing and of adding additive constants which are independent of the operands, using the so-called method of the additive constants for computing the product.

As previously stated, both factors may be natural numbers, two's complement numbers, or one may be a two's complement and the other a natural number.

It can at all events be shown that all the cases of the possible products for current devices, such as 8×16 bits or 16×16 bits, can be encompassed by one or more multiplications of 8×8 bits belonging to one of the following four types. The factors A and B are designated as follows:

A=a7a6a5a4a3a2a1a0

and

B=b7b6b5b4b3b2b1b0

a) 8×8 multiplication--where a7 and b7 have positive weight, and therefore, the partial products a0b0. . . a7b7 (designated X in the following charts) are added in the natural mode; the matrix of partial products has the following structure:
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X

Thus, the product of natural A and natural B will be a natural number.

b) 8×8 multiplication--where b7 has negative weight. In this case, those partial products which contain bit b7 should be complemented, and a suitable constant should be added to the result of the multiplication (elements to be complemented are underlined):
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
100000001

Thus, the product of natural A and relative B will be a relative number.

c) 8×8 multiplication--where a7 has negative and b7 positive weight. Here, it is the partial products which contain a7 that should be complemented. In view of the structure being symmetrical with the case b) above, the additive constant will be the same.
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
100000001

The product of relative A and natural B will, therefore, be a relative number.

d) 8×8 multiplication--where both a7 and b7 have negative weight. The partial products which contain a7 and b7 should be complemented except a7b7.

The additive constant will be the sum of the constants in the previous two cases b) and c).
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
X X X X X X X X
100000001

Thus, the product of relative A and relative B will be a relative number.

The example of the partial product matrix resulting in the instance of 8×8 bits, to which can be reduced as mentioned even the more complex cases of 8×16 bits and 16×16 bits, is in no way limiting.

The same method can be used for cases of m×n bits, where m and n are any selected integers.

Those elements which belong to the main diagonal of the partial product matrix should, therefore, be complemented if a multiplication of the c) or d) type is to be performed, while those in the bottom row should be complemented in the instance of a b) or d) operation. The matrix of partial products should, moreover, be added bits representing the additive constant. In the b) and c) cases, the additive constant is given by the following sequence of bits:

1000000100000000

and in the d) case by:

1000001000000000.

In the a) situation, the constant would be zero.

These considerations can be accounted for by introducing three bits, P, Q and S, into the partial product matrix in accordance with a scheme as shown here below:
E8 a6b0 a5b0 a4b0 a3b0 a2b0 a1b0 a0b0
E9 a6b1 a5b1 a4b1 a3 b1 a2b1 a1b1 a0b1
E10 a6b2 a5b2 a4b2 a3 b2 a2b2 a1b2 a0b2
E11 a6b3 a5b3 a4b3 a3 b3 a2b3 a1b3 a0b3
E12 a6b4 a5b4 a4b4 a3 b4 a2b4 a1b4 a0b4
E13 a6b5 a5b5 a4b5 a3 b5 a2b5 a1b5 a0b5
E14 a6b6 a5b6 a4b6 a3 b6 a2b6 a1b6 a0b6
E7 E6 E5 E4 E3 E2 E1 E0
P Q S

which represents the partial product matrix in its most general form, again for the preferred example with 8-bit numbers.

Shown in more detail in the two charts that follow is the value taken by the functions E0, E1, E2, . . . , E14, P, Q and S in each of the four cases, identified here by two bits X and Y.

X Y E0 E1 E2 E3 E4 E5 E6 E7
a 0 0 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 a7b7
b 0 1 {overscore (a0b7)} {overscore (a1b7)} {overscore (a2b7)} {overscore (a3b7)} {overscore (a4b7)} {overscore (a5b7)} {overscore (a6b7)} {overscore (a7b7)}
c 1 0 a0b7 a1b7 a2b7 a3b7 a4b7 a5b7 a6b7 {overscore (a7b7)}
d 1 1 {overscore (a0b7)} {overscore (a1b7)} {overscore (a2b7)} {overscore (a3b7)} {overscore (a4b7)} {overscore (a5b7)} {overscore (a6b7)} a7b7
X Y E8 E9 E10 E11 E12 E13 E14
a 0 0 a7b0 a7b1 a7b2 a7b3 a7b4 a7b5 a7b6
b 0 1 a7b0 a7b1 a7b2 a7b3 a7b4 a7b5 a7b6
c 1 0 {overscore (a7b0)} {overscore (a7b1)} {overscore (a7b2)} {overscore (a7b3)} {overscore (a7b4)} {overscore (a7b5)} {overscore (a7b6)}
d 1 1 {overscore (a7b0)} {overscore (a7b1)} {overscore (a7b2)} {overscore (a7b3)} {overscore (a7b4)} {overscore (a7b5)} {overscore (a7b6)}

These charts represent the truth table for the two's complement functions added to the partial product matrix, while the additive constant can be calculated as follows:

P=X+Y

Q=X·Y

S=X⊕Y

where the logic operations specified are of the OR, AND and EXOR types, respectively.

In a similar way to conventional multiplier circuits, the multiplier circuit of this invention includes a structure with logic gating circuits for receiving, in the form of electric signals having predetermined logic values, the two binary numbers which are to be multiplied together and for obtaining the partial products shown in the general matrix layout.

In the most general of cases, this structure includes m groups of n logic gating circuits, where m and n are the bits of the two binary numbers to be multiplied, which would usually have the same number of bits (m=n).

Such logic gating circuits have first and second input terminals for the electric signals and an output terminal which is connected to a combinatorial network for the final summing of the partial products.

Applied to the first input terminal of all the logic gating circuits in one group is one of the m electric signals which encode one of the two binary numbers.

The second input terminal of each logic gating circuit in one group instead receives one of the n electric signals which encode the other binary number, which signal would be a different one for each logic gating circuit in one group.

According to this invention, those logic gating circuits which receive electric signals corresponding to the most significant bits of the two binary numbers (at both, or at least one of, the first and second input terminals) and carry out the operations with two's complement function, as indicated in the matrix layout by the character E, also have at least a third input terminal and may even have a fourth input terminal.

These terminals receive, for all the logic gating circuits mentioned above, similar electric control signals having predetermined values, whereby each of the logic gating circuits can be enabled to also carry out a two's complement operation on the product of the signals applied to the first and second input terminals.

The logic gating circuits with two input terminals may be provided as standard logic AND circuits. However, the logic gating circuits with four input terminals may be implemented with differently if desired.

FIG. 1 shows an implementation of those logic gating circuits which provide the partial products with two's complement function, E0, E1, E2, E3, E4, E5 and E6. The logic gating circuit 1 of FIG. 1 has first, second, and third input terminals. First, input terminal receives a bit of the first number A to be multiplied. The logic gating circuit 1 providing partial product E0 receives bit a0 at the first input terminal; the logic gating circuit 1 providing partial product E1receives bit a1 at the first terminal A, and so on for the bits of the first number to be multiplied. For example, in an 8-bit number, the logic circuit 1 providing partial product E7 receives bit a7 at the first input terminal. On the other hand, the logic circuit 1 of FIG. 1 is coupled to receive bit b7 at the second input terminal regardless of the partial product provided. The logic circuit of FIG. 1 has a third input terminal coupled to receive bit Y.

The first input terminal is coupled to a first input terminal of NOR gate 2. The first input terminal is also coupled to an input terminal of a first inverter 4. The second input terminal is coupled to a first input terminal of a second NOR gate 6 and is also coupled to an input terminal of a second inverter 8. The third input terminal is coupled to an input terminal of a third inverter 10 and is also coupled to a first input terminal of a third NOR gate 12.

The output terminal of third inverter 10 is coupled to a second input terminal of first NOR gate 2 and to a second input terminal of second NOR gate 6. The output terminal of second inverter 8 is coupled to a second input terminal of third NOR gate 12, and the output terminal of first inverter 4 is coupled to a third input terminal of third NOR gate 12. The output terminals of first NOR gate 2, second NOR gate 6, and third NOR gate 12 are coupled to first, second and third input terminals of fourth NOR gate 14, respectively. The output terminal of fourth NOR gate 14 provides the partial product. When bit Y is high, i.e., a logic 1, the logic circuit 1 of FIG. 1 is enabled to perform a two's complement logic multiplication operation.

FIG. 2 shows an implementation of the logic gating circuit which provides E7. The logic circuit 15 of FIG. 2 has a first input terminal coupled to receive bit a7, a second input terminal coupled to receive bit b7, a third input terminal coupled to receive bit X, and a fourth input terminal coupled to receive bit Y. The first input terminal is coupled to a first input terminal of NAND gate 16, and the second input terminal is coupled to a second input terminal of NAND gate 16. The third input terminal is coupled to a first input terminal of exclusive NOR gate 18, and the fourth input terminal is coupled to a second input terminal of exclusive NOR gate 18. The output terminal of NAND gate 16 is coupled to a first input terminal of exclusive NOR gate 20, and the output terminal of exclusive NOR gate 18 is coupled to a second input terminal of exclusive NOR gate 20. The output terminal of exclusive NOR gate 20 provides the partial product of bits a7and b7. When bits X and Y have different logic values, i.e., bit X is low and bit Y is high, or bit X is high and bit Y is low, the logic circuit 15 of FIG. 2 is enabled to perform a two's complement logic multiplication operation.

FIG. 3 shows an implementation of those logic gating circuits which provide E8, E9, E10, E11, E12, E13 and E14. The logic circuit 21 of FIG. 3 has a first in terminal coupled to receive bit a7. A second input terminal is coupled to receive bits, to be multiplied with bit a7, as follows. The logic circuit 21 providing partial product E8 is coupled to receive bit b0. at the second input terminal. The circuit 21 providing partial product E9 receives bit b1 at the second input terminal. This pattern continues up to the circuit 21 for providing partial product E14, which receives bit b6 at input terminal B. A third input terminal is coupled to receive bit X.

The first input terminal is coupled to a first input terminal of first NOR gate 22, and to an input terminal of first inverter 24. The second input terminal is coupled to a first input terminal of second NOR gate 26 and is coupled to an input terminal of second inverter 28. Input terminal X is coupled to a first input terminal of third NOR gate 30, and is coupled to an input terminal of third inverter 32.

The output terminal of third inverter 32 is coupled to a second input terminal of first NOR gate 22, and to a second input terminal of second NOR gate 26. The output terminal of second inverter 28 is coupled to a second input terminal of third NOR gate 30, and the output terminal of first inverter 24 is coupled to a third input terminal of third NOR gate 30. The output terminals of first NOR gate 22, second NOR gate 26, and third NOR gate 30 are coupled to first, second, and third input terminal of fourth NOR gate 34, respectively. The output terminal of NOR gate 34 provides partial products E8, E9, E10, E11, E12, E13, and E14. The logic circuit of FIG. 3 is enabled to perform a two's complement logic multiplication operation when bit X is high, i.e., a logic 1.

A multiplier circuit according to the invention further includes first, second and third additional logic gating circuits, each having first and second input terminals and an output terminal.

Such additional circuits supply the combinatorial network with signals having a predetermined logic value, unrelated to the binary factors, for addition to the output signals from the other logic gating circuits.

The input terminals of the additional circuits receive the same signals as are applied to the third and fourth terminals of the logic gating circuits for the partial products with two's complement function.

The predetermined logic values of the control signals correspond to the bits X and Y in the above charts, and therefore, are associated with cases a), b), c) and d) of multiplication type.

The additional logic gating circuits are, as mentioned above, ordinary logic circuits of the OR, AND, and EXOR types. FIG. 4 shows the first additional logic gating circuit as OR gate 36. OR gate 36 is coupled to receive bit X at a first input terminal and bit Y at a second input terminal, and provides additive constant P at an output terminal of OR gate 36. FIG. 5 shows the second additional logic gating circuit as AND gate 38. AND gate 38 is coupled to receive bit X at a first input terminal and bit Y at a second input terminal, and provides additive constant Q at an output terminal. FIG. 6 shows third additional logic gating circuit as exclusive OR gate 40. Exclusive OR gate 40 is coupled to receive bit X at a first input terminal and bit Y at a second input terminal, and provides additive constant S at an output terminal.

The electric signals corresponding to the bits X and Y are generated by circuit means in the system which includes the multiplier circuit based upon a determination of either the natural or two's complement form of the binary operands.

FIG. 7 shows a combinatorial network 42 for combining the partial products supplied the logic gating circuits of FIGS. 1, 2, and 3, and the signals supplied by the additional logic gating circuits of FIGS. 4, 5, and 6. As can be seen, combinatorial network 42 includes 37 full adders FA and 5 half adders HA, and includes 4 cascade-connected stages of adders. The adders included in combinatorial network 42 are well known and will not be discussed in detail.

On applying the rules discussed above to the multiplier developed by Dadda, it will be appreciated that the changes made do not affect the delay in computation time. As regards the silicon area occupied, the increase is a modest one. In fact, both the number of the stages (four stages in cascade) and the total number of the adders (37 FAs plus 5 HAs instead of 35 FAs plus 7 HAs) may be left unchanged if the circuit is designed using a method similar to Dadda's .

It should be noted, however, that for the same partial product matrix and functions and additive constants as specified above, in designing a multiplier circuit according to this invention, the column compression portion can be implemented in any of several different ways.

For example, the integration area efficiency can be improved by a distribution of FAs and HAs which is as equal as possible among the various stages and a reduction in the number of interconnects. An example of such a combinatorial network is shown in FIG. 8. Combinatorial network 43 includes four stages of full adders FA and half adders HA. As can be seen, the lowest number of adders per stage is 9; the highest is 12. This distribution of adders is more equal than that of combinatorial network 42 of FIG. 7, in which the number of adders per stage varies between a low of 6 and a high of 4.

Shown in FIG. 9 is a block diagram for an application of a fast multiplier circuit according to the invention which can operate on either forms of binary numbers.

FIG. 9 shows a dedicated arithmetic macro-cell (VCU) 44 for calculating the scalar product (or internal product) of the two integer vectors, adapted to be integrated to a microcontroller using a technology of the VLSI type. The VCU 44 is a macrocell dedicated to the computation of the inner product of two vectors of integer numbers, and is based on the multiply and accumulate algorithm. The macrocell contains two units, interface unit 46 and arithmetic unit 48. Interface unit 46 is controlled by interface control unit 50, and arithmetic unit 48 is controlled by arithmetic control unit 52.

The interface unit 46 fetches the operands from the microcontroller's memories. It includes VCU peripheral register page 54--a page of registers with the addresses of the operands--and a register update unit 56 for updating the registers after each addressing. The arithmetic unit 48 realizes the inner product according to the relationship: S=A*B, i.e., S=ai*bi. Arithmetic unit 48 includes a FIFO memory 58 for storing the operands of each multiplication, an 8*8 multiplier 60 and a 32 bit adder 62 for the products accumulation.

The processing speed is usually a concern in integrated circuit microprocessor or microcontroller applications, and accordingly in one embodiment of the invention it is used in integrated circuits in which the mode of inputting the digital signals that represent the operands and outputting the signals that represent the result is of the parallel type rather than serial type.

In another embodiment it is used in a serial type application and can also be used in a mited mode application. Thus, the possibility of it being used in a serial or mixed mode should not be ruled out.

It will be appreciated that the embodiment described hereinabove in an illustrative and non-limitative sense may the subject of modifications, supplements and substitutions of elements without departing from the protection scope of the following claims.

INVENTORS:

Costa, Raffaele, Faldarini, Anna, Formenti, Laura

THIS PATENT IS REFERENCED BY THESE PATENTS:
Patent Priority Assignee Title
THIS PATENT REFERENCES THESE PATENTS:
Patent Priority Assignee Title
4153938, Aug 18 1977 Advanced Micro Devices, INC High speed combinatorial digital multiplier
5121352, Feb 06 1990 Micron Technology, Inc. Multiplier-accumulator circuit array operable in multiple modes
WO9119249,
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