A device for identifying a determined repetitive sequence of predetermined signals arriving on a modem. The device includes a delay circuit so that all the words of a sequence are simultaneously present; a combination circuit for providing a combined word; a circuit for calculating the modulus of each combined word and for comparing this modulus with a threshold; a circuit for counting clock pulses corresponding to the rate at which words arrive; a circuit for inhibiting the counting circuit when the modulus of the combined word is lower than the threshold; and a circuit for providing an identification signal when a predetermined number of clock signals is counted.
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10. A method for detecting a predetermined pattern of digital words within a continuous sequence of digital words, comprising the steps of:
A. combining consecutive pairs of digital words in the continuous sequence to form a series of combined words; B. setting a count indicator to zero when a magnitude of a combined word from the series of combined words is greater than a first threshold; C. incrementing the count indicator once for each combined word having a magnitude greater less than the first threshold; and D. indicating detection of the predetermined pattern of digital words when the count indicator is incremented beyond a predetermined count value.
17. An apparatus for detecting a predetermined pattern of digital words from a continuous sequence of digital words, comprising:
means for combining consecutive pairs of digital words in the continuous sequence of digital words to form a series of combined words; means for setting a count indicator to zero when a magnitude of a combined word from the series of combined words is greater than a first threshold; means for incrementing the count indicator once for each combined word having a magnitude greater less than the first threshold and means for indicating detection of the predetermined pattern when the count indicator is incremented beyond a predetermined count value.
24. An apparatus for detecting a predetermined pattern of digital signals from a continuous sequence of digital words arriving at the apparatus at a baud rate, comprising:
a counting circuit having a reset input and an output indicating a number of times counted, the counting circuit incrementing at the baud rate; a combinatorial logic circuit having an output, coupled to the reset input of the counting circuit, which resets the counting circuit when a mathematical combination of two successive words arriving at the apparatus exceeds a first threshold; and an indicator circuit, coupled to the output of the counting circuit, which asserts a detection signal when the output of the counting circuit exceeds a predetermined count value.
1. A process for identifying a predetermined repetitive pattern of signals in a sequence of words arriving on a modem, each signal being digitized as a word having a first portion corresponding to a real value and a second portion corresponding to an imaginary value, the process including the steps of:
A. delaying at least one word of the sequence so that a plurality of words is simultaneously present; B. linearly combining the plurality of words to provide a combined word; C. determining a first magnitude of the combined word; D. comparing the first magnitude with a threshold; E. when the first magnitude is lower than the threshold, counting clock pulses corresponding to a rate at which words arrive on the modem; and F. providing an identification signal when a predetermined number of continuous clock pulses is counted.
5. A device for identifying a predetermined repetitive pattern of signals in a sequence of words arriving on a modem, the signals being digitized as words, each word having a first portion corresponding to a real value and a second portion corresponding to an imaginary value, the words arriving on the modem in a sequence, the device comprising:
first means, electrically connectable to the modem, for delaying at least one word of the sequence so that a plurality of words is simultaneously present in the device; second means, connected to the first means, for linearly combining the words to provide a combined word; third means, connected to the second means, for determining a first magnitude of the combined word fourth means, connected to the third means, for comparing the first magnitude with a threshold; fifth means, connected to the fourth means, for, when the first magnitude of the combined word is lower than the threshold, counting clock pulses corresponding to a rate at which the words arrive on the modem; and sixth means, connected to the fifth means, for providing an identification signal when a predetermined number of continuous clock signals has been counted.
2. The process of
3. The process of
4. The process of
G. determining a second magnitude of each word arriving on the modem; and H. inhibiting the counting of clock pulses in step E when the magnitude for any word deviates from the predetermined magnitude by more than a predetermined threshold.
6. The device of
seventh means, for determining a magnitude of each word arriving on the modem; and eighth means, connected to the fifth means and the seventh means, for inhibiting counting of the clock pulses when the magnitude of a word arriving on the modem deviates from the predetermined magnitude by more than a predetermined threshold.
7. The device of
8. The device of
9. The device of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
E. calculating a magnitude of each word in the continuous sequence of digital words; and F. setting the count indicator to zero when the magnitude for any word exceeds a second threshold.
18. The apparatus of
19. The apparatus of
20. The apparatus of
21. The apparatus of
22. The apparatus of
means for calculating a magnitude of each word in the continuous sequence of digital words; and means for setting the count indicator to zero when the magnitude of any word exceeds a second threshold.
25. The apparatus of
26. The apparatus of
a delay circuit, coupled to a source of the continuous sequence of digital words, which delays the continuous sequence of digital words by one word; a mathematical calculator, coupled to the delay circuit and to the source of the continuous sequence of digital words, having an output which provides a linear combination of each pair of consecutive digital words; a complex conjugate magnitude calculator with an output and an input connected to the output of the mathematical calculator; and a comparator, having a first input connected to a signal representing a the first threshold, a second input connected to the output of the complex conjugate magnitude calculator, and an output, coupled to the reset input of the counting circuit, which is activated whenever the output of the complex conjugate magnitude calculator is greater than the first threshold input.
27. The apparatus of
an adder/subtractor that generates a mathematical combination of each pair of consecutive digital words, the mathematical combination being one of a sum of the pair of consecutive digital words and a difference between the pair of consecutive digital words.
28. The apparatus of
29. The apparatus of
a magnitude circuit having an input connected to a source of the continuous sequence of digital words, and an output, connected to the counting circuit reset input, that asserts a reset signal when the magnitude of a word from the continuous sequence of words exceeds a second threshold.
30. The apparatus of
a complex conjugate magnitude calculator with an output and an input connected to the source of the continuous stream sequence of digital words; and a comparator having a first input connected to a signal representing the second threshold, a second input connected to the output of the complex conjugate magnitude calculator, and an output that is activated whenever the output of the complex conjugate magnitude calculator exceeds the second threshold.
31. The apparatus of
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The circuit according to the invention represented in
In practice, since the lines are always noisy, the output of adder 14 is not strictly zero when the incoming signals are the expected signals. Accordingly, adder 14 is followed by an energy calculation circuit including a multiplier 17 receiving, on the one hand, directly the output of adder 14 and, on the other hand, this output through a circuit 18 providing the complex conjugate. The output signal 20 of multiplier 17 is provided to a first input of a comparator 21 that compares this Signal with a threshold TH1. Comparator 21 has an output at a high level when the signal at input 20 is higher than the threshold, and has an output at a low level when the signal is lower than the threshold. The output of comparator 21 is provided through an OR gate 22 to the reset input RS of a counter 23 that receives at its input 24 signals arriving at the same rate as data are introduced at input 11, that is, the signal at input 24 is normally the baud clock. Thus, as long as the output of comparator 21 is at a low level, counter 23 counts and as soon as output 21 reaches a high level, the counter is reset and the next counting begins at zero. The output of counter 23 is applied to an input 25 of a comparator 26 that compares this output with a predetermined value N, for example equal to 32. Thus, when a counting equal to 32 has occurred, a signal appears at the output terminal 28 of comparator 26. This signal at terminal 28 is an identification signal since it indicates that the output of comparator 21 has been 32 successive times at a low level, that is, its input was 32 successive times lower than threshold TH1. This means that signals corresponding to a sequence ACAC . . . were received 32 successive times (when multiplier 15 is a multiplier by +1) or a sequence AAA . . . (when multiplier 15 is a multiplier by -1).
Indeed, it is necessary to wait for a determined number of passages of signal 20 at a low level to, detect with certainty a sequence because the combinatory circuit 12 provides a low output each time successive signals exhibiting a predetermined (for example identical or reverse) relation are provided thereto; this can occur during a signal transmission for specific signals, as is apparent by studying the constellations of
However, there is a case when an erroneous detection of a sequence such as ACAC . . . may happen, that is, when no signal arrives at terminal 11, or more precisely when only noise arrives due to a temporary misfunction of the telephone link. The lower branch of the circuit of
This lower branch includes a circuit for determining the energy of the incoming signal. The circuit includes a multiplier 31, whose first input directly receives the signal of terminal 11, and whose second input receives its complex conjugate through a circuit 32. The average energy A2 of signal A or C is subtracted from this energy (it should be noted that these signals have the safe modulus). This operation is carried out in an adder 33 whose output is provided to an absolute value calculator. 34. The output of circuit 34 is provided to the first, input of a comparator 35, whose second input receives a threshold signal TH2. The output of comparator 35 is provided to a second input of the OR gate 22. Thus, if the signal at terminal 11 is a signal having the same modulus as a signal A or C, the output of circuit 34 will be substantially zero and the output of comparator 35 will be zero. Accordingly, this signal will not affect the output of the OR gate 22. In contrast, if the signal at terminal 11 has a modulus different from the modulus of A, for example because it corresponds to a symbol having a different value or because it corresponds only to noise the output of comparator 35 will be at a high level and counter 23 will be reset.
Various other safety circuits can be devised by those skilled in the art.
Of course, although for the sake of simplification, the above description has been made using terms sometimes corresponding to analog systems, it will clearly appear to those skilled in the art that all the elements of the circuit according to the invention process digital signals and that the components of the circuit illustrated as hardware are often in practice embodied as software operating on a processor.
Having thus described one particular embodiment of the invention, various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The invention is limited only as defined in the following claims and the equivalents thereto.
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