A dc matrix converter having six forward current conducting power switches and six reverse current conducting power switches has the on time duration of each power switch within a pulse width modulation period controlled by relationships between d and q components of a modulation index determined by the ratio of a voltage command to the instantaneous voltage of the ac mains expressed in stationary dq coordinates, the selection of which is made based on inequalities between the dc main voltage components expressed in stationary dq coordinates. switch selection is also performed in response in relationships of the ac main voltage components expressed in stationary dq coordinates. Zero vectors are selected to minimize the common mode voltage.
|
1. A method of controlling the flow of current through a dc matrix converter between a dc load and a set of three-phase ac mains, said dc matrix converter comprising a plurality of top switches, each connected between a corresponding one of said ac mains and a first dc output of said dc matrix converter, and a plurality of bottom switches, each connected between a corresponding one of said ac mains and a second dc output of said dc matrix converter, comprising:
operating said switches in a manner so that each switch, when operated to connect a corresponding one of said ac mains to a related specific one of said dc outputs, remains operated until another switch has operated to connect one of said ac mains to said specific dc output, and so that one of said top switches is operated contemporaneously with one of said bottom switches, said switches being operated in pairs, each pair including a top switch related to one ac main and a bottom switch related to an ac main other than said one ac main, and said switches also being operated in sets, each set including a top switch and a bottom switch both related to the same ac main; providing a voltage command signal, V*, indicative of the voltage to be provided by said dc output terminals to said load; providing a modulation command, m*, as the ratio of said voltage command signal, V*, to the instantaneous magnitude of voltage, V, of said ac mains in stationary d, q coordinates; and providing an in-phase modulation command component, mq=m* cos θ and a quadrature modulation command component md=m* sin θ; providing a quantity m1=3md/2-mq/2; providing a quantity m2=3md/2+mq/2; providing an in-phase component, Vq, and a quadrature component, Vd, of the instantaneous ac mains voltage in orthogonal coordinates aligned with the phase of a given one of said ac mains; and providing, when |Vd3|<|Vq|, a first fraction dα=-m1 if Vq>0 and dα=m1 if Vq<0, and a second fraction dβ=m2 if Vq>0 and dβ=-m2 if Vq<0; providing when VdVq3>Vq2, said first fraction dα=-m2 mq if Vq>0 and dα=m2 -mq if Vq<0, and said second fraction dβ=mq m1 if Vq>0 and dβ=-mq -m1 if Vq<0; and providing, when neither |Vd3|<|Vq| nor Vd3>Vq, said first fraction dα=mq -m2 if Vq>0 and dα=-mq m2 if Vq<0, and said second fraction dβ=-m1 mqif Vq>0 and dβ=-m1 -mq if Vq<0; and in each of a continuous sequence of modulation periods which are small compared with the period of voltage of said ac mains, operating a first pair of said switches for said first fraction, dα, of said period, operating a second pair of said switches for said second fraction, dβ, of said period, and operating a set of switches for the remainder of said period.
4. A method of controlling the flow of current through a dc matrix converter between a dc load and a set of three-phase ac mains, said dc matrix converter comprising a plurality of top switches, each connected between a corresponding one of said ac mains and a first dc output of said dc matrix converter, and a plurality of bottom switches, each connected between a corresponding one of said ac mains and a second dc output of said dc matrix converter, comprising:
operating said switches in a manner so that each switch, when operated to connect a corresponding one of said ac mains to a related specific one of said dc outputs, remains operated until another switch has operated to connect one of said ac mains to said specific dc output, and so that one of said top switches is operated contemporaneously with one of said bottom switches, said switches being operated in pairs, each pair including a top switch related to one ac main and a bottom switch related to an ac main other than said one ac main, and said switches also being operated in sets, each set including a top switch and a bottom switch both related to the same ac main; in each of a continuous sequence of modulation periods which are small compared with the period of voltage of said ac mains, operating a first pair of said switches for a first fraction, dα, of said period, operating a second pair of said switches for a second fraction, dβ, of said period, and operating a set of switches for the remainder of said period; characterized by the improvement comprising: providing an in-phase component, Vq, and a quadrature component, Vd, of the instantaneous ac mains voltage in orthogonal coordinates aligned with the phase of a given one of said ac mains; if Vd3< ≧|Vq|, said first pair of switches include a top switch connected to a third ac main, next advanced in phase from said given one of said ac mains, but if not, then if Vq>0, said first pair of switches include a top switch connected to said given one of said ac mains, but if neither, then said first pair of switches include a top switch connected to a second ac main, next delayed in phase from said given one of said ac mains; if -Vd3>|Vq|, said first pair of switches include a bottom switch connected to said third ac main, but if not, then if - Vq<0, said first pair of switches include a bottom switch connected to said given one of said ac mains, but if neither, then said first pair of switches include a bottom switch connected to said second ac main; if -Vd3>|Vq|, said second pair of switches include a top switch connected to said second main, but if not, then if Vq>0, said second pair of switches include a top switch connected to said given one of said ac mains, but if neither, then said second pair of switches include a top switch connected to said third ac main; and if Vd3< ≧|Vq|, said second pair of switches include a bottom switch connected to said second main, but if not, then if Vq<0, said second pair of switches include a bottom switch connected to said given one of said ac mains, but if neither, then said second pair of switches include a bottom switch connected to said third ac main.
7. A method of controlling the flow of current through a dc matrix converter between a dc load and a set of three-phase ac mains, said dc matrix converter comprising a plurality of top switches, each connected between a corresponding one of said ac mains and a first dc output of said dc matrix converter, and a plurality of bottom switches, each connected between a corresponding one of said ac mains and a second dc output of said dc matrix converter, comprising:
operating said switches in a manner so that each switch, when operated to connect a corresponding one of said ac mains to a related specific one of said dc outputs, remains operated until another switch has operated to connect one of said ac mains to said specific dc output, and so that one of said top switches is operated contemporaneously with one of said bottom switches, said switches being operated in pairs, each pair including a top switch related to one ac mains and a bottom switch related to an ac main other than said one ac main, and said switches also being operated in sets, each set including a top switch and a bottom switch both related to the same ac main; providing a voltage command signal, V*, indicative of the voltage to be provided by said dc output terminals to said load; providing a modulation command, m*, as the ratio of said voltage command signal, V*, to the instantaneous magnitude of voltage, V, of said ac mains in stationary d, q coordinates; and providing an in-phase modulation command component, mq=m* cos θ and a quadrature modulation command component md=m* sin θ; providing a quantity m1=3md/2-mq/2; providing a quantity m2=3md/2+mq/2; providing an in-phase component, Vq, and a quadrature component, Vd, of the instantaneous ac mains voltage in orthogonal coordinates aligned with the phase of a given one of said ac mains; and providing, when |Vd3|>|Vq|, said first fraction dα=-m1 if Vq>0 and dα=m1 if Vq<0, and said second fraction dβ=m2 if Vq>0 and dβ=-m2 if Vq<0; providing when Vd3=Vq, said first fraction dα=-m2 mq if Vq>0 and dα=m2 -mq if Vq<0, and said second fraction dβ=mq m1 if Vq>0 and dβ=-mq -m1 if Vq<0; and providing, when neither |Vd3|<|Vq| nor Vd3>Vq, said first fraction dα=mq -m2 if Vq>0 and dα=-mq m2 if Vq<0, and said second fraction dβ=m1 mq if Vq> and dβ-m1 -mq if Vq<0; in each of a continuous sequence of modulation periods which are small compared with the period of voltage of said ac mains, operating a first pair of said switches for a first fraction, dα, of said period, operating a second pair of said switches for a second fraction, dβ, of said period, and operating a set of switches for the remainder of said period; and further comprising: if Vd3< ≧|Vq|, said first pair of switches include a top switch connected to a third ac main, next advanced in phase from said given one of said ac mains, but if not, then if Vq>0, said first pair of switches include a top switch connected to said given one of said ac mains, but if neither, then said first pair of switches include a top switch connected to a second ac main, next delayed in phase from said given one of said ac mains; if -Vd3>|Vq|, said first pair of switches include a bottom switch connected to said third ac main, but if not, then if -Vq<0, said first pair of switches include a bottom switch connected to said given one of said ac mains, but if neither, then said first pair of switches include a bottom switch connected to said second ac main; if -Vd3>|Vq|, said second pair of switches include a top switch connected to said second main, but if not, then if Vq>0, said second pair of switches include a top switch connected to said given one of said ac mains, but if neither, then said second pair of switches include a top switch connected to said third ac main; and if Vd3< ≧|Vq|, said second pair of switches include a bottom switch connected to said second main, but if not, then if Vq<0, said second pair of switches include a bottom switch connected to said given one of said ac mains, but if neither, then said second pair of switches include a bottom switch connected to said third ac main.
2. A method according to
3. A method according to
5. A method according to
6. A method according to
8. A method according to
9. A method according to
|
This invention relates to controlling a direct, AC to DC matrix converter to supply controlled DC voltage to a load utilizing precisely controlled, pulse width modulation.
In commonly owned, copending U.S. patent application Ser. No. 09/310,600 filed contemporaneously herewith, a direct, 3-phase AC to DC matrix converter employs switches which are controlled in sequence to directly synthesize a desired average DC voltage waveform at the input terminals of the DC motor, while simultaneously distributing the DC output current among the AC input lines as a sinusoidal waveform in phase with the AC voltage. The difference between the direct DC matrix converter of said copending application and prior DC-PWM converters is that the prior converters create a DC power of a fixed voltage, much the same as a battery, and then utilized some portion of the voltage, as needed, synthesizing a correct DC voltage, on average, by means of pulse width modulation, whereas in said application, the desired voltage at the desired current is synthesized by pulse width modulation directly from the AC mains, while retaining the sinusoidal balance and unity power factor of the AC input currents.
In the system of said application, each switch is turned on and off in each modulation period. As is known, the switching losses in power switches occur only during transition between the non-conducting and conducting states; therefore, reducing the number of commutations will significantly reduce power losses in the switches.
Objects of the invention include providing pulse width modulation synthesis of DC voltage directly from three-phase AC mains with minimal commutation losses, with a minimum of calculations (processor steps), with modulation frequencies as high as 10 KHz or more to provide minimal ripple in the DC voltage and current, with minimal distortion and a unity power factor at the AC mains.
This invention is predicated on my discovery that all switches in a DC matrix converter can be turned on and remain on for two out of three portions of the same or adjacent pulse width modulation periods, when operated in a proper sequence, including two voltage producing portions and one non-voltage producing portion of each pulse width modulation period.
According to this invention, the switch-on time of DC matrix power switches is determined by the ratio of an instantaneous voltage command signal, V*, (indicative of the voltage to be provided by said DC matrix converter) to the instantaneous magnitude, V, of the three-phase AC mains in stationary dq coordinates, along with the phase relationship between the present instantaneous phase of said AC mains voltage in stationary dq coordinates and the leading and lagging boundaries of six phase sectors that span a cycle of said AC mains.
According to the invention further, the phase relationship are expressed in terms of dq quantities, using trigonometric angle-sum relationships and identified by inequalities existing between the voltages of the AC mains expressed in orthogonal dq coordinates and zero.
In still further accord with the invention, the pairs of switches to be used in each portion of a pulse width modulation period are selected by relationships between the components of the AC mains voltage in orthogonal DQ coordinates. The invention may be implemented in DC matrix converters which supply unilateral current, bilateral current, and with or without regeneration.
Other objects, features and advantages of the present invention will become more apparent in the light of the following detailed description of exemplary embodiments thereof, as illustrated in the accompanying drawing.
Referring to
In the example herein, the commands which will ultimately cause the DC matrix converter to drive the motor 19 in a desired fashion are provided by a conventional elevator motion controller (not shown) which provides a speed command on a line 30 to a summer 31 which subtracts the actual speed on the line 32 provided by a conventional position and speed conversion circuit 33 in response to a signal on a line 34 from a suitable, conventional encoder (not shown) which is coupled to the sheave 20 (or the motor 19, as the case may be). A position output of the circuit 33 on a line 37 is fed back to the motion controller so as to determine the continuity of commands necessary to cause the elevator to move in the desired fashion, all as is well known in the art and forms no part of the present invention. The output of the summer 31 is provided on a signal line 40 to a conventional speed error proportional and integral gain circuit 41, the output of which on a line 42 comprises a current command, I*, which is fed to a summer 43. The summer 43 subtracts the actual motor current on a line 44, derived from a conventional current sensor 45 to provide a current error signal on a line 46. The current error signal is processed with conventional proportional and integral gain in a circuit 51, the output of which on a line 52 comprises a voltage command, V*.
In accordance with the invention, the ratio of the magnitude of the voltage command to the magnitude of the input AC mains voltage vector, in stationary dq coordinates, determines a modulation index, m*, which is used to determine the duration of switch-on time during pulse width modulation of the voltage on the AC input mains in order to achieve the desired DC voltage for application to the load, such as the motor 19.
The voltage on the AC mains a, b, c is fed to a conventional stationary three-phase to stationary dq coordinate conversion circuit 56 to provide outputs Vd, Vq which define the three-phase input voltages of the AC mains in orthogonal coordinates, as is known. The magnitude of the AC mains, V, on a line 57, is simply the square root of the sum of the squares of Vd, Vq, performed in a conventional unit 58. The orthogonal magnitudes Vd, Vq are also fed to a conventional phase locked loop 63, the output of which on lines 65 and 66 are signals indicative of sine Θ and cosine Θ, respectively. These are applied to a circuit 68 which converts the modulation index m* in synchronous dq coordinates to desired modulation index components mq, md in stationary dq coordinates. The mq and md signals on lines 71, 72 are fed to a duration and selection function 73 which determines the duration for which a selected pair or set of switches should be turned on, and selects which pair or set of switches are to be on, at any given moment, to perform the necessary pulse width modulation in order to synthesize the desired DC voltage at the output terminals, j, k, of the DC matrix converter 18. The functions 73 are described more fully hereinafter. Signals indicative of the duration of switch on times, and the selected pair of switches to be turned on, are provided over a trunk of lines 77 to timing circuits 78 which actually count pulses in real time so as to implement the desired durations by providing switch on gating circuits over a trunk of 12 lines 79 to the DC matrix converter 18. The timing circuits turn the switches on and off according to conventional commutation methods, so that each of the output terminals is always connected to an AC main, with no open circuit gaps, to satisfy the known continuity of current constraint. One commutation example is set forth in Holmes and Lipo, "Implementation of a Controlled Rectifier Using AC--AC Matrix Converter Theory", IEEE Trans, Power Elec., January, 1992.
Although not shown in
One embodiment of a DC matrix converter 18 is illustrated in FIG. 2. For each phase of the AC mains, a, b, c there are two power transistor switches at the top of FIG. 2 and two switches at the bottom of FIG. 2. One switch at the top of
The general nature of operation of the DC matrix converter is illustrated in FIG. 3. Therein, the sinusoidal voltage of the AC mains Va, Vb, Vc is plotted against time. Also plotted in
The commanded modulation index, m* for the DC matrix converter is transformed to the stationary reference frame, in dq coordinates, as follows:
where Θ=0 corresponds to the q-axis of the AC mains voltage in the synchronous reference frame (63-68, FIG. 1).
The currents i1-i6 are the only possibilities that produce non-zero voltage at the output terminals (Vj not equal to Vk), which can be achieved by selective operation of two of the switches in
Referring to
where φ=0 and φ=π/3 correspond to the angular location of the α-vector and β-vector, respectively.
In further accord with the invention, to determine the switch times, the above modulation functions are expressed in terms of dq quantities by using trigonometric angle-sum relations in each sector as follows. Using the above equations and the fact that φ=π/6+Θ-sπ/3, where s is the sector in
For reference, the values of the sine and cosine coefficients in the above equations are given in the following table, for each sector s=0 through s=5.
sin(π/6 + | -cos (π/6 + | sin(π/6 - | -cos(π/6 - | |
s | s π/3) | s π/3) | s π/3) | s π/3) |
0 | ½ | -3/2 | ½ | 3/2 |
1 | 1 | 0 | -½ | 3/2 |
2 | ½ | 3/2 | -1 | 0 |
3 | -½ | 3/2 | -½ | -3/2 |
4 | -1 | 0 | ½ | -3/2 |
5 | -½ | -3/2 | 1 | 0 |
If the following quantities are defined:
then the modulation functions (α and β duty ratios) are determined in each sector by the quantities given in the following table:
s | dα | dβ |
0 | -m1 | m2 |
1 | mq | m1 |
2 | m2 | -mq |
3 | m1 | -m2 |
4 | -mq | -m1 |
5 | -m2 | mq |
This is illustrated in the space-vector diagrams of
During a modulation period which is at the beginning of a sector, the switching time for the α vector will be significant, and the switching time for the β vector will be slight. Midway through the sector, the switching time for the α vector will be equal to the switching time of the β vector. Near the end of a sector, the on-time for the β vector will be significant and the on-time for the α vector will be slight. In the remainder of each modulation period, d0=1-dα-dβ (the duration for the zero vector), a pair of switches related to the same AC main, such as Bt, Bb, will be turned on so as to provide a zero vector, thereby adjusting the magnitude of the output voltage while utilizing a minimum number of switch commutations. The times when the various top switches will be turned on so as to conduct an α vector are shown in
m* > 0 | m* < 0 | ||
Top | Vd' = Vd | Vd' = -Vd | |
Switches | Vq' = Vq | Vq' = -Vq | |
Bottom | Vd' = -Vd | Vd' = Vd | |
Switches | Vq' = -Vq | Vq' = Vq | |
Therefore, test 107 and steps 108-111 define Vd' and Vq' appropriately for the sign of m* before the inequalities are tested. From
This is easily tested for on a digital signal processor as shown in test 115 of FIG. 8. Similarly, |dβ|=m1 in sectors 1 and 4, which are defined by the following inequality:
This is determined in test 116 of FIG. 8.
The remaining sectors, 2 and 5, in which |dβ|=mq, are determined through the process of elimination (tests 115 and 116 negative, FIG. 8). The sign of dβ is determined by testing the sign of Vq in tests 117-119 of
The duty ratio din dα is easily obtained by noting in
This is achieved by steps 123 and 124 (
Once the on-times are determined for the α and β vectors, it is necessary to determine which switches are to be turned-on to produce the vectors according to FIG. 4. This is a two-step process: a determination of switches for the non-zero vectors, followed by switch assignments for the zero vector.
The phases (i.e., switches) to which the above duty ratios or durations apply are determined by the region in which the voltage vector lies. For example, the switch assignments for the top power switches in the DC matrix converter for the α vector and β vector are shown in
The remaining assignments of top switches for the β-vector are determined, after eliminating sectors 1 and 2, by testing the sign of Vq as shown in
The top switch assignments for the α-vector are easily obtained by noting in
These assignments are shown in tests and steps 138 of FIG. 13.
Determination of bottom switch assignments for the α-vector and β-vector is identical to the above except for a phase shift of π radians between the assignments for the two groups. Hence, the determination is identical to the above when using the following substitutions (steps 140, 141, FIG. 13):
These selections are made in steps and tests 143 of FIG. 13.
As described hereinbefore, a zero vector, i0, is defined as the short circuiting of the output terminals j, k by a set of like-phase switches, At, Ab; Bt, Bb; Ct, Cb. The selection of which set of switches to use in representing the zero vector affects the common-mode output voltage. The application of each vector, i1-i6, results in each of the output terminals, j, k, to be connected to one of the AC main voltages Va, Vb, or Vc. The differential voltage applied across the load, VD, is the difference in the output phase voltages, Vj-Vk, while the common-mode voltage referenced to the system neutral, VCM, is the sum of the two output line voltages divided by the number of output phases, (Vj+Vk)/2. The resulting differential and common-mode voltages produced by each vector is given in the following tables:
Vector | i1 | i2 | i3 | i4 | i5 | i6 | i0 | i0 | i0 |
Switches | At, Cb | Bt, Cb | Bt, Ab | Ct, Ab | Ct, Bb | At, Bb | At, Bb | Bt, Bb | Ct, Cb |
Vj | VC | VC | VA | VA | VB | VB | VA | VB | VC |
Vk | VA | VB | VB | VC | VC | VA | VA | VB | VC |
VD | VAC | VBC | VBA | VCA | VCB | VAB | 0 | 0 | 0 |
VCM | VA + VC | VB + VC | VB + VA | VC + VA | VC + VB | VA + VB | VA | VB | VC |
Since the line voltages Va, Vb, and Vc are sinusoidal, the peak common-mode voltage attained by the non-zero vectors, i1 through i6, over an AC cycle is easily calculated as
where VLL is the rms line-to-line voltage and wt is the AC phase angle in radians. In contrast, the peak common-mode voltage attained by the zero vectors during the same period is
As a consequence, an indiscriminant use of the zero vectors results in a peak common-mode voltage which is twice that for the non-zero vectors.
The zero vectors can, however, be chosen in such a way as to reduce the peak common-mode voltage. For example, if the use of the zero vector (At, Ab) is restricted to the periods
where ωt=0 corresponds to the peak of the line voltage Va, the maximum common mode voltage is given by:
which equals
Consequently, the peak common-mode voltage produced by this zero vector has been reduced by half, by restricting its usage during the AC cycle. To realize this reduction factor over the entire AC cycle, similar restrictions are placed on the other zero vectors. This is summarized in the following table and illustrated in FIG. 14.
Zero Vector | Allowable Periods of Application | |
(At, Ab) | π/3 < ωt < 2π/3 and 4π/3 < ωt < 5π/3 | |
(Bt, Bb) | 0 < ωt < π/3 and π < ωt < 4π/3 | |
(Ct, Cb) | 2π/3 < ωt < π and 5π/3 < ωt < 0 | |
Determination of the switch sets for the zero vector, denoted SW0, applies to both the top and bottom groups of switches in the DC matrix converter. Determination of which sector the voltage vector lies in is accomplished with inequality testing. The inequalities that define the sector boundaries are shown in FIG. 14. The sectors, in which SW0=A, are defined by the following inequality (positive result of test 139 of FIG. 15):
Similarly, SW0=B is identified by testing the following inequality (positive result of test 140 of FIG. 15);
SW0=C is determined by elimination (negative result of test 140 of FIG. 15).
If desired, programming may be simplified by noting the similarity to the algorithm for setting the duty ratios, provided the following substitution is made:
The zero vector switch selection described hereinbefore with respect to
Within each modulation period, the order in which the various pairs and sets of switches are operated for the α vector, the β vector, and the zero vector, is immaterial. Thus the order may be α, β, zero; β, α, zero; β, zero, α; or any other order. With the constraint that a switch conducting between one of the AC mains and one of the output terminals is never shut off until another switch is turned on to conduct from an AC main to that terminal, the relationship of switch pairs (αand β) and sets (zero vectors) illustrated in
Thus, the advantages of reduced commutations offered by the space-vector approach of the invention represented in the space-vector diagram shown in
Sec- | Vector | Vector | Voltage | Zero | |
tor | Iα | Iβ | Angle | Relationship | Vector |
0 | i6 | i1 | 330-360 | VA > VC > VB | (C1, C2) |
(A1, B2) | (A1, C2) | 0-30 | VA > VB > VC | (B1, B2) | |
1 | i1 | i2 | 30-60 | ||
(A1, C2) | (B1, C2) | 60-90 | VB > VA > VC | (A1, A2) | |
2 | i2 | i3 | 90-120 | ||
(B1, C2) | (B1, A2) | 120-150 | VB > VC > VA | (C1, C2) | |
3 | i3 | i4 | 150-180 | ||
(B1, A2) | (C1, A2) | 180-210 | VC > VB > VA | (B1, B2) | |
4 | i4 | i5 | 210-240 | ||
(C1, A2) | (C1, B2) | 240-270 | VC > VA > VB | (A1, A2) | |
5 | i5 | i6 | 270-300 | ||
(C1, B2) | (A1, B2) | 300-330 | VA > VC > VB | (C1, C2) | |
Referring to
The order in which the calculations are performed (
The invention has been described in an embodiment in which there are 12 switches at+ at-, . . . cb+, cb-, in order to accommodate loads in both directions and regeneration. However, the invention may as well be utilized in DC matrix converters driving loads in a single direction without regeneration, such as for driving power tools, or in other applications.
The present invention has been shown as it may be implemented utilizing n-type, punch-through, insulated gate bipolar transistor power switches. However, the invention may be implemented using p-type transistors, or with non-punch-through, insulated gate bipolar transistors connected in anti-parallel pairs.
The foregoing patent application and article are incorporated herein by reference.
Patent | Priority | Assignee | Title |
10158299, | Apr 18 2018 | Rockwell Automation Technologies, Inc. | Common voltage reduction for active front end drives |
10305368, | Aug 13 2012 | Rockwell Automation Technologies, Inc. | Method and apparatus for bypassing Cascaded H-Bridge (CHB) power cells and power sub cell for multilevel inverter |
11211879, | Sep 23 2019 | Rockwell Automation Technologies, Inc.; ROCKWELL AUTOMATION TECHNOLOGIES, INC | Capacitor size reduction and lifetime extension for cascaded H-bridge drives |
11342878, | Apr 09 2021 | Rockwell Automation Technologies, Inc.; ROCKWELL AUTOMATION TECHNOLOGIES, INC | Regenerative medium voltage drive (Cascaded H Bridge) with reduced number of sensors |
6914409, | Mar 26 2001 | TOSHIBA CARRIER CORPORATION | Current detection method and control apparatus for electric motor |
7881087, | Apr 28 2006 | Daikin Industries, Ltd | Matrix converter and control method for the matrix converter |
8259474, | May 16 2007 | Otis Elevator Company | Pulse width modulation control of a matrix converter |
8362732, | Feb 02 2010 | GM Global Technology Operations LLC | Motor phase winding fault detection method and apparatus |
8450957, | Jun 13 2008 | ZHUZHOU CSR TIMES ELECTRIC CO , LTD | Space vector based synchronous modulating method and system |
9325252, | Jan 13 2014 | Rockwell Automation Technologies, Inc. | Multilevel converter systems and sinusoidal pulse width modulation methods |
9362839, | Feb 09 2011 | Rockwell Automation Technologies, Inc. | Power converter with common mode voltage reduction |
9425705, | Aug 13 2012 | Rockwell Automation Technologies, Inc. | Method and apparatus for bypassing cascaded H-bridge (CHB) power cells and power sub cell for multilevel inverter |
9520800, | Jan 09 2014 | ROCKWELL AUTOMATION TECHNOLOGIES, INC | Multilevel converter systems and methods with reduced common mode voltage |
9559541, | Jan 15 2015 | Rockwell Automation Technologies, Inc.; ROCKWELL AUTOMATION TECHNOLOGIES, INC | Modular multilevel converter and charging circuit therefor |
9748862, | May 13 2015 | Rockwell Automation Technologies, Inc.; ROCKWELL AUTOMATION TECHNOLOGIES, INC | Sparse matrix multilevel actively clamped power converter |
9787213, | Mar 18 2013 | Rockwell Automation Technologies, Inc. | Power cell bypass method and apparatus for multilevel inverter |
9812990, | Sep 26 2016 | Rockwell Automation Technologies, Inc. | Spare on demand power cells for modular multilevel power converter |
9912221, | Aug 13 2012 | Rockwell Automation Technologies, Inc. | Method and apparatus for bypassing cascaded h-bridge (CHB) power cells and power sub cell for multilevel inverter |
Patent | Priority | Assignee | Title |
3961154, | Apr 18 1972 | Elektriska Svetsningsaktiebolaget | Direct current power supply for manual arc welding |
4599685, | Jan 25 1984 | Hitachi, Ltd. | Control circuit for power converter apparatus |
4984147, | May 12 1989 | Mitsubishi Denki Kabushiki Kaisah | Control method for PWM converter |
5541827, | May 17 1995 | DOBLE ENGINEERING COMPANY | Reducing switching losses in a phase-modulated switch-mode amplifier |
5706186, | Sep 23 1996 | Allen-Bradley Company, Inc.; ALLEN-BRADLEY COMPANY, INC | Hybrid pulse width modulation method and apparatus |
5852551, | Oct 02 1996 | LG-Otis Elevator Company | Pulsed width modulation method for power transforming apparatus |
EP531151, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 02 2002 | Otis Elevator Company | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
Nov 12 2007 | REM: Maintenance Fee Reminder Mailed. |
Apr 28 2008 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Apr 28 2008 | M1555: 7.5 yr surcharge - late pmt w/in 6 mo, Large Entity. |
Sep 19 2011 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Feb 24 2007 | 4 years fee payment window open |
Aug 24 2007 | 6 months grace period start (w surcharge) |
Feb 24 2008 | patent expiry (for year 4) |
Feb 24 2010 | 2 years to revive unintentionally abandoned end. (for year 4) |
Feb 24 2011 | 8 years fee payment window open |
Aug 24 2011 | 6 months grace period start (w surcharge) |
Feb 24 2012 | patent expiry (for year 8) |
Feb 24 2014 | 2 years to revive unintentionally abandoned end. (for year 8) |
Feb 24 2015 | 12 years fee payment window open |
Aug 24 2015 | 6 months grace period start (w surcharge) |
Feb 24 2016 | patent expiry (for year 12) |
Feb 24 2018 | 2 years to revive unintentionally abandoned end. (for year 12) |