A ring oscillator includes an even-numbered plurality of ring coupled delay stages. Each delay stage includes a differential amplifier, a voltage clamping circuit, and a current source. The differential amplifier receives first and second input signals from a preceding delay stage. The differential amplifier provides a first output signal and a complementary second output signal at first and second nodes, respectively. The voltage clamping circuit is coupled between the first and second nodes to limit a peak-to-peak voltage swing of each of the first and second output signals. The current source is coupled to the differential amplifier and varies a bias current in accordance with a delay bias voltage.

PTO Wrapper PDF
Dossier Espace Google
Patent
   RE38482
Priority
May 28 1992
Filed
Aug 02 2000
Issued
Mar 30 2004
Expiry
May 28 2012

TERM.DISCL.
Inventors
Leung, Win…
Assg.orig
Rambus Inc.
Assg.curr
Rambus Inc.
Entity
Large
Referenced by
34
References
52
Maint.:
all paid
CROSS-REFERENCE TO R…
FIELD OF INVENTION
BACKGROUND OF THE IN…
SUMMARY AND OBJECTS …
BRIEF DESCRIPTION OF…
DETAILED DESCRIPTION
21. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
a differential amplifier providing a differential output signal;
a self-biased voltage clamping circuit coupled to limit a peak-to-peak voltage swing of the differential output signal; and
a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.
23. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
a differential amplifier providing a differential output signal comprising a first output signal at a first node and a second output signal at a second node;
a voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal without independently clamping each of the first and second nodes; and
a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.
0. 71. A clock synchronization circuit comprising:
a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a respective delay time with respect to a reference clock signal; and
interpolator circuitry coupled to the plurality of delay stages, the interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether the phase of the first clock signal leads or lags a target phase, wherein the target phase is based on transitions in an input signal.
0. 25. A synchronous memory device comprising:
an array of memory cells to store data;
a clock synchronization loop to generate a plurality of clock signals, each clock signal having a timing relationship with respect to a reference clock signal;
first interpolator circuitry to generate a first internal clock signal from a first and a second clock signal of the plurality of clock signals, wherein a phase of the first internal clock signal is interpolated from respective phases of the first and second clock signals according to phase information indicative of whether the first internal clock signal leads or lags a first external clock signal; and
interface circuitry to synchronize a transmission of data with the first internal clock signal.
0. 91. A method for clock synchronization, comprising:
generating a plurality of clock signals from a reference clock signal, wherein each clock signal of the plurality of clock signals is delayed from the reference clock signal by a corresponding delay time such that a plurality of different delays with respect to the reference clock signal are represented in the plurality of clock signals;
detecting phase of an input signal, wherein the phase of the input signal represents a target phase; and
generating a first clock signal based on a pair of clock signals of the plurality of clock signals, wherein generating the first clock signal includes interpolation between the pair of clock signals using information indicative of whether the phase of the first clock signal leads or lags the target phase.
0. 52. A clock synchronization circuit comprising:
a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage having a delay time with respect to a reference clock signal;
interpolator circuitry to generate a first clock signal using a pair of clock signals of the plurality of clock signals, wherein a phase of the first clock signal is interpolated between respective phases of each clock signal of the pair of clock signals in accordance with information indicative of whether a phase of the first clock signal leads or lags a phase of an input clock signal; and
a detector circuit to compare the phase of the first clock signal with the phase of the input clock signal, to generate the information indicative of whether the phase of the first clock signal leads or lags the phase of the input clock signal.
0. 40. An integrated circuit device comprising:
interface circuitry to receive first and second external clock signals; and
clock synchronization circuitry to synchronize a transmission of data with the first external clock signal and to synchronize a reception of data with the second external clock signal, the clock synchronization circuitry including:
a reference loop to receive a reference clock signal and generate a plurality of clock signals, each clock signal of the plurality of clock signals having a predetermined timing relationship with the reference clock signal;
a first subloop circuit, coupled to the reference loop, to synchronize the transmission of data with the first external clock signal using the plurality of clock signals; and
a second subloop circuit, coupled to the reference loop, to synchronize the reception of data with the second external clock signal using the plurality of clock signals.
0. 66. A synchronous memory device comprising:
an array of memory cells to store data;
a plurality of delay elements coupled in series, each delay element generating a respective output signal having a different phase;
a detector circuit to compare a phase of an external clock signal with a phase of an internal transmit clock signal, the detector circuit to generate information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal;
a multiplexer circuit, coupled to the plurality of delay elements, to select a first output signal generated by the plurality of delay elements in response to the information; and
an interface circuit to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using at least the first output signal selected by the multiplexer circuit.
0. 60. A synchronous memory device comprising:
an array of memory cells to store data;
clock synchronization circuitry including:
a plurality of delay stages coupled in series;
a first multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a first internal clock signal, the selection being controlled by a first plurality of control signals;
a first shift register circuit to generate the first plurality of control signals in accordance with information indicative of whether a phase of an external clock signal leads or lags a phase of an internal transmit clock signal; and
a detector circuit to compare the phase of the external clock signal with the phase of the internal transmit clock signal and generate the information; and
interface circuitry to output data from the memory device, the data being output in synchronism with the internal transmit clock signal, the internal transmit clock signal being generated using the first internal clock signal.
0. 100. An integrated circuit comprising:
a plurality of delay stages coupled in series to output a plurality of clock signals, each delay stage of the plurality of delay stages having a delay time with respect to a reference clock signal;
a phase detector to determine the phase of an input signal by sampling the input signal, wherein the phase of the input signal is based on at least one transition in the input signal, the phase detector to generate information indicative of whether a phase of a first clock signal leads or lags the phase of the input signal; and
interpolator circuitry coupled to the plurality of delay stages and the phase detector, the interpolator circuitry to generate the first clock signal using a pair of clock signals of the plurality of clock signals, wherein the phase of the first clock signal is interpolated between respective phases of the pair of clock signals in accordance with the information indicative of whether the phase of the first clock signal leads or lags the phase of the input signal.
1. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
(A) a differential amplifier for generating a differential output signal comprising a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises:
(i) a first transistor coupled to the first node;
(ii) a second transistor coupled to the second node and the first transistor, wherein the first and second transistors are biased by an output level biasing voltage;
(iii) a third transistor coupled to the first node, wherein the third transistor receives a first input signal from a preceding delay stage;
(iv) a fourth transistor coupled to the second node and the third transistor, wherein the fourth transistor receives a second input signal from the preceding delay stage;
(B) a self-biased voltage clamping circuit coupled to the first and second nodes to limit a peak-to-peak voltage swing of the differential output signal; and
(C) a current source coupled to the differential amplifier, the current source varying a bias current through the current source in accordance with a delay bias voltage.
11. A ring oscillator comprising:
a plurality of ring coupled delay stages, each delay stage comprising:
(A) a differential amplifier for generating a first output signal at a first node and a second output signal at a second node, wherein the differential amplifier further comprises:
(i) a first transistor coupled between the first node and a first potential;
(ii) a second transistor coupled between the second node and the first potential, wherein the first and second transistors are biased by an output level biasing voltage;
(iii) a third transistor coupled between the first node and a third node, wherein the third transistor receives a first input signal from a preceding delay stage;
(iv) a fourth transistor coupled between the second node and the third node, wherein the fourth transistor receives a second input signal from the preceding delay stage;
(B) a current source coupled between the third node and a second potential, the current source varying a bias current through the current source in accordance with a delay bias voltage; and
(C) a voltage clamping circuit coupled to the first and second nodes to limit a relative peak-to-peak voltage swing of the first and second output signals without independently clamping each of the first and second nodes.
2. The ring oscillator of claim 1, wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
3. The ring oscillator of claim 2, wherein the first and second diode-coupled transistor are metal-oxide semiconductor transistors.
4. The ring oscillator of claim 2, wherein the first and second diode-coupled transistors are N-type transistors.
5. The ring oscillator of claim 1, wherein the current source further comprises a fifth transistor.
6. The ring oscillator of claim 1 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.
7. The ring oscillator of claim 6 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.
8. The ring oscillator of claim 6 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.
9. The ring oscillator of claim 6 wherein the first and second types are complementary.
10. The ring oscillator of claim 1 wherein each delay stage further comprises a source follower buffer.
12. The ring oscillator of claim 11, wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
13. The ring oscillator of claim 12, wherein the first and second diode-coupled transistors are metal-oxide semiconductor transistors.
14. The ring oscillator of claim 12, wherein the first and second diode-coupled transistors are N-type transistors.
15. The ring oscillator of claim 11, wherein the current source further comprises a fifth transistor.
16. The ring oscillator of claim 11 wherein the first and second transistors are of a first type, wherein the third and fourth transistors are of a second type.
17. The ring oscillator of claim 16 wherein the first and second transistors are P-type and the third and fourth transistors are N-type.
18. The ring oscillator of claim 16 wherein the first and second transistors are N-type and the third and fourth transistors are P-type.
19. The ring oscillator of claim 16 wherein the first and second types are complementary.
20. The ring oscillator of claim 11 wherein each delay stage further comprises a source follower buffer.
22. The ring oscillator of claim 21, wherein the differential amplifier provides a first output signal at a first node and a second output signal at a second node, the first and second output signal forming the differential output signal, wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
24. The ring oscillator of claim 23, wherein the voltage clamping circuit further comprises:
(i) a first diode-coupled transistor; and
(ii) a second diode-coupled transistor, wherein the first and second diode-coupled transistors are cross-coupled between the first and second nodes.
0. 26. The memory device of claim 25 wherein the clock synchronization loop is a phase locked loop circuit.
0. 27. The memory device of claim 25 wherein the timing relationship of each one of the plurality of clock signals is a respective phase offset from a phase of the reference clock signal.
0. 28. The memory device of claim 25 wherein the clock synchronization loop comprises a plurality of delay elements coupled in series, each delay element outputting at least one of the plurality of clock signals.
0. 29. The memory device of claim 28 wherein the plurality of delay elements in an even number of delay elements.
0. 30. The memory device of claim 25 further comprising selection circuitry, coupled to the clock synchronization loop, to select the first and second clock signals from the plurality of clock signals.
0. 31. The memory device of claim 30 further comprising:
a detector circuit to detect a phase polarity between the first internal clock signal and the first external clock signal;
a shift register, coupled in parallel with the selection circuitry, to output selection signals that control selection of the first and second clock signals; and
a control circuit to provide shift information to the shift register based on the phase polarity such that the selection signals output by the shift register select clock signals of the plurality of clock signals that have phases neighboring, on respective either sides, the phase of the first external clock signal.
0. 32. The memory device of claim 25, further comprising:
a detector circuit, coupled to the first interpolator circuitry, to detect the phase information; and
a control circuit to generate a control voltage that is responsive to the phase information, wherein the first interpolator circuitry steers the phase of the first internal clock signal between the phase of the first and second clock signals in response to the control voltage.
0. 33. The memory device of claim 32 wherein after detection the phase information is represented by a binary value.
0. 34. The memory device of claim 32 wherein the control circuit comprises:
a digital counter to generate a digital count value in response to the phase information; and
a digital to analog converter to generate the control voltage from the digital count value.
0. 35. The memory device of claim 25 further comprising a buffer circuit to receive a second external clock signal and generate the reference clock signal using the second external clock signal.
0. 36. The memory device of claim 35 wherein a reception of data is synchronized with the second external clock signal.
0. 37. The memory device of claim 35 wherein the plurality of clock signals comprises a clock signal that is in phase with the second external clock signal.
0. 38. The memory device of claim 25 further comprising second interpolator circuitry to generate a second internal clock signal from a pair of clock signals of the plurality of clock signals, wherein a phase of the second internal clock signal is interpolated from respective phases of the pair of clock signals according to phase information indicative of whether the second internal clock signal leads or lags a second external clock signal.
0. 39. The memory device of claim 25 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.
0. 41. The integrated circuit device of claim 40 wherein the first subloop circuit generates an internal transmit clock signal having a phase relationship with respect to the first external clock signal.
0. 42. The integrated circuit device of claim 41 wherein the phase relationship is a quadrature relationship.
0. 43. The integrated circuit device of claim 41 wherein the internal transmit clock is in phase with the first external clock signal.
0. 44. The integrated circuit device of claim 40 wherein the first subloop circuit further comprises:
selection circuitry to select first and second clock signals of the plurality of clock signals;
interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal transmit clock signal in response to a control signal, wherein the control signal steers the phase of the internal transmit clock signal between respective phases of the first and second clock signals; and
detector circuitry to detect phase information indicative of whether the internal transmit clock signal leads or lags the first external clock signal, and to generate the control signal using the phase information.
0. 45. The integrated circuit device of claim 40 wherein the second subloop circuit generates an internal receive clock signal having a phase relationship with respect to the second external clock signal.
0. 46. The integrated circuit device of claim 45 wherein the internal receive clock signal is in phase with the second external clock signal.
0. 47. The integrated circuit device of claim 40 wherein the second subloop circuit further comprises:
selection circuitry to select first and second clock signals of the plurality of clock signals;
interpolator circuitry to interpolate between the first and second clock signals, and to generate an internal receive clock signal in response to a control signal, wherein the control signal steers the phase of the internal receive clock signal between respective phases of the first and second clock signals; and
detector circuitry to detect phase information indicative of whether the internal receive clock signal leads or lags the second external clock signal, and to generate the control signal using the phase information.
0. 48. The integrated circuit device of claim 40 wherein a first clock signal of the plurality of clock signals is in phase with the second external clock signal, and the other clock signals of the plurality of clock signals have respective phases that are evenly spaced across a clock period of the second external clock signal.
0. 49. The integrated circuit device of claim 40 wherein the reference loop is a phase locked loop circuit.
0. 50. The integrated circuit device of claim 40 wherein the data is transmitted during a plurality of clock edge transitions of the first external clock signal.
0. 51. The integrated circuit device of claim 40 further comprising a buffer circuit to receive the second external clock signal and to generate the reference clock signal from the second external clock signal.
0. 53. The clock synchronization circuit of claim 52 wherein the plurality of delay stages is an even number of delay stages.
0. 54. The clock synchronization circuit of claim 52 further comprising a buffer to output the reference clock signal, wherein the buffer receives the input clock signal.
0. 55. The clock synchronization circuit of claim 52 wherein each delay stage of the plurality of delay stages comprises:
a first output terminal;
a second output terminal;
a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and
a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.
0. 56. The clock synchronization circuit of claim 52 wherein the plurality of delay stages is included in a phase locked loop circuit.
0. 57. The clock synchronization circuit of claim 52 further comprising selection circuitry to select the pair of clock signals from the plurality of clock signals.
0. 58. The clock synchronization circuit of claim 52 wherein the detector circuit comprises a phase detector to compare the phase of the first clock signal with the phase of the input clock signal, the phase detector to generate a binary signal that indicates whether the first clock signal leads or lags the input clock signal.
0. 59. The clock synchronization circuit of claim 52 wherein the detector circuit comprises:
a counter circuit to change a count value in a first direction when the phase of the input clock signal lags the phase of the first clock signal, and change the count value in a second direction when the phase of the input clock signal leads the phase of the first clock signal; and
a digital to analog converter circuit to generate an analog control signal from the count value, wherein the analog control signal steers the phase of the first clock signal between the respective phases of each clock signal of the pair of clock signals.
0. 61. The memory device of claim 60 further comprising:
a second multiplexer circuit, coupled to the plurality of delay stages, to perform selection of a delay time for a second internal clock signal, the selection being controlled by a second plurality of control signals; and
a second shift register circuit to generate the second plurality of control signals in accordance with the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.
0. 62. The memory device of claim 61 further comprising:
interpolator circuitry to generate the internal transmit clock signal by interpolating between phases of the first and a second internal clock signals in accordance with a control voltage; and
a control circuit to generate the control voltage according to the information indicative of whether the phase of the external clock signal leads or lags the phase of the internal transmit clock signal.
0. 63. The memory device of claim 62 wherein the control circuit comprises:
a counter circuit to generate a digital count value based on the information; and
a digital to analog converter to generate the control voltage based on the digital count value.
0. 64. The memory device of claim 60, wherein the first internal clock signal is generated by an output of a delay stage of the plurality of delay stages.
0. 65. The memory device of claim 60 wherein the plurality of delay stages is included in a phase locked loop circuit.
0. 67. The memory device of claim 66 further comprising a shift register coupled to the multiplexer circuit to control selection of the first output signal.
0. 68. The memory device of claim 66 further comprising:
a control circuit to generate a control voltage that is responsive to the information; and
interpolator circuitry to generate the internal transmit clock signal using the first output signal and a second output signal generated by the plurality of delay elements, the phase of the internal transmit clock signal being interpolated between the phases of the first and second output signals in response to the control voltage.
0. 69. The memory device of claim 68 wherein the control circuit comprises:
a digital converter to generate a digital count value in response to the information; and
a digital to analog converter to generate the control voltage using the digital count value.
0. 70. The memory device of claim 66 wherein the plurality of delay elements is included in a phase locked loop circuit.
0. 72. The clock synchronization circuit of claim 71 further comprising detector circuitry coupled to the interpolator circuitry, the detector circuitry to compare the phase of the first clock signal with the target phase, the detector circuitry to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase.
0. 73. The clock synchronization circuit of claim 72 wherein the detector circuitry comprises a counter circuit to change a count value in a first direction when the target phase lags the phase of the first clock signal, and change the count value in a second direction when the target phase leads the phase of the first clock signal, wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is based on the count value.
0. 74. The clock synchronization circuit of claim 73 wherein the information indicative of whether the phase of the first clock signal leads or lags the target phase is provided as an analog control signal, and wherein the detector circuitry further comprises a digital to analog converter circuit coupled to the counter circuit, the digital to analog converter circuit to generate the analog control signal from the count value, wherein the analog control signal controls interpolation between the respective phases of the clock signals of the pair of clock signals to produce the phase of the first clock signal.
0. 75. The clock synchronization circuit of claim 71 wherein the target phase is detected based on sampling of the input signal.
0. 76. The clock synchronization circuit of claim 75 wherein the input signal is sampled using the first clock signal.
0. 77. The clock synchronization circuit of claim 76 wherein the input signal is a clock signal.
0. 78. The clock synchronization circuit of claim 71 wherein the input signal includes clock information.
0. 79. The clock synchronization circuit of claim 78 wherein the input signal is a clock signal.
0. 80. The clock synchronization circuit of claim 79 wherein the input signal and the reference clock signal are both derived from an external clock signal.
0. 81. The clock synchronization circuit of claim 80 wherein the input signal is the reference clock signal.
0. 82. The clock synchronization circuit of claim 71 wherein the plurality of delay stages is an even number of delay stages.
0. 83. The clock synchronization circuit of claim 71 wherein the plurality of delay stages and the interpolator circuitry are formed on a single integrated circuit device.
0. 84. The clock synchronization circuit of claim 83 further comprising a buffer coupled to the interpolator circuitry, the buffer to receive the input signal from external to the integrated circuit device.
0. 85. The clock synchronization circuit of claim 83 further comprising a buffer coupled to the plurality of delay stages, the buffer to receive the reference clock signal from external to the integrated circuit device.
0. 86. The clock synchronization circuit of claim 71 wherein each delay stage of the plurality of delay stages comprises:
a first output terminal;
a second output terminal;
a first transistor having a source, a drain, and a gate, the source and gate being coupled to the first output terminal, and the drain being coupled to the second output terminal; and
a second transistor having a source, a drain, and a gate, the source and gate being coupled to the second output terminal, and the drain being coupled to the first output terminal.
0. 87. The clock synchronization circuit of claim 71 wherein the plurality of delay stages is included in a phase locked loop circuit.
0. 88. The clock synchronization circuit of claim 71 further comprising selection circuitry coupled to the interpolator circuitry, the selection circuitry to select the pair of clock signals from the plurality of clock signals.
0. 89. The clock synchronization circuit of claim 71 further comprising a phase detector to compare the phase of the first clock signal with the target phase, and to generate the information indicative of whether the phase of the first clock signal leads or lags the target phase, wherein the information is represented by a binary signal.
0. 90. The clock synchronization circuit of claim 71 wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.
0. 92. The method of claim 91 wherein detecting phase of the input signal further comprises sampling the input signal.
0. 93. The method of claim 92 wherein sampling the input signal further comprises sampling the input signal based on the first clock signal.
0. 94. The method of claim 93 wherein the input signal is a clock signal.
0. 95. The method of claim 94 wherein the input signal and the reference clock signal are generated from an external clock signal.
0. 96. The method of claim 92 further comprises selecting the pair of clock signals from the plurality of clock signals based on the sampling of the input signal.
0. 97. The method of claim 91 wherein generating the plurality of clock signals further comprises generating the plurality of clock signals using a plurality of delay stages coupled in series, wherein each delay stage of the plurality of delay stages generates complementary outputs, wherein each output of the complementary outputs is one of the plurality of clock signals.
0. 98. The method of claim 91 wherein the input signal includes clock information.
0. 99. The method of claim 98 wherein the input signal is a clock signal.
0. 101. The integrated circuit of claim 100 wherein the phase detector samples the input signal using the first clock signal.
0. 102. The integrated circuit of claim 100 wherein the input signal includes clock information.
0. 103. The integrated circuit of claim 102 wherein the input signal is a clock signal.
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 08/347,844, filed Dec. 1, 1994 (now U.S. Pat. No. 5,596,610), which is a continuation of application Ser. No. 08/161,769, filed Dec. 2, 1993 (now abandoned), which is a divisional of application Ser. No. 07/890,034, filed May 28, 1992 (now abandoned).

FIELD OF INVENTION

The present invention relates to clock synchronization circuitry including a cascaded phase locked loop. In particular the present invention relates to a delay stage for a ring oscillator and a fine phase tuning circuitry, both used in the cascaded phase locked loop.

BACKGROUND OF THE INVENTION

Clock synchronization in integrated circuits is typically performed by a phase locked loop (PLL).

Some prior PLLs use a ring oscillator as a voltage controlled oscillator. A ring oscillator is a chain of inversion elements coupled together in a negative feedback fashion, with each element contributing a delay amount which adds up to half an oscillation period. Some prior phase locked loop implementations using ring oscillators suffer phase offset and deadband problems, which are difficult to minimize without compromising one or the other.

One disadvantage of prior ring oscillators is that the number of phase signals that can be generated are limited by the number of inversion elements contained in the ring oscillator. The number of inversion elements is, in turn, limited by the length of time delay contributed by each inversion element. The greater the time delay of the inversion element, the fewer the number of inversion elements that can be included in the ring oscillator.

Another disadvantage of some prior oscillators is that they must include an odd number of inversion elements to develop a phase shift of greater than 180°C.

Other prior PLLs use voltage controlled delay line to generate the phase shift necessary for oscillation. Such prior PLLs have a limited delay range, typically a clock period or less. Hence, the frequency of operation of such prior PLLs is very limited. Prior PLLs including delay lines also tend to be susceptible to supply noise because of their use of CMOS inverters, which couple supply noise directly into output signals.

SUMMARY AND OBJECTS OF THE INVENTION

One object of the present invention is to provide a method and circuitry for synchronizing internal device functions to an external clock.

Another object of the present invention is to provide a method and circuitry for clock synchronization that allows phase deadband characteristics to be easily optimized.

Another object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of stability characteristics.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of the delay of clock buffers.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes the affect of a cock distribution network on loop stability.

A still further object of the present invention is to provide a method and circuitry for clock synchronization that allows easy optimization of loop bandwidth.

A further object of the present invention is to provide a method and circuitry for clock synchronization that provides high rejection of power supply noise.

Another object of the present invention is to provide a method and circuitry for fine phase adjustment with small static phase error and high loop stability.

Another object of the present invention is to provide a method and circuitry for phase adjustment in which there are no boundary conditions or start up conditions to be concerned with.

Another object of the present invention is to provide a method and circuitry for clock synchronization that provides smooth phase adjustment.

Another object of the present invention is to provide a method and circuitry for clock synchronization that is suitable for a wide range of frequencies.

Another object of the present invention is to provide a method and circuitry for clock synchronization that minimizes restart response time after power down.

Another object of the present invention is to provide a method and circuitry for clock synchronization that compensates for the delays associated with data input circuitry and data output circuitry.

A still further object of the present invention is to provide a method and circuitry for clock synchronization that generates an output signal with an controlled phase offset with respect to the input reference signal.

A method of performing phase adjustment in a phase locked loop is described. First, two phase signals are selected from a multiplicity of phase signals. The two selected phase signals are selected by a select signal. Next, an output signal is generated by interpolating between the two selected phase signals. The contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.

Also described is phase tuning circuitry, which includes a phase selector and a phase interpolator. The phase selector selects two phase signals from a multiplicity of phase signals in response to a select signal. The two selected phase signals are coupled to the phase interpolator. The phase interpolator generates an output signal by interpolating between the two selected phase signals. The relative contribution of each of the two selected phase signals to the output signal is determined by a weighting signal.

Also described is a delay stage for a ring oscillator. The ring oscillator includes an even number of cascaded delay stages. Each delay stage includes a differential amplifier, which generates two complementary output signals. Coupled between the complementary output signals, two voltage clamping means limit the peak-to-peak voltage swing of the output signal. Limiting the peak-to-peak voltage swing of the output signal speeds-up the delay stage and allows the ring oscillator to includes a greater number of delay stages.

Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which:

FIG. 1 is a block diagram of a high speed computer bus.

FIG. 2 is a block diagram of a phase locked loop.

FIG. 3 is a block diagram of the VCO.

FIG. 4 is a diagram of the relationship between the external reference signal and the phase signals output by the VCO.

FIG. 5 is a schematic diagram of a delay stage of the VCO.

FIG. 6 is an illustration of the phase adjustment levels of the phase selection circuitry and the phase interpolator.

FIG. 7 is a detailed block diagram of the receive subloop within the phase locked loop.

FIG. 8 is a schematic diagram of the coarse select control circuit.

FIG. 9 is a block diagram of the even multiplexer and the odd multiplexer.

FIG. 10 is a schematic diagram of a multiplexer select stage.

FIG. 11 is a schematic diagram of the phase interpolator.

FIG. 12 is a timing diagram for a subloop of the phase locked loop.

FIG. 13 is a detailed block diagram of the transmit subloop within the phase locked loop.

FIG. 14 is a block diagram of the out-of-phase even multiplexer and the out-of-phase odd multiplexer.
DETAILED DESCRIPTION

FIG. 1 is a block diagram of a high speed digital computer bus system 20. Devices 30 and 32 use clock synchronization circuitry 36 to synchronize the transfer of data between data bus 38. Clock synchronization circuitry 36 is a cascaded phase locked loop (PLL) 36. The main loop of PLL 36 utilizes a ring voltage controlled oscillator (VCO), which includes an even number of cascaded delay stages of the present invention. Two subloops coupled to the main loop perform fine phase tuning according to the method and circuitry of the present invention to generate two internal clock signals.

As will be described in more detail below, each delay stage of the present invention generates two complementary output signals using a differential amplifier. Coupled between the two complementary output signals, two clamping devices limit the peak-to-peak voltage swing of the complementary output signals. When the delay stages are cascaded together, they provide twelve different phase signals that are used by the subloops.

The method and circuitry for fine phase adjustment used in the subloops also will be described in detail below. Briefly described, the phase tuning circuitry of the present invention includes a phase selector and a phase interpolator. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO of the main loop. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The effect of the even phase signal and the odd phase signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. The weighting signals allow even phase signals and odd phase signals to switch without introducing jitter onto the output signal.

The high speed digital computer bus system 20 of FIG. 1 includes master device 30, slave devices 32, only one of which is shown, and data bus 38. Data bus 38 transfers data between devices 30 and 32 at data rates up to 500 MBytes per second, in the preferred embodiment.

Master device 30 is an intelligent device, such as a microprocessor, an application specific integrated circuit (ASIC), a memory controller, or a graphics engine. Master 30 differs from slave device 32 in that master device 30 initiates data requests, such as requests to read or write slave devices 32.

Slave devices 32 do not include as much intelligence as master device 30 and can only respond to data requests. Slave devices 32 may be dynamic random access memories (DRAMs), static random access memories (SRAMs), read only memories (ROMs), electrically programmable read only memories (EPROMs), or flash memories.

Master device 30 and slave devices 32 transfer data synchronously. That is, data transfers are referenced to the clock edges of clock signals CLOCKFROMMASTER 42 and CLOCKTOMASTER 44. Both clock signals 42 and 44 are generated by clock source 46. Both clock signals 42 and 44 are carried by a single clockline, which turns around near master device 30. From there, the clockline extends back toward clock source 46, where it is terminated. As a result, both CLOCKFROMMASTER 42 and CLOCKTOMASTER 44 run at the same frequency. The phase shift between clock signals 42 and 44 varies depending upon the location of devices 30 and 32 relative to the turnaround in the clockline. The phase difference between clock signals 42 and 44 is approximately 0°C near the turnaround and increases as distance from the turnaround increases.

Slave devices 32 transmit data with the edges of CLOCKTOMASTER 44 and receive data with CLOCKFROMMASTER 42. Analogously, master device 30 transmits data with the edges of CLOCKFROMMASTER 42 and receives data with CLOCKTOMASTER 44. Clock and data signals remain synchronized as they propagate toward their destination because clock lines 42 and 44 and data bus 38 are matched for delay.

Devices 30 and 32 interface with data bus 38 and clock signals 42 and 44 using interface 34. Interface 34 performs a number of tasks. Among those tasks, interface 34 converts the low voltage levels of data bus 38 to ordinary CMOS levels. Interface 34 also generates internal clocks for receiving and transmitting data. Interface 34 uses clock synchronization circuitry 36 to perform voltage level conversion and clock synchronization.

FIG. 2 illustrates in block diagram form clock synchronization circuitry 36 that is the heart of interface 34. Phase locked loop 36 synchronizes the reception of data to the device's external receive clock, CLOCKTOMASTER 44 or CLOCKFROMMASTER 42, as the case may be. Similarly, phase locked loop 36 synchronizes the transmission of data with the device's external transmit clock, CLOCKTOMASTER 44 or CLOCKFROMMASTER 42, as the case may be.

Phase locked loop 36 performs both synchronization tasks using a cascaded design, which includes main loop 52 and two subloops, a receive subloop 54 and a transmit subloop 56. Main loop 52 acquires and tracks frequency, outputting 12 phase signals, PH(11:0) 58, all with the same frequency, to subloops 54 and 56. Subloops 54 and 56 perform fine phase tracking of clock signals 42 and 44 by selecting two phase signals from PH(11:0) 58. The two selected phase signals are interpolated to generate internal receive and transmit clock signals, INTRCLK 60, INTTCLK 62, and LEADING INTTCLK 63. INTRCLK 60 is in-phase with external receive clock 42. INTTCLK 62 is also in phase with its external reference clock signal, TCLKS 44. In contrast, LEADING INTTCLK 63 leads TCLKS 44 by 90°C in a preferred embodiment.

Main loop 52 uses a conventional second order architecture to track and acquire signal frequencies ranging from 50 MHz to 250 MHz. Main loop 52 has a short pull in time of less than 10 usec. The amount of static phase error generated by main loop 52 has no affect upon the phase tracking accuracy of PLL 36 because subloops 54 and 56 perform phase acquisition. Thus, static phase error in main loop 52 may be, and is, traded for reduced deadband and improved stability characteristics. In contrast, the jitter of phase signals PH(11:0) 58 is minimized because it directly affects the jitter within subloops 54 and 56.

Optimization of the stability of phase signals PH(11:0) 58 is further aided by the cascaded design of PLL 36. Clock distribution and buffering is performed by subloops 54 and 56, rather than main loop 52. Thus, main loop stability is unaffected by buffer and clock distribution delay. Consequently, main loop bandwidth may be easily optimized and the size of filter c, clock buffer 126c, and output buffer delay compensation circuit 127. As its name implies, output buffer delay compensation circuit 127 allows subloop 56 to compensate for the delay contributed to INTTCLK 62 by the output buffers of interface 34. The open loop includes phase select circuitry 121, out-of-phase interpolator 122b, amplifier 124b, and clock buffer 126b.

The heart of subloop 56 is phase select circuitry 121, in-phase phase interpolator 122c, and out-of-phase interpolator 122b. Phase select circuitry 121 performs coarse phase tuning for both the open loop and the closed loop within subloop 56. Each phase interpolator 122b and 122c generates a fine-tuned signal that lies between the two pairs of phase signals coupled to it by phase selector 121. Like subloop 54, both loops with subloop 56 generate 16 fine levels of adjustment between each coarse adjustment level.

Phase select circuitry 121 gives rise to a major difference between subloop 54 and subloop 56. Unlike phase select circuitry 120, phase select circuitry 121 selects two pairs of even phase output signals and two pairs of odd phase output signals. One set of pairs of even and odd phase output signals 248 and 268 is in-phase with TCLKS 44 and are coupled to in-phase phase interpolator 122c. The other set of pairs of even and odd phase output signals 249 and 269 are out-of-phase with TCLKS 44 and are coupled to out-of-phase phase interpolator 122b.

The cooperation of phase select circuitry 121 and phase interpolators 122b and 122c can be understood in greater detail with reference to FIG. 13. As can be seen, portion 57 closely resembles portion 55. For this reason, the following description of portion 57 focuses on its differences as compared to portion 55. Unless otherwise stated, portion 57 functions like portion 55, as described with reference to FIGS. 7-12.

The primary difference between phase select circuitry 120 and phase select circuitry 121 arises from even select circuit 241 and odd select circuit 261. Where even select circuit 240 included only one even multiplexer, even select circuit 241 includes two, in-phase even multiplexer 246 and out-of-phase even multiplexer 247. Multiplexers 246 and 247 are identical and receive identical input signals, even select signals 244 and phase signals 58. Even select signals 244 are coupled to multiplexers 246 and 247 in different fashions, however. As a result, in-phase even multiplexer 246 outputs signals 248 that are substantially in-phase with TCLKS 44, while out-of-phase multiplexer 247 outputs signals 249 that are out-of-phase with TCLKS 44.

Similar to even select circuit 241, odd select circuit 261 includes two odd multiplexers 266 and 267. In-phase odd multiplexer 266 and out-of-phase odd multiplexer 267 are identical and receive identical input signals, odd select signals 264 and phase signals 58. These input signals 264 and 58 are coupled to multiplexers 266 and 267 in differing fashions such that in-phase odd multiplexer 266 outputs signals 268 in substantially in-phase with TCLKS 44 and out-of-phase odd multiplexer 267 outputs signals out-of-phase with TCLKS 44.

In-phase even multiplexer 246 and in-phase odd multiplexer 266 are coupled to even select signals 244, odd select signals 264, and phase signals 58 as shown in FIG. 9. The coupling of even select signals 244, odd select signals 266, and phase signals 58 is shown in FIG. 14. For simplicity's sake, the pull-up circuitry associated with multiplexer 247 and odd multiplexer 267 has been omitted. In the embodiment shown, out-of-phase even phase output signals 249 and out-of-phase odd phase output signals 269 lead their in-phase counterparts 248 and 268 by substantially 90°C. This phase shift in the out-of-phase multiplexer is achieved by associating each select signal with a phase signal 58 that leads by 90°C the phase signal associated with that same select signal in the corresponding in-phase multiplexer. For example, in in-phase even multiplexer 246 even select signal ES0 selects phase signal PH090. In contrast, out-of-phase even multiplexer 247 selects PH9108 using ES0. Analogously, while OS3 is used to select PH7 in in-phase odd multiplexer 266, OS3 is used to select PH498 in out-of-phase odd multiplexer 267.

The degree of phase shift between signals 248 and 249, and 268 and 269, may be arbitrarily selected in other embodiments simply by altering which select signal selects which phase signal in out-of-phase multiplexers 247 and 267.

Out-of-phase phase interpolator 122b uses the output of out-of-phase multiplexers 247 and 267 to generate PIOUT- 90°C 123b. Out-of-phase interpolator 122b also responds to EVENWEIGHT 218 and ODDWEIGHT 220, as discussed with respect to FIGS. 7-12.

Thus, circuitry for performing fine phase adjustment within a phase locked loop has been described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select signal, respectively. The phase interpolator interpolates between the even phase signal and the odd phase signal to generate an output signal. The affect of each phase input signal on the output signal is determined by an even weighting signal and an odd weighting signal, respectively. Together, the weighting signals and the switching mechanisms of the phase select circuitry prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching.

A method of performing fine phase adjustment in a phase locked loop has also been described. First, two phase signals are selected from a multiplicity of phase signals. The two phase signals are selected by a select signal. Next, an output signal is generated by interpolating between the two phase signals. The contribution of each of the two phase signals to the output signal is determined by a weighting signal. The weighting signals prevent glitches from appearing on the output signal when either the even phase signal or the odd phase signal is switching.

Finally, a delay stage for a ring oscillator has also been described. Each delay stage includes a differential amplifier, which generates two complementary output signals. Coupled between the complementary output signals, two voltage clamping means limit the peak-to-peak voltage swing of the output signal. Limiting the peak-to-peak voltage swing of the output signal speeds-up the delay stage and allows the ring oscillator to include a greater number of delay stages, and increases the power supply rejection of the oscillator.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

INVENTORS:

Leung, Wingyu, Horowitz, Mark A.

THIS PATENT IS REFERENCED BY THESE PATENTS:
Patent Priority Assignee Title
10310999, Oct 19 1999 Rambus Inc Flash memory controller with calibrated data communication
10678296, Aug 03 2018 FUTUREWEI TECHNOLOGIES, INC Multi-phase signal generation
10972108, Dec 06 2019 Qualcomm Incorporated Systems and methods for reduction of in-phase and quadrature-phase (IQ) clock skew
11782475, Aug 03 2018 Huawei Technologies Co., Ltd. Multi-phase signal generation
6812799, Aug 29 2002 Micron Technology, Inc. Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals
6906566, Oct 09 2001 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Dual-phase delay-locked loop circuit and method
6924686, Jun 20 2002 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line
6930524, Oct 09 2001 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Dual-phase delay-locked loop circuit and method
6947510, Jun 09 2000 Texas Instruments Incorporated Circuit for generating an output phase signal with a variable phase shift relative to a reference phase
6950956, Oct 19 1999 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
7149145, Jul 19 2004 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Delay stage-interweaved analog DLL/PLL
7158587, Sep 18 2001 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
7234642, Jun 16 2000 Mineral Lassen LLC Memory device
7397725, Oct 19 1999 Rambus Inc. Single-clock, strobeless signaling system
7426247, Sep 18 2001 BROADCOM INTERNATIONAL PTE LTD Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
7587012, Jul 08 2004 Cadence Design Systems, INC Dual loop clock recovery circuit
7663966, Oct 19 1999 Rambus, Inc. Single-clock, strobeless signaling system
7793844, Jun 16 2000 Mineral Lassen LLC Memory device
7835205, Jul 19 2004 U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT Delay stage-interweaved analog DLL/PLL
8036300, Jul 08 2004 Rambus, Inc. Dual loop clock recovery circuit
8085893, Sep 13 2005 Rambus, Inc. Low jitter clock recovery circuit
8102730, Oct 19 1999 Rambus, Inc. Single-clock, strobeless signaling system
8113433, Jun 15 2001 Mineral Lassen LLC Memory device
8170067, Oct 19 1999 Rambus Inc. Memory system with calibrated data communication
8630317, Oct 19 1999 Rambus Inc. Memory system with calibrated data communication
8903031, Sep 13 2005 Rambus Inc. Low jitter clock recovery circuit
8948212, Oct 19 1999 Rambus Inc. Memory controller with circuitry to set memory device-specific reference voltages
8995598, Sep 13 2005 Rambus Inc. Low jitter clock recovery circuit
9036764, Dec 07 2012 Rambus Inc. Clock recovery circuit
9164933, Oct 19 1999 Rambus Inc. Memory system with calibrated data communication
9209966, Dec 07 2012 Rambus Inc. Clock recovery circuit
9405678, Oct 19 1999 Rambus Inc. Flash memory controller with calibrated data communication
9565036, Jun 30 2009 Rambus Inc Techniques for adjusting clock signals to compensate for noise
9785589, Oct 19 1999 Rambus Inc. Memory controller that calibrates a transmit timing offset
THIS PATENT REFERENCES THESE PATENTS:
Patent Priority Assignee Title
4099266, Feb 25 1977 Data General Corporation Single-chip bi-polar sense amplifier for a data processing system using MOS memory
4231104, Apr 26 1978 Teradyne, Inc. Generating timing signals
4247817, May 15 1978 Teradyne, Inc. Transmitting electrical signals with a transmission time independent of distance between transmitter and receiver
4481625, Oct 21 1981 INTEL CORPORATION, A DE CORP ; ELXSI CORPORATION, A DE CORP ; TRILOGY SYSTEMS CORPORATION, A CORP OF CALIFORNIA High speed data bus system
4494021, Aug 30 1982 Xerox Corporation Self-calibrated clock and timing signal generator for MOS/VLSI circuitry
4519034, Jun 30 1982 INTEL CORPORATION, A DE CORP ; ELXSI CORPORATION, A DE CORP I/O Bus clock
4600943, Nov 09 1982 Tokyo Shibaura Denki Kabushiki Kaisha Sampling pulse generator
4637018, Aug 29 1984 Unisys Corporation Automatic signal delay adjustment method
4641048, Aug 24 1984 Tektronix, Inc. Digital integrated circuit propagation delay time controller
4785394, Sep 19 1986 Datapoint Corporation Fair arbitration technique for a split transaction bus in a multiprocessor computer system
4808944, Nov 23 1987 TriQuint Semiconductor, Inc.; TRIQUINT SEMICONDUCTOR, INC , AN OREGON CORP High accuracy differential output stage
4811202, Oct 01 1981 Texas Instruments Incorporated Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package
4815113, Oct 21 1986 International Business Machines Corporation Method for digital slope control of output signals of power amplifiers in semiconductor chips
4815202, May 02 1988 Emhart Inc Electronic component insertion machine
4831338, May 13 1987 Synchronizing clock signal generator
4841551, Jan 05 1987 Grumman Aerospace Corporation High speed data-clock synchronization processor
4845670, Feb 18 1986 MATSUSHITA ELECTRIC INDUSTRIAL CO , LTD Memory device using shift-register
4859970, Nov 30 1987 Kabushiki Kaisha Toshiba Voltage controlled oscillator
4860198, Jan 31 1985 Kabushiki Kaisha Toshiba Microprocessor system
4888729, May 06 1988 ALCATEL NETWORK SYSTEM INC Digitally controlled oscillator apparatus
4893095, Aug 04 1987 U S PHILIPS CORPORATION, A CORP OF DE Frequency stabilized oscillator
4953128, Dec 16 1986 Mitsubishi Denki Kabushiki Kaisha Variable delay circuit for delaying input data
5010303, Dec 08 1989 Motorola, Inc. Balanced integrated circuit differential amplifier
5036528, Jan 29 1990 HEWLETT-PACKARD DEVELOPMENT COMPANY, L P Self-calibrating clock synchronization system
5095284, Sep 10 1990 Synaptics, Incorporated Subthreshold CMOS amplifier with wide input voltage range
5126692, Aug 03 1987 BANKBOSTON, N A , AS AGENT Variable frequency system having linear combination of charge pump and voltage controlled oscillator
5140688, Nov 10 1986 Texas Instruments Incorporated GaAs integrated circuit programmable delay line element
5142244, May 06 1991 Intersil Corporation Full range input/output comparator
5166641, Mar 17 1992 National Semiconductor Corporation Phase-locked loop with automatic phase offset calibration
5180994, Feb 14 1991 Regents of the University of California, The Differential-logic ring oscillator with quadrature outputs
5182525, Dec 22 1990 Deutsche ITT Industries GmbH CMOS transconductance amplifier with floating operating point
5191301, May 12 1992 International Business Machines Corporation; INTERNATIONAL BUSINESS MACHINES CORPORATION A CORP OF NEW YORK Integrated differential voltage controlled ring oscillator
5198780, May 28 1990 Freescale Semiconductor, Inc Adjustable gain differential amplifier
5206550, Jun 20 1991 Texas Instruments, Incorporated; Texas Instruments Incorporated Amplifier with actively clamped load
5206609, May 15 1992 Freescale Semiconductor, Inc Current controlled oscillator with linear output frequency
5210236, Sep 21 1990 Kabushiki Kaisha Toshiba Differential amplifier
5220294, May 21 1990 NEC Electronics Corporation Phase-locked loop circuit
5239274, May 26 1992 HEWLETT-PACKARD DEVELOPMENT COMPANY, L P Voltage-controlled ring oscillator using complementary differential buffers for generating multiple phase signals
5245637, Dec 30 1991 INTERNATIONAL BUSINESS MACHINES CORPORATION, A CORPORATION OF NEW YORK Phase and frequency adjustable digital phase lock logic system
5285173, Jul 13 1992 Analog Devices, Inc. Signal-controlled ring oscillator with delay cells having constant gain with change in frequency
5298870, Jul 18 1991 STMicroelectronics, Inc Voltage controlled ring oscillator having differential amplifier stages
5300898, Jul 29 1992 TAIWAN SEMICONDUCTOR MANUFACTURING CO , LTD High speed current/voltage controlled ring oscillator circuit
5302920, Oct 13 1992 MAGNACHIP SEMICONDUCTOR LTD Controllable multi-phase ring oscillators with variable current sources and capacitances
5361277, Apr 27 1988 Alberta Telecommunications Research Centre Method and apparatus for clock distribution and for distributed clock synchronization
5446418, Nov 06 1992 Mitsubishi Denki Kabushiki Kaisha Ring oscillator and constant voltage generation circuit
5596610, May 28 1992 Rambus, Inc. Delay stage circuitry for a ring oscillator
5818740, Sep 23 1991 Lucent Technologies Inc. Decimator for use with a modem with time invariant echo path
6049846, Apr 18 1990 Rambus Inc. Integrated circuit having memory which synchronously samples information with respect to external clock signals
GB2197553,
JP61228720,
WO8912936,
WO9116680,
ASSIGNMENT RECORDS    Assignment records on the USPTO
/
Executed onAssignorAssigneeConveyanceFrameReelDoc
Aug 02 2000Rambus Inc.(assignment on the face of the patent)
MAINTENANCE FEES AND DATES:    Maintenance records on the USPTO
Date Maintenance Fee Events
Feb 27 2006M1552: Payment of Maintenance Fee, 8th Year, Large Entity.
Feb 25 2010M1553: Payment of Maintenance Fee, 12th Year, Large Entity.


Date Maintenance Schedule
Mar 30 20074 years fee payment window open
Sep 30 20076 months grace period start (w surcharge)
Mar 30 2008patent expiry (for year 4)
Mar 30 20102 years to revive unintentionally abandoned end. (for year 4)
Mar 30 20118 years fee payment window open
Sep 30 20116 months grace period start (w surcharge)
Mar 30 2012patent expiry (for year 8)
Mar 30 20142 years to revive unintentionally abandoned end. (for year 8)
Mar 30 201512 years fee payment window open
Sep 30 20156 months grace period start (w surcharge)
Mar 30 2016patent expiry (for year 12)
Mar 30 20182 years to revive unintentionally abandoned end. (for year 12)