A self-diagnostic arrangement for a video display apparatus and method effectuating the same is disclosed. The apparatus according to the present invention includes a cable connector, amplifiers and a cathode ray tube and comprises a microprocessor storing information on a display status, for selectively switching signals to generate horizontal and vertical sync signals for displaying a variety of self-diagnostic displays, an on screen display IC for supplying a blanking signal and a video signal correspondingly responsive to information supplied from the microprocessor and a H/V deflection circuit for supplying on screen display video. signals to the CRT. There is also provided a method of self-diagnosis, which comprises the steps of generating internal horizontal and vertical sync.signals sync signals of predetermined frequency levels and displaying self-diagnostic screens representing video component colors and a display status.
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0. 76. A video display apparatus, comprising:
a video display device providing displays of variable video images; and a controller connected to said video display device, monitoring an operational connection providing reception of externally generated signals for said video images, determining a state of said connection, generating an internal video signal in dependence upon said state of said connection, applying to said video display device said internal video signal for said video image.
0. 23. A method for self-diagnosis testing of a video display apparatus including a cable connector, a microprocessor, on-screen display circuit and a display screen, said method comprising the steps of:
checking said cable connector to determine connection to an external system; generating horizontal and vertical synchronizing frequencies in case of no connection between said cable connector and external system; and outputting a message display signal to said circuit responsive to an input signal supplied from said microprocessor.
2. A method for self-diagnosis testing of a video display apparatus including a cable connector, a microprocessor, on-screen display means and a cathode ray tube, said method comprising the steps of:
checking said cable connector to determine connection to an external system; generating horizontal and vertical synchronizing frequencies in said microprocessor in case of no connection between said cable connector and external system; and outputting a self-diagnosis display signal to said cathode ray tube from said on-screen display means responsive to an input signal supplied from said microprocessor.
0. 11. A method of generating a self-diagnostics video display, comprising the steps of:
checking a cable connector of a video display apparatus including a cable connector, a microprocessor, on-screen display circuit and a display means to determine connection to an external system; generating horizontal and vertical synchronizing frequencies in said microprocessor when no connection is detected between said cable connector and external system; and outputting a self-diagnosis display signal to said display means from said on-screen display circuit responsive to an input signal supplied from said microprocessor.
1. A video display apparatus including a microprocessor, on-screen display integrated circuit and a cathode ray tube, characterized in that:
the microprocessor receives horizontal and vertical synchronization frequencies, generates internal horizontal and vertical synchronization frequencies and determines a state of connection between said apparatus and an external system; and the cathode ray tube is fed with either one of said horizontal and vertical synchronization frequencies or said internal horizontal and vertical synchronization frequencies determined by said microprocessor in response to the state of connection.
0. 28. A video display apparatus, comprising:
a video device providing displays of variable video images; a circuit driving said video device to provide said displays; and a controller monitoring reception of external horizontal and vertical timing signals, generating internal horizontal and vertical timing signals, determining a state of signal connection between said circuit and an external system supplying video signals, and selectively applying to said circuit one of said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals as determined by said controller in dependence upon said state of connection between said circuit and said external system.
0. 18. A method for self-diagnosis testing of a video display apparatus including a cable connector to which a signal cable of an external system is engagedly connected, a circuit controlling a video signal input via said cable connector and a display means for displaying said video signal input from said circuit, said method comprising the steps of:
generating internally generated horizontal and vertical synchronizing signals of predetermined frequencies, respectively, when there is no connection between said signal cable and cable connector; and generating signals for at least two self-diagnostic displays representing a detail of video component colors and a display status from predetermined data stored in said apparatus.
0. 17. A method of generating a self-diagnostics video display, comprising:
making a determination of whether a signal cable of a video device providing displays of variable video images is connected to a cable connector supplying a video signal; generating internal horizontal and vertical synchronizing signals when said determination indicates that said signal cable is not connected to a cable connector supplying a video signal; displaying an initial menu of a plurality of self-diagnostic functions; soliciting an input by key-stroke manipulation via a video display on said video device; and responding to said key-stroke by displaying on said video device a detail of self-diagnostic information corresponding to said key-stroke.
4. A method for self-diagnosis of a video display apparatus including a cable connector to which a signal cable of an external system is engagedly connected, amplifier means for amplifying a video signal input via said cable connector and a cathode ray tube for displaying said amplified video signal input from said amplifier means, said method comprising the steps of:
a first process for generating internally generated horizontal and vertical synchronizing signals of predetermined frequencies, respectively, on an occasion of no connection between said signal cable and cable connector; and a second process for generating signals for at least two self-diagnosis display screens representing a detail of video component colors and display status from predetermined data stored in said apparatus.
0. 30. A video display apparatus, comprising:
a video device providing displays of variable video images; a circuit disposed to receive externally generated video signals, driving said video device to provide said displays; and a controller monitoring a connection providing reception of external horizontal and vertical timing signals, generating internal horizontal and vertical timing signals, determining a state of signal connection between said circuit and an external system supplying said externally generated video signals, and selectively applying to said circuit one of said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals as determined by said controller in dependence upon said state of connection between said circuit and said external system.
0. 10. A video display apparatus, comprising:
a video device providing displays of variable video images; a circuit driving said video device to provide said displays; and a microprocessor based controller monitoring reception of external horizontal and vertical synchronization frequencies, generating internal horizontal and vertical synchronization frequencies and determining a state of signal connection between said video device and an external system supplying video signals and selectively applying to said circuit one of said external horizontal and vertical synchronization frequencies and said internal horizontal and vertical synchronization frequencies to control said displays as determined by said controller in dependence upon said state of connection between said video device and said external system.
0. 69. A video display process, comprising:
arranging an operational connection to separately and individually receive externally generated video signals, externally generated horizontal and vertical timing signals, and a synchronization ground signal; monitoring a state of said connection; generating internal horizontal and vertical timing signals; making a determination of a state of said operational connection; selectively transmitting one of said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals in dependence upon said determination of said state of connection; and driving a video device to provide visual displays of variable video images, in correspondence with said one of said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals transmitted.
0. 47. A video display process, comprising:
arranging an operational connection to receive externally generated video signals and externally generated horizontal and vertical timing signals; monitoring a connection providing reception of said external horizontal and vertical timing signals; generating internal horizontal and vertical timing signals; making a determination of a state of said operational connection; selectively transmitting one of said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals in dependence upon said determination of said state of connection; and driving a video device to provide visual displays of variable video images, in correspondence with said one of said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals transmitted.
0. 62. A video display apparatus, comprising:
a video device providing displays of variable video images; a controller monitoring a connection providing separate and individual reception of externally generated video signals, external horizontal and vertical timing signals and a synchronization ground signal, generating internal horizontal and vertical timing signals, determining a state of said connection, selectively generating internal video signals, and supplying output horizontal and vertical timing signals selected from among said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals as determined by said controller in dependence upon said state of connection; and a circuit disposed to receive said externally generated video signals, driving said video device in response to said output horizontal and vertical timing signals, while under control of said controller to provide said displays in correspondence with selections by said controller from among said externally generated video signals and said internally generated video signals and image control data.
5. A video display apparatus including a cable connector to which a signal cable of an external system is engagedly connected, an amplifier for receiving a first video signal supplied via said cable connector and a cathode ray tube for displaying said signal input from said amplifier, said apparatus comprising:
a microprocessor storing information for an image status being displayed, for selectively switching between internal horizontal and vertical synchronizing signals from an internal generator and external horizontal and vertical synchronizing signals from said external system to provide output horizontal and vertical synchronizing signals having predetermined frequency levels based on a connection status between said signal cable and said cable connector; means for supplying a plurality of second video signals corresponding to said stored information provided by said microprocessor to said amplifier; and horizontal and vertical deflection circuits, responsive to said output horizontal and vertical synchronizing signals input from said microprocessor, for supplying horizontal and vertical deflection signals to said cathode ray tube.
0. 21. A video display apparatus, comprising:
a cable connector disposed to be functionally connected to a signal cable of an external system supplying a first video signal; an amplifier receiving said first video signal supplied via said cable connector and a display means for displaying said signal input from said amplifier; a microprocessor storing information for an image status being displayed, for selectively switching between internal horizontal and vertical synchronizing signals from an internal generator and external horizontal and vertical synchronizing signals from said external system to provide output horizontal and vertical synchronizing signals having predetermined frequency levels based on a connection status between said signal cable and said cable connector; means for supplying a plurality of second video signals corresponding to said stored information provided by said microprocessor to said amplifier; and horizontal and vertical deflection circuits, responsive to said output horizontal and vertical synchronizing signals input from said microprocessor, for supplying horizontal and vertical deflection signals to said display means.
0. 55. A video display process, comprising:
arranging an operational connection to receive externally generated video signals and externally generated horizontal and vertical timing signals; monitoring a connection providing reception of said externally generated horizontal and vertical timing signals; generating internal horizontal and vertical timing signals; making a determination of a state of said operational connection with an external system supplying said externally generated video signals; selectively generating internal video signals and image control data; transmitting output horizontal and vertical timing signals selected from among said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals as in dependence upon said determination of said state of said operational connection between said circuit and said external system; and driving said video device in response to said output horizontal and vertical timing signals, while under control to provide said displays in correspondence with selections from among said externally generated video signals and said internally generated video signals and image control data.
0. 41. A video display apparatus, comprising:
a video device providing displays of variable video images; a controller monitoring a connection providing reception of external horizontal and vertical timing signals, generating internal horizontal and vertical timing signals, determining a state of signal connection with an external system supplying externally generated video signals, selectively generating internal video signals and image control data, and supplying output horizontal and vertical timing signals selected from among said external horizontal and vertical timing signals and said internal horizontal and vertical timing signals as determined by said controller in dependence upon said state of connection between said circuit and said external system; and a circuit disposed to receive said externally generated video signals from said external system, driving said video device in response to said output horizontal and vertical timing signals, while under control of said controller to provide said displays in correspondence with selections by said controller from among said externally generated video signals and said internally generated video signals and image control data.
0. 9. A video display apparatus, comprising:
a signal cable; a cable connector for connecting the video display apparatus to an external system; a microprocessor stage having key input ports, a horizontal input terminal and a vertical input terminal respectively disposed to receive an external horizontal synchronizing signal and an external vertical synchronizing signal from said external system via said signal cable, said microprocessor comprising a generator generating an internal horizontal synchronizing signal and an internal vertical synchronizing signal and selectively outputting one of said external horizontal synchronizing signal and said internal horizontal synchronizing signal and one of said external vertical synchronizing signal and said internal vertical synchronizing signal, said microprocessor stage storing self-diagnostic video information; a horizontal and vertical deflection stage generating horizontal and vertical flyback signals in response to the horizontal and vertical synchronizing signals output by said microprocessor stage; a video device generating an on-screen display comprising color components and a blanking signal corresponding to said self-diagnostic video information and said horizontal and vertical flyback signals for generating an on screen display video signal comprising color components and a blanking signal; a preamplifier outputting an amplified signal corresponding to an external video signal received from said cable connector and said on screen display video signal; and a video amplifier driving said video device to provide said on-screen display by amplifying said amplified video signal.
3. The method of
detecting an input signal from a key pad; and displaying a pre-stored self-diagnostic display on a screen of said cathode ray tube in response to said input signal from said key pad.
6. The video display apparatus of
oscillator means for generating an oscillation clock frequency; horizontal and vertical synchronizing circuits as said internal generator for generating said internal horizontal and vertical synchronizing signals using said oscillation clock frequency; and a pair of switches for selectively switching between said internal horizontal and vertical synchronizing signals and said external horizontal and vertical synchronizing signals.
7. The video display apparatus of
8. The video display apparatus of
0. 12. The method of
detecting an input signal from a key pad; and displaying a pre-stored self-diagnostic display on said display means in response to said input signal from said key pad.
0. 13. The method of
0. 14. The method of
0. 15. The method of
0. 16. The method of
0. 19. The video display apparatus of
oscillator means for generating an oscillation clock frequency; horizontal and vertical synchronizing circuits as said internal generator for generating said internal horizontal and vertical synchronizing signals using said oscillation clock frequency; and a pair of switches for selectively switching between said internal horizontal and vertical synchronizing signals and said external horizontal and vertical synchronizing signals.
0. 20. The video display apparatus of
0. 22. The video display apparatus of
0. 24. The method of
0. 25. The method of
0. 26. The method of
0. 27. The method of
detecting an input signal from a key pad; and displaying a pre-stored self-diagnostic display on a screen of said cathode ray tube in response to said input signal from said key pad.
0. 29. The video display apparatus of
said controller storing information and selectively applying to said circuit video signals representing said information and data controlling horizontal position, vertical position and size of said displays.
0. 31. The video display apparatus of
0. 32. The video display apparatus of
0. 33. The video display apparatus of
0. 34. The video display apparatus of
0. 35. The video display apparatus of
a horizontal and vertical deflection stage responding to said image control data and said output horizontal and vertical timing signals by generating vertical deflection signals and horizontal deflection signals; an on-screen display generating on-screen video component signals and on-screen blanking signals in correspondence with said image control data and said vertical deflection signals and horizontal deflection signals; and an amplifier driving the display device in dependence upon said externally generated video signals, said on-screen video component signals, and said on-screen blanking signals.
0. 36. The video display apparatus of
0. 37. The video display apparatus of
0. 38. The video display apparatus of
0. 39. The video display apparatus of
0. 40. The video display apparatus of
0. 42. The video display apparatus of
0. 43. The video display apparatus of
0. 44. The video display apparatus of
0. 45. The video display apparatus of
a horizontal and vertical deflection stage responding to said image control data and said output horizontal and vertical timing signals by generating vertical deflection signals and horizontal deflection signals; an on-screen display generating on-screen video component signals and on-screen blanking signals in correspondence with said image control data and said vertical deflection signals and horizontal deflection signals; and an amplifier driving the display device in dependence upon said externally generated video signals, said on-screen video component signals, and said on-screen blanking signals.
0. 46. The video display apparatus of
0. 48. The video display process of
0. 49. The video display process of
0. 50. The video display process of
0. 51. The video display process of
0. 52. The video display process of
storing second video signals representing predetermined images and image control data indicative of parameters of said displays; responding to said image control data and said one of said external horizontal and vertical timing signals and internal horizontal and vertical timing signals selectively transmitted, by generating vertical deflection signals and horizontal deflection signals; generating on-screen video component signals and on-screen blanking signals in correspondence with said image control data and said vertical deflection signals and horizontal deflection signals; and driving the display device in dependence upon said externally generated video signals, said on-screen video component signals, and said on-screen blanking signals.
0. 53. The video display process of
0. 54. The video display apparatus of
0. 56. The video display process of
0. 57. The video display process of
0. 58. The video display process of
0. 59. The video display process of
0. 60. The video display process of
storing second video signals representing predetermined images and image control data indicative of parameters of said displays; responding to said image control data and said one of said external horizontal and vertical timing signals and internal horizontal and vertical timing signals selectively transmitted, by generating vertical deflection signals and horizontal deflection signals; generating on-screen video component signals and on-screen blanking signals in correspondence with said image control data and said vertical deflection signals and horizontal deflection signals; and driving the display device in dependence upon said externally generated video signals, said on-screen video component signals, and said on-screen blanking signals.
0. 61. The video display process of
0. 63. The video display apparatus of
0. 64. The video display apparatus of
0. 65. The video display apparatus of
0. 66. The video display apparatus of
0. 67. The video display apparatus of
0. 68. The video display apparatus of
0. 70. The video display process of
0. 71. The video display process of
0. 72. The video display process of
0. 73. The video display process of
0. 74. The video display process of
0. 75. The video display process of
0. 77. The video display apparatus of
0. 78. The video display apparatus of
0. 79. The video display apparatus of
0. 80. The video display apparatus of
0. 81. The video display apparatus of
0. 82. The video display apparatus of
0. 83. The video display apparatus of
0. 84. The video display process, comprising the steps of:
monitoring an operational connection providing reception of externally generated signals; making a determination a state of said connection; generating an internal video signal in dependence upon said determination of said state of said connection; and applying said internal video signal to a video display device providing displays of video images.
0. 85. The video display process of
0. 86. The video display process of
0. 87. The video display process of
0. 88. The video display process of
0. 89. The video display process of
0. 90. The video display process of
0. 91. The video display process of
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This application make reference to, incorporates the same herein, and claims all benefits acruing under 35 U.S.C §119 from an application entitled A DISPLAY APPARATUS HAVING SELF-DIAGNOSTIC FUNCTION earlier filed in the Korean Industrial Property Office on 22 Oct. 1994 and assigned Ser. No. 27039/1994.
The present invention relates to an apparatus for a video display, and
Turning now to the drawings and referring to
A video pre-amplifier 3, receives the RGB video signal from cable connector 1, amplifies the received RGB video signal and then mixes the amplified RGB video signal with a video signal supplied from an on-screen display integrated circuit (hereinafter, referred to as an "OSD video signal") for output to a video main amplifier 5. Video main amplifier 5 amplifies the magnitude of the mixed video signal output from video pre-amplifier 3, to the extent capable of driving a cathode ray tube (CRT) 13, and thus outputs an amplified mixed video signal to CRT 13.
A microprocessor 7 detects the frequency level of the external H/V sync signal XHSYNC and XVSYNC fed via cable connector 1, determines the type of video mode currently being supplied, then adjusts deflection parameters and controls horizontal and vertical deflection integrated circuit 11 so as to accurately display a determined current video mode.
Also, microprocessor 7 scans for a key input signal from a key pad (not shown) such that a video display is controlled according to a function corresponding to a key input signal.
In a self-raster display mode, particularly, the on-screen display pattern is arbitrarily interchangeable as a function of microprocessor 7, the construction of which will be described in detail with respect to FIG. 2.
On-screen display integrated circuit OSD IC 9 is adapted for display information using video signals SS stored in microprocessor 7, and for the sake of easy manipulation of a video display apparatus such as a monitor, receives as inputs a control clock signal CLK and data DATA pertaining to image control from microprocessor 7, and outputs, to video pre-amplifier 3, an on-screen blanking signal BLK and an OSD video signal including respective video components of red R, green G and blue B.
Here, on-screen display blanking signal BLK cause video pre-amplifier 3 to blank the RGB video signal such that an image displayed by OSD video signal is displayed clearly when the OSD video signal from OSD IC 9 and the RGB video signal from the external system are input to video preamplifier 3 simultaneously for display on a screen,
The DATA for picture control output by microprocessor 7 includes information for controlling horizontal position, vertical position, pin-cushion, vertical size, V-linearity, trap geoid and pin balance. This DATA is fed to H/V deflection circuit 11 along with the control clock signal CLK and is accompanied by the horizontal and vertical synchronizing signals HSYNC, VSYNC supplied from microprocessor 7.
H/V deflection circuit 11 supplies horizontal and vertical deflection signals to cathode ray tube 13 in response to the DATA, the control clock signal CLK and the horizontal and vertical synchronizing signals HSYNC, VSYNC supplied from microprocessor 7. The vertical and horizontal deflections signals are also supplied to OSD IC 9 via flyback buffer amplifiers 10 and 12, respectively, as vertical and horizontal flyback signals.
Referring now to
As a result, in dependence upon the instant state, either internal horizontal synchronizing signal IHSYNC or external horizontal synchronizing signal XHSYNC is selected via switch 31 for output as horizontal synchronizing signal HSYNC for input to H/V deflection circuit 11, while either internal vertical synchronizing signal IVSYNC or external vertical synchronizing signal XVSYNC is selected for output via switch 33 as vertical synchronizing signal VSYNC for input to H/V deflection circuit 11.
Additionally, microprocessor 7 includes a synchronizing counter block 29. The horizontal and vertical synchronizing signals HSYNC and VSYNC, selected by way of switches 31 and 33 as described above, are also supplied for input to synchronizing counter block 29. Synchronizing counter block 29 provides count information in dependence upon the frequencies of the horizontal and vertical synchronizing signals HSYNC and VSYNC.
The internal horizontal and vertical synchronizing signals IHSYNC and IVSYNC, respectively generated by horizontal and vertical synchronizing circuits 25 and 27, are set at predetermined frequency levels by, in part. frequency dividing a crystal oscillation frequency generated in oscillation device 23.
Referring again to
A grounding terminal port SYNC GND of cable connector 1, which is connected to an input port P1 of microprocessor 7 in
Alternatively, in determining above described state of connection, microprocessor 7 counts the frequency of external horizontal synchronizing signal XHSYNC. In this regard, a configuration of control block 21 in microprocessor 7 may well be constructed by way of a hardware configuration, especially by an application specific integrated circuit ASIC.
A variety of self-diagnosis display exhibits are shown displayed on the screens in
In of
Accordingly, the operational status of respective video component signals and circuits therefor as well as each the chromaticity thereof in a displayed screen including a state indicative of the integrity of a cathode ray tube, are provided as display information to a viewer.
In of
In
A preset procedure for effectuating the above embodiment of the present invention is discussed with regard to FIG. 4.
Alternatively, when it is determined that the cable connector 1 is not connected to a cable of the external system, microprocessor 7 controls, in step 4b, the set up and generation of the internal horizontal and vertical synchronizing signals IHSYNC and IVSYNC by horizontal and vertical synchronizing circuits 25 and 27 as discussed with regard to
Where, the oscillation clock frequency is provided by the oscillation device 23 and each value of x and y is user adjustable according to, for example, a key input so that desired frequencies can be obtained.
Upon completion of setting up internal horizontal and vertical synchronizing signals, IHSYNC and IVSYNC to respective desired frequencies and selection thereof by switches 31 and 33, then in step 4c, stored data for an initial self-diagnosis display, such as the color bars for video components as shown
Then, in step 4d, microprocessor 7 scans for a key input to detect a positive key input in order to display one of the self-diagnostic screen displays in
Consequently, a viewer is able to obtain information regarding the connection status between a signal cable and cable connector 1, by referring to a message, as exemplified in
As stated above, according to the self-diagnosis arrangement and method for a video display of the present invention, a viewer can easily check the status of a signal input to the display and self-diagnostic tests for video components, such as colors, as well as for the status of a display, such as a CRT, can be accomplished, without connecting cable connector to an external system, by displaying a variety of internally generated images.
In addition, according to the present invention an external device for synchronizing signal generation is not needed when setting up the video display during factory production due to the capability of self-generation or internal generation of horizontal and vertical synchronization signals. Further, a self-diagnosis test for the video display, such as a monitor, can be accomplished without connection to an external computer system due to the use of internally stored image information, thus effecting efficiency in use and in mass production.
While there have been illustrated and described what are considered to be embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the present invention. For example, the user could select a key input which causes the self-diagnostic routine to begin even when there is a connection between a cable and cable connector 1. Accordingly, the blanking signal BLK could enable the self-diagnostic display data, i.e., the OSD video signal, to be displayed on the entire screen or in a predetermined window portion as a picture-in-picture display. In addition, may modifications may be made to adapt a particular situation to the teaching of the present invention without departing from the central scope thereof. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed as the best mode contemplated for carrying out the present invention, but that the present invention includes all embodiments failing within the scope of the appended claims.
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