A dc to dc buck pulse width modulator converter circuit includes an input, a high side output and a low side output. A high side switch is electrically connected between a common output node and a voltage supply, and controls a flow of current therethrough dependent upon the high side output. A low side switch is electrically connected between the common output node and ground, and controls a flow of current therethrough dependent upon the low side output. A virtual ground amplifier includes a second input electrically connected to ground. A current feedback resistor is electrically connected intermediate the common output node and a first input of the virtual ground amplifier. A variable impedance component is electrically connected to an output of the virtual ground amplifier and to the first input of the virtual ground amplifier. The impedance of the variable impedance component is varied dependent upon the output of the virtual ground amplifier. A sample and hold circuit is electrically connected intermediate the input of the pulse width modulator converter circuit and the variable impedance component. The sample and hold circuit sources a virtual ground current through the variable impedance component, and samples the virtual ground current.
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0. 26. A method of sensing an output current in a power supply, the power supply comprising a dc to dc converter circuit having an input, a high side output and a low side output, the method comprising:
receiving a sensed current at a node, the sensed current representative of the output current when a low side circuit is in an on condition, the sensed current flowing into the node in a first direction;
sourcing a current into the node, the sourced current flowing into the node in a second direction, the second direction being opposite to the first direction, the sourced current also representative of the output current; and
sampling and holding a value of the sourced current.
0. 30. A method of controlling an output current in a power supply, the power supply comprising a converter circuit having an input, a high side output coupled to a high side switch and low side output coupled to a low side switch, the method comprising:
generating a sensed current that is representative of the load current;
directing the sensed current to a current sense node in a first direction;
sourcing a current into the current sense node, the sourced current flowing into the current sense node in a second direction, the second direction being opposite to the first direction, the sourced current being substantially equal to the sensed current and thereby canceling the sensed current at the current sense node;
sampling and holding a value of the sourced current; and
generating control signals for the high side and low side outputs based on the sourced current.
0. 19. A method for controlling a dc/DC converter having an output voltage and sourcing an output current to a load, the method comprising:
receiving a sensed current at a node, the sensed current representative of the output current when a low side circuit is in an on condition, the sensed current flowing into the node in a first direction;
sourcing a current into the node, the sourced current flowing into the node in a second direction, the second direction being opposite to the first direction, the sourced current also representative of the output current;
sampling and holding a value of the sourced current;
receiving a signal representative of the output voltage;
issuing an error signal dependent at least in part upon the signal representative of the output voltage, the sampled and held value of the sourced current and a first reference signal;
issuing a comparison signal, the comparison signal based at least in part upon the error signal and a second reference signal; and
issuing a control signal based at least in part upon the comparison signal, wherein the control signal selectively controls the dc/DC converter.
12. A method of sensing an output current in a power supply, said power supply comprising a dc to dc buck pulse width modulator converter circuit having an input, a high side output and a low side output, said method comprising the steps of:
electrically connecting a high side switch intermediate a common output node and a voltage supply, said high side switch configured for controlling a flow of current therethrough dependent at least in part upon said high side output;
a low side switch electrically connected intermediate said common output node and ground, said low side switch configured for controlling a flow of current therethrough dependent at least in part upon said low side output;
directing a sensed current to a virtual ground node, said sensed current comprising a known portion of the output current when said low side switch is in an on condition, said sensed current flowing into said virtual ground node in a first direction;
sourcing a virtual ground current into said virtual ground node, said virtual ground current flowing into said virtual ground node in a second direction, said second direction being opposite to said first direction, said virtual ground current being substantially equal to said sensed current and thereby canceling said sensed current at said virtual ground node; and
sampling and holding a value of said virtual ground current.
0. 1. A power supply, comprising:
a dc to dc buck pulse width modulator converter circuit having an input, a high side output and a low side output;
a high side switch electrically connected intermediate a common output node and a voltage supply, said high side switch configured for controlling a flow of current therethrough dependent at least in part upon said high side output;
a low side switch electrically connected intermediate said common output node and ground, said low side switch configured for controlling a flow of current therethrough dependent at least in part upon said low side output;
a virtual ground amplifier having a first input, a second input and an output, said second input electrically connected to ground potential;
a current feedback resistor electrically connected intermediate said common output node and said first input of said virtual ground amplifier;
a variable impedance component electrically connected to said output of said virtual ground amplifier and to said first input of said virtual ground amplifier, said variable impedance component configured to vary in impedance dependent at least in part upon said output of said virtual ground amplifier; and
a sample and hold circuit electrically connected intermediate said dc to dc buck pulse width modulator converter circuit and said variable impedance component, said sample and hold circuit configured to source a virtual ground current through said variable impedence component and to sample and hold said virtual ground current.
0. 2. The power supply of
0. 3. The power supply of
0. 4. The power supply of
0. 5. The power supply of
0. 6. The power supply of
0. 7. The power supply of
0. 8. The power supply of
0. 9. The power supply of
0. 10. The power supply of
0. 11. The power supply of
13. The method of
14. The method of
15. The method of
comparing said sampled and held value of said virtual ground current to a predetermined maximum limit; and
shutting down said power supply when said virtual ground current exceeds said predetermined maximum limit.
16. The method of
17. The method of
0. 18. A power supply, comprising:
A dc to dc buck pulse width modulator converter circuit having an input, a high side output and a low side output;
a high side switch electrically connected intermediate a common output node and a voltage supply, said high side switch configured for controlling a flow of current therethrough dependent at least in part upon said high side output;
a low side switch electrically connected to said common output node and to ground through a sense resistor, said low side switch configured for controlling a flow of current therethrough dependent at least in part upon said low side output;
a virtual ground amplifier having a first input, a second input and an output, said second input electrically connected to ground potential;
a current feedback resistor electrically connected intermediate said sense resistor and said first input of said virtual ground amplifier;
a variable impedance component electrically connected to said output of said virtual ground amplifier and to said first input of said virtual ground amplifier, said variable impedance component configured to vary in impedance dependent at least in part upon said output of said virtual ground amplifier; and
a sample and hold circuit electrically connected intermediate said dc to dc buck pulse width modulator converter circuit and said variable impedance component, said sample and hold circuit configured to source a virtual ground current through said variable impedance component and to sample and hold said virtual ground current.
0. 20. The method of
0. 21. The method of
0. 22. The method of
0. 23. The method of
0. 24. The method of
0. 25. The method of
0. 27. The method of
0. 28. The method of
0. 29. The method of
0. 31. The method of
0. 32. The method of
0. 33. The method of
0. 34. The method of
comparing the sampled and held value of the sourced current to a selected value; and
shutting down the power supply when the sourced current exceeds the selected value.
0. 35. The method of
0. 36. The method of
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This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/151,826, filed Sep. 1, 1999. Notice: More than one reissue application has been filed for the reissue of Pat. No. 6,246,220. The reissue applications are reissue application No. 10/044,506 (the parent reissue) and reissue application No. 10/282,753(the present, continuation reissue application). Both Reissue applications are reissues of the same U.S. Pat. No. 6,246,220.
This reissue Application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/151,826, filed Sep. 1, 1999.
A synchronous buck DC to DC converter typically employs a pair of switches arranged to connect one end of an inductor to either an input supply voltage or to ground. The second end of the inductor is attached to a load. It is well known to use field effect transistors (FET's) as these switches. Load current flows from the supply through the upper FET and the inductor while the FET is on, and from ground through the lower FET and the inductor while that FET is on.
It is desirable to sense the value of the load current to perform various functions such as, for example, to deliberately decrease the output voltage as load current increases (i.e., output voltage “droop”), to provide for current limiting or over-current trip to protect the load and the converter components, and in order to balance the output current being sourced by each channel in a multi-channel or multi-phase converter. The load current can be sensed through determining the DC resistor of the inductor and sensing the voltage drop across that DC resistance, or by sensing the voltage drop across an added series sense resistor. The load current can also be detected by sensing the voltage drop caused by the load current flowing through the upper FET switch. However, each of these methods has their disadvantages. Sensing the load current by using the DC resistance of the inductor requires adding an R-C filter across the inductor to remove the AC component of the current. Thus, additional components are required and extra cost incurred. Adding a series sense resistor also requires an extra component, increase cost, and reduces system efficiency. Furthermore, sensing the voltage drop across the drain-to-source resistance of the upper FET when it is conducting has often proven to be impractical, since the “on” time of that switch is typically very short.
Therefore, what is needed in the art is a DC/DC converter with improved current sensing. Furthermore, what is needed in the art is an apparatus and method which enables the sensing of load current in a DC/DC converter by sensing the voltage drop across the drain-to-source resistance of a switching FET.
Moreover, what is needed in the art is an apparatus and method which enables sensing and detection of overcurrent in a DC/DC converter.
The present invention provides a power supply with improved current sensing.
The invention comprises, in one form thereof, a DC to DC buck pulse width modulator converter circuit having an input, a high side output and a low side output. A high side switch is electrically connected between a common output node and a voltage supply, and controls a flow of current therethrough dependent upon the high side output. A low side switch is electrically connected between the common output node and ground, and controls a flow of current therethrough dependent upon the low side output. A virtual ground amplifier includes a second input electrically connected to ground. A current feedback resistor is electrically connected intermediate the common output node and a first input of the virtual ground amplifier. A variable impedance component is electrically connected to an output of the virtual ground amplifier and to the first input of the virtual ground amplifier. The impedance of the variable impedance component is varied dependent upon the output of the virtual ground amplifier. A sample and hold circuit is electrically connected intermediate the input of the pulse width modulator converter circuit and the variable impedance component. The sample and hold circuit sources a virtual ground current through the variable impedance component, and samples the virtual ground current.
An advantage of the DC/DC converter or the present invention is that it provides an improved method and apparatus to measure the voltage drop across the drain-to-source resistance of a FET having a very brief “on” time.
Another advantage of the DC/DC converter of the present invention is that the amount of droop in the output voltage in response to a change in load current is easily manipulated and scaled by selecting an appropriate value for the voltage feedback resistor.
Yet another advantage of the DC/DC converter of the present invention is that the sensitivity or magnitude of the current limiting or trip is easily manipulated or scaled by selecting an appropriate value for the voltage feedback resistor.
A still further advantage of the DC/DC converter of the present invention is that a broad range of load current and component values is accommodated by selecting an appropriate value for the current feedback resistor.
The above-mentioned and other features and advantages of this invention, and the manner of attaining them, will become apparent and be better understood by reference to the following description of embodiments of the invention in conjunction with the accompanying drawings, wherein:
Corresponding reference characters indicate corresponding parts throughout the several views. The exemplifications set out herein illustrate one preferred embodiment of the invention, in one form, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.
Referring now to the drawings, and particularly to
Virtual ground amplifier 34 has its inverting input 34a electrically connected to virtual ground circuit node 30 and its non-inverting input 34b connected to ground. Output 34c of virtual ground amplifier 34 is electrically connected to and drives the gate of FET 36. The source of FET 36 is electrically connected to virtual ground circuit node 30. The drain of FET 36 is electrically connected to sample and hold circuit 38. Thus, as will be apparent to one skilled in the art, virtual ground amplifier 34 and FET 36 are configured to continuously drive virtual ground circuit node 30 toward ground potential. With virtual ground circuit node 30 being continuously driven towards ground potential, the end of current feedback resistor 26 that is connected to circuit node 30 will be at ground potential and the end connected to common output node 16 will have a negative voltage. This negative voltage at the end of current feedback resistor 26 that is connected to common output node 16 will be equal to the product of output current IOUT and the on-state resistance that exists between the drain and source (RDSON) of low side FET 12. Current ISENSE flows through current feedback resistor 26 and has a magnitude determined by the ratio of RDSON of low side FET 12 to the value of current feedback resistor 26. Thus, ISENSE is the product of output current IOUT and the ratio of RDSON of low side FET 12 to current feedback resistor 26, and as such is representative of output current IOUT. Load current IL is the current flowing through inductor 24 and is substantially equal to output current IOUT minus ISENSE. Typically, since the ratio of RDSON to the value of current feedback resistor 26 is relatively small, ISENSE is substantially smaller than output current IOUT. Therefore, output current IOUT and load current IL will be of substantially similar magnitudes and thus ISENSE will also be representative of load current IL.
The value of current feedback resistor 26 is selected to provide a convenient value of current flow for the values of load current IL and/or the value of RDSON of low side FET 12. Thus, the sensitivity or magnitude of, for example, the voltage droop, current limiting or trip, and current balancing incorporated into DC/DC converter 10 is scaled by selecting the value of current feedback resistor 26 relative to the value of RDSON of low side FET 12. Furthermore, the voltage drop across RDSON of low side FET 12, which is usually negative, is accommodated in DC/DC converter 10 without the need for a negative voltage supply.
Referring now to
DC/DC converter 10 monitors the voltage VOUT across load 32 through voltage feedback resistor 44. Voltage feedback resistor 44 is connected at one end to load 32 and at the other end to inverting input 46a of error amplifier 46. VFB is the voltage across voltage feedback resistor 44. The non-inverting input 46b of error amplifier 46 is electrically connected to reference voltage supply 48, which provides a predetermined voltage that is substantially equal to the desired output voltage of DC/DC converter 10. Error amplifier 46 regulates the voltage of inverting input 46a to be substantially equal to the voltage from reference voltage supply 48. Since the voltage at inverting input 46a is substantially equal to the sum of VOUT and VFB, error amplifier 46 acts to regulate the sum of VOUT and VFB to be substantially equal to the voltage from reference voltage supply 48. Output 46c of error amplifier 46 is electrically connected to compensation circuit node 50. A feedback path between output 46c and inverting input 46a of error amplifier 46 includes compensation resistor 52 and compensation capacitor 54. More particularly, connected to compensation circuit node 50 is one end of compensation capacitor 54 which, in turn, is connected at its other end to compensation resistor 52. Compensation resistor 52, at the end thereof opposite to compensation capacitor 54, is connected to summing node 56. Compensation resistor 52 and capacitor 54 in the voltage feedback path provide system stability and control system response.
Sample signal 38a, which is issued by sample and hold circuit 38 and is representative of load current IL, is also connected to the inverting input of error amplifier 46. There is no other path for direct current at inverting input 46a of error amplifier 46 except through voltage feedback resistor 44. Thus, the voltage across voltage feedback resistor 44, i.e., VFB, is modified by signal 38a. As stated above, error amplifier 46 regulates the voltage at its inverting input 46a, which is equal to the sum of VOUT and VFB, to be substantially equal to the reference voltage supply 48. Thus, for example, as sampling signal 38a increases, VFB increases proportionally and error amplifier 46 reduces VOUT to maintain the voltage at inverting input 46a to be equal to reference voltage supply 48. Since sampling signal 38a is representative of load current IL, VOUT is in effect modulated in an inversely proportional manner relative to load current IL. Thus, as shown in
Inverting input 58a of comparator 58 is electrically connected to sawtooth generator 60, and receives therefrom a sawtooth waveform having predetermined characteristics. Output 58c of comparator 58 is electrically connected to set-rest (SR) latch 62. Output 62a of SR latch 62 is electrically connected to and buffered by driver 64 which, in turn, drives low side FET 12 and high side FET 14. DC/DC converter 10 is configured, for example, such that a high-level signal at output 62a of SR latch 62 turns low side FET 12 off and turns on high side FET 14. Sawtooth generator 60 receives sync pulse 66 from system control circuit 40. SR latch 62 also receives sync pulse 66.
Error amplifier 46 produces at output 46c a signal that is representative of the actual output voltage VOUT relative to, such as, for example, subtracted from or added to, the voltage of reference voltage supply 48, which represents the desired output voltage of DC/DC converter 10. For example, output 46c of error amplifier 46 produces a signal that is more negative, or increases in a negative direction, as VOUT increases above the voltage of reference voltage supply 48. Conversely, and as a further example, error amplifier 46 produces at output 46c a signal having a decreasingly negative magnitude (i.e., a more positive magnitude) as VOUT decreases below the voltage of reference voltage supply 48. Output 46c of error amplifier 46 is electrically connected to the non-inverting input of comparator 58. Comparator 58 compares the sawtooth waveform electrically connected to its inverting input 58a with output 46c of error amplifier 46 which is electrically connected to its noninverting input 58b. Output 58c of comparator 58 is active, such as, for example, high during the time that the sawtooth waveform generated by sawtooth generator 60 is less positive than output 46c of error amplifier 46.
Referring to
Conversely, and with particular reference to
When output 58c is active, output 62a of SR latch 62 is set, such as, for example, high. Conversely, when output 58c is not active, output 62a of SR latch 62 is reset, such as, for example, low. Thus, when the sawtooth waveform is more positive than the voltage level of reference voltage supply 48, output 62a of SR latch 62 is reset, i.e., low. Output 62a of SR latch 62 is set, i.e., high, when the sawtooth waveform drops below the predetermined voltage. Output 62a of SR latch 62 is electrically connected to and buffered by driver 64 which, in turn, drives low side FET 12 and high side FET 14. DC/DC converter 10 is configured such that, for example, a high or set condition on output 62a of SR latch 62 results in driver 64 turning off low side FET 12 and turning on high side FET 14.
Current tripping or over current protection is provided by overcurrent detection circuit 70. Overcurrent detection circuit 70 compares the sample signal 38a to a reference current (not shown) and issues overnight signal 70a to system control circuit 40 when sample signal 38a exceeds the reference current. System control 40 responds to overcurrent signal 70a by shutting down DC/DC converter 10. System control 40 is configured, for example, to restart the operation of DC/DC converter 10 after a predetermined amount of time.
Negative current source 72 is electrically connected intermediate system control 40 and virtual ground circuit node 30. Load current IL becomes negative under certain operating conditions, such as, for example, when load current IL has a low average value and the sawtooth waveform created due to the switching of voltage across inductor 24 dips to a negative value. During such operating conditions, i.e., when IL is negative, the voltage at the drain of low side FET 12 is positive. The positive voltage on the drain of low side FET 12 results in the sourcing of current through resistor 26 and into virtual ground circuit node 30, thereby driving virtual ground circuit node 30 to a positive potential. Negative current source 72 sources IPULL DOWN into virtual ground circuit node 30 in response to signal 40N, and thereby maintains virtual ground node 30 at ground potential under the conditions when IL is negative. Thus, virtual ground amplifier 46, variable impedance component 36 and sample and hold circuit 38 are not required to operate in a bi-directional manner (i.e., they source current is one direction only) and the need to include a negative voltage supply in DC/DC converter 10 is eliminated.
As best shown in
In use, and with continued reference to
Referring now particularly to
At point 310a, the trailing, or negatively sloped, edge of the sawtooth waveform crosses below the output level of output 46c of error amplifier 46, thereby sending output 58c of comparator 58 high. This transition in output 58c to a high level, in turn, sets output 62a of SR latch 62 high thereby turning high side FET 14 on and turning off low side FET 12. The high level of output 46c relative to the sawtooth waveform results in the sawtooth waveform dropping below the level of output 46c (at point 310a) relatively early in the period of the sawtooth waveform. Thus, points 300a and 310a are relatively close in time, and, therefore, the period of time during which low side FET 12 is off is corresponding brief. Conversely, the period of time during which high side FET 14 is on and sourcing current is relatively long. Thus, high side FET 14 is on for a relatively long period of time and sources a greater amount of current to load 32 when VOUT is less than the desired output voltage.
Referring now
At point 310b, the trailing, or negatively sloped, edge of the sawtooth waveform crosses below the output level of output 46c of error amplifier 46, thereby sending output 58c of comparator 58 high. This transition in output 58c to a high level, in turn, sets output 62a of SR latch 62 high thereby turning high side FET 14 on and turning off low side FET 12. The low level of output 46c relative to the sawtooth waveform results in the sawtooth waveform dropping below the level of output 46c (at point 310b) relatively late in the period of the sawtooth waveform. Thus, points 300a and 310a are separated by a substantially greater amount of time relative to the situation illustrated in
In both cases, i.e., whether the voltage across load 32 is higher or lower than desired, output 62a of SR latch 62 goes low based upon sync pulse 66 rather than dependent upon the relative value of the voltage across load 32. Output 62a of SR latch 62 remains low at least during the duration of sync pulse 66. When output 62a of SR latch 62 is in the low state, high side FET 14 is in the off condition and low side FET 12 is in the on condition, and the voltage drop across RDSON of low side FET 12 is sampled and held. However, when low side FET 12 is in the on condition the direction of load current IL is toward load 32. Thus, load current IL flows from ground through the source to the drain of low side FET 12 when low side FET 12 is in the on condition. This direction of current flow through low side FET 12 develops a negative voltage on the drain of low side FET 12. The magnitude of this negative voltage is the product of IL and the RDSON of low side FET 12.
In the embodiment shown, the source of low side FET 12 is electrically connected to ground. However, it is to be understood that low side FET 12 can be alternately configured such as, for example, having its source tied through a resistor to ground, and electrically connecting sensing resistor 26 to the source of low side FET 12. The net effect is the same, and the virtual ground amplifier continues to drive virtual ground node 30 to virtual ground. In this alternative configuration, current from Sample and Hold circuit 38 is still representative of load current IL except the load-current-induced voltage drop across the added sense resistor is measured rather than the voltage drop across RDSON of low side FET 12. This alternative embodiment is best shown in FIG. 6.
In the embodiment shown, reference voltage supply 48 is described as a fixed voltage supply. However, it is to be understood that reference voltage supply 48 can be alternatively configured, such as, for example, as a bandgap or other fixed voltage source, or may be configured as a Digital to Analog converter or other variable voltage source.
In the embodiment shown, FET 36 is configured as an FET. However, it is to be understood that FET 36 can be alternately configured, such as, for example, an NPN transistor, with Base substituted for Gate, Emitter for Source, and Collector of Drain.
In the embodiment shown, virtual ground amplifier 34 is configured for continuous operation. However, it is to be understood that virtual ground amplifier 34 can be alternately configured, such as, for example, an auto-zeroed amplifier or other non-continuously operating amplifier, as it is needed only when low side FET 12 is in the on state.
In the embodiment shown, DC/DC converter 10 is configured such that a high-level signal at output 62a of SR latch 62 turns low side FET 12 off and turns on high side FET 14. However, it is to be understood that DC/DC converter 10 can be alternately configured such that the operational polarity of FET 12 and FET 14 is reversed.
In the embodiment shown, system control circuit 40 is configured to restart the operation of DC/DC converter 10 after a predetermined amount of time following the detection of an overcurrent condition. However, it is to be understood that system control circuit 40 may be alternately configured, such as, for example, to issue a visual or audible warning signal or to completely shut down DC/DC converter 10.
In the embodiment shown, DC/DC converter 10 is configured with indicator 24, load capacitor 28 and load 32 connected to node 16. However, it is to be understood that DC/DC converter 10 can be alternately configured, such as, for example, without interface 24, load capacitor 28 and load 32 such that a user, designer, or manufacturer can choose and customize circuitry attached to node 16 of DC/DC converter 10.
While this invention has been described as having a preferred design, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the present invention using the general principles disclosed herein. Further, this application is intended to cover such departures from the present disclosure as come within the known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.
Isham, Robert H., Hawkes, Charles E., Walters, Michael M.
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