The invention provides a method for producing semiconductor packages comprising the steps of forming electronic circuits for a plurality of semiconductor chips 11 on a wafer 1, forming bumps 2 on the plurality of semiconductor chips 11, encapsulating the circuit-forming surface 111 of the wafer 1 and the bumps 2 with a sealant by screen printing means to form a sealant layer 4, curing the sealant layer 4, grinding the surface of the sealant layer 4 until the upper end surface of the bump 2 becomes exposed, placing solder balls on said upper end surface of bumps 2 to weld the balls to the surface thereof, and dicing the wafer 1 and the sealant layer 4 as united into individual semiconductor chips 11. Screen printing means is used to encapsulate the entire surface of the wafer with a resin, so that the equipment costs can be markedly reduced as compared with conventional methods using a mold.
|
0. 19. A method comprising:
forming electronic circuits for a plurality of semiconductor chips on a surface of a semiconductor wafer;
forming substantially columnar shaped bumps on the surface of the semiconductor wafer by a plating method, each bump having an upper end and a height;
screen-printing the surface of the semiconductor wafer with a resin sealant including silica in an amount of 60-95% of the resin sealant by weight to encapsulate the bumps, including the upper ends of the bumps, and the electronic circuits formed on the surface of the semiconductor wafer with the resin sealant, thereby forming a sealant layer;
curing the sealant layer;
grinding the cured sealant layer downward until the upper ends of the bumps become exposed; and
dicing the semiconductor wafer and the sealant layer as an integrated unit into individual semiconductor chips.
1. A method for producing semiconductor packages, comprising the steps of :
forming electronic circuits for a plurality of semiconductor chips on a surface of a semiconductor wafer;
forming substantially columnar shaped bumps on circuit-provided the surface of the semiconductor wafer in accordance with the electronic circuits by a plating method, each bump having an upper end and a height;
screen-printing the bump-provided surface of the semiconductor wafer with a resin sealant to encapsulate the bumps, including their the upper ends of the bumps, and the remaining circuit-provided electronic circuits formed on the surface of the semiconductor wafer with the resin sealant, by placing a metal mask having a single through-hole and a thickness which is larger than the height of each bump over the surface of the semiconductor wafer, thereby forming a sealant layer;
curing the sealant layer;
grinding the cured sealant layer downward until the upper ends of the bumps become exposed; and
placing solder balls on the exposed upper ends of the bumps to weld the balls thereto; and
dicing the semiconductor wafer and the sealant layer as an integrated unit into individual semiconductor chips.
2. The method according to
placing a mask having through-holes on the bump-provided surface of the wafer;
feeding the resin sealant onto the placed mask; and
squeegeeing the resin sealant onto the bump-provided surface of the semiconductor wafer through the through-holes single through-hole of the mask by sliding a squeegee along the mask with a reciprocative movement.
3. The method according to
0. 5. The method according to
0. 6. The method according to
0. 7. The method according to
0. 8. The method according to
0. 9. The method according to
0. 10. The method according to
0. 11. The method according to
0. 12. The method according to
0. 13. The method according to
0. 14. The method according to
0. 15. The method according to
0. 16. The method according to
0. 17. The method according to
0. 18. The method according to
0. 20. The method according to
|
The present invention relates to a method for producing a chip-size semiconductor package.
In view of recent development of electronic equipment such as portable telephones, notebook-size personal computers, electronic personal data books, etc., there are demands for production of semiconductor packages of higher density, smaller size and reduced thickness which are useful for such electronic equipment.
To meet said demands, various kinds of semiconductor packages have been developed. Examples are LSI-mounting TAB, tape carriers, plastic leaded chip carriers (PLCC), ball grid arrays (BGA), chip-size packages (CSP), flip chips, etc. These semiconductor packages have excellent features but are defective in production efficiency and mounting reliability.
Methods have been proposed for producing chip-size semiconductor packages among said semiconductor packages in an attempt to improve the production efficiency and the mounting reliability (of. Japanese Unexamined Patent Publication No. 79362/1998). According to the proposed methods, electronic circuits for a plurality of semiconductor chips are formed on a wafer and bumps are provided on the semiconductor chips. Then, after the wafer is placed into a mold cavity, a resin is supplied to the space around the bumps to encapsulate the bumps by the so-called transfer molding. Thereafter at least the tips of bumps covered with the resin layer are exposed at the surface of the resin layer. Finally the wafer with the resin layer formed thereon is cut into individual semiconductor chips to obtain semiconductor packages.
According to the foregoing conventional methods for producing semiconductor packages, a resin layer is formed on the bump-arranged surface of the wafer before mounting the semiconductor packages on the printed circuit board. Consequently the methods eliminate the need for the step of filling an encapsulation resin into a narrow space between the semiconductor chips and the printed circuit board after mounting the semiconductor chips on the board so that the mounting reliability is improved. Because of the encapsulation of the wafer with a resin, the methods can achieve a higher production efficiency than the encapsulation of individual semiconductor packages with a resin.
However, the conventional methods pose the following problems due to the use of ai a mold. First of all, high investment in equipment is essentially needed. Further, since the encapsulating step and heat-curing step are conducted in this order within the mold, the wafer is confined in the mold for a prolonged period of time, thereby lowering the production efficiency. Moreover, it is difficult to form a resin layer having a thickness of 1 mm or less.
The present invention was accomplished to overcome the above-mentioned prior art problems. An object of the invention is to provide a method for producing semiconductor packages, the method being capable of lowering the equipment investment, increasing the production efficiency and forming a resin layer with a thickness of 1 mm or less.
Other features of the invention will become apparent from the following description.
According to the invention, there is provided a method for producing semiconductor package, the method comprising the steps of:
This invention will be further clarified by the description of two embodiments with reference to the accompanying drawings. The invention, however, is not limited to the embodiments, but various modifications are possible without deviation from the scope of the invention.
First, the structure of a semiconductor package 10 is described below with reference to FIG. 1. The semiconductor package 10 comprises a semiconductor chip 11, bumps 2 serving as electrodes, a sealant layer 4 having substantially the same height as the bumps 2 and solder balls 3 welded to the upper end surface of bumps. Namely the semiconductor package 10 has a very simple structure.
The semiconductor package 10 with said structure is substantially equal in size to the semiconductor chip 11, and is of the so-called chip-size package structure. Because of this structure, the semiconductor package produced by the method of the invention can satisfactorily fulfil the need for the miniaturized semiconductor packages as required in recent years.
The method for producing the semiconductor package 10 is described below with reference to
In the step of forming electronic circuits in
After practicing the step of forming the electronic circuits, the wafer 1 is subjected to the step of forming bumps. In the step of forming bumps, pillar-shaped bumps 2 with the specified height are provided on the wafer surface 111 provided with the circuit as shown in FIG. 4. The bumps 2 are formed by the bump-forming technique conventionally used for flip chips or the like, such as the plating method.
After practicing the step of forming bumps, the wafer 1 is subjected to the step of printing encapsulation. In the printing encapsulation step, a viscous fluid sealant 40 is forcedly filled by screen printing to form on the entire circuit-forming surface of the wafer 1 a sealant layer 4 having a thickness of height higher than the bumps 2 as shown in FIG. 5. Stated more specifically, after a metal mask 6 and the wafer 1 are properly positioned, a specific amount of sealant 40 is fed onto the specified part of the metal mask 6 and forcedly filled into a through-hole 6a of the metal mask 6 by the reciprocative movement of a squeegee 5. After filling, the metal mask 6 is released from the sealant layer 4. The diameter of the through-hole 6a is substantially equal to or smaller by about 1 to about 10 mm than that of the wafer. Preferred sealing materials useful as the sealant 40 are viscous fluids which are excellent in adhesion to the wafer 1, and have low shrinkage in curing, low residual stress after curing, low expansion coefficient, low water absorption and high heat resistance. An epoxy resin composition having such properties is suitable as the sealant 40. Specific examples include a composition containing an epoxy resin and silica in an amount of 60 to 95% by weight based on the composition, such as NPR-780 and NPR-785 (trademarks, products of Japan Rec Co., Ltd.). It may occur that the air is included into the sealant 40 when the sealant 40 is forcedly filled into the through-hole 6a of the metal mask 6. The inclusion of air can be effectively prevented by encapsulation with screen printing means under a vacuum atmosphere preferably in the same vacuum degree between during the forward movement of the squeegee and during the backward movement thereof. Alternatively the vacuum degree may be varied between during the forward movement of the squeegee and during the backward movement thereof (e.g. under 10 Torr or less in the forward movement and under 50 to 150 Torr in the backward movement). In the method of the invention, printing means is used for encapsulation, so that the sealant layer can be thinned to a minimum thickness of about 50 μm. When required, a thick layer up to about 2 mm in thickness can be formed.
After practicing the step of printing encapsulation, the wafer 1 is subjected to the step of curing the sealant layer. In the step of curing the sealant layer, the wafer 1 with the sealant layer is placed into a known heating furnace to cure the sealant layer as shown in FIG. 6.
After practicing the step of curing the sealant layer, the wafer 1 is subjected to the step of exposing the bumps. In the step of exposing the bumps, the surface of the sealant layer 4 is ground with a grinder 7 as shown in
After practicing the step of exposing the bumps, the wafer 1 is subjected to the step of welding solder balls. In the step of welding solder balls, solder balls 3 for bonding to the printed circuit board are placed onto the exposed upper end surface of the bumps and welded thereto by the conventional ball mounter as shown in FIG. 8. The solder balls 3 can be welded to the bumps by the conventional bump-forming technique such as a transfer method.
Finally after executing the step of welding solder balls, the wafer 1 is subjected to the dicing step. In the dicing step, the wafer 1 and the sealant layer 4 as united are diced by a known dicer 8 into individual chips 11, whereby numerous chip-size semiconductor packages 10 are obtained.
A second embodiment of the invention will be described below.
First, the semiconductor package 100 according to the second embodiment is described with reference to FIG. 10. The semiconductor package 100 comprises a semiconductor chip 11, bumps 2, a sealant layer 400 and solder balls 3 which are provided in the semiconductor package 10 of the first embodiment. However, unlike the semiconductor package 10, the upper surface of the sealant layer 400 does not evenly extend and covers the bumps 2 in such a manner that the bump 2 is individually surrounded with a slope as shown in FIG. 10. With this structure, the semiconductor package 100 is such that the bumps 2 are reinforced by the sealant layer 400 and the circuit-forming surface 111 of the chip 11 is covered and protected with the sealant layer 400. Consequently the semiconductor package 100 is equal in mounting reliability to the semiconductor package 10 of the first embodiment shown in FIG. 1.
The method for producing the semiconductor package 100 is described below. In the method for producing the semiconductor package 100, the steps of forming electronic circuits and forming bumps as shown in
After practicing the step of printing encapsulation, the wafer 1 is subject(ed to the step of curing the sealant layer. In the step of curing the sealant layer, the printed wafer 1 is placed into a heating furnace to cure the sealant layer indented between the pairs of bumps as shown in FIG. 12.
After practicing the step of curing the sealant layer, the wafer 1 is subjected to the step of exposing the bumps. In the step of exposing the bumps, the surface of the sealant layer 400 is ground with the grinder 7 as shown in
After practicing the step of exposing the bumps, a plurality of semiconductor packages 100 are obtained following the step of welding solder balls and the dicing steps. The step of welding solder balls and the dicing steps can be carried out in the same manner as in the first embodiment. Thus the description of these steps is omitted.
According to the producing method of the invention, screen printing means is used to encapsulate the entire surface of the wafer with a resin, so that the equipment costs can be markedly reduced as compared with conventional methods using a mold. Since the formation of sealant layer and the heat-curing are separately done, the production operation can be continuously performed without necessity of confining the wafer to a step for a prolonged period of time. Moreover, the sealant layer can be thinned to a minimum thickness of about 50 μm.
Okuno, Atsushi, Ishikawa, Yuki, Fujita, Noriko, Nagai, Koichiro, Oyama, Noritaka, Hashimoto, Tsunekazu
Patent | Priority | Assignee | Title |
7189599, | May 30 2001 | Renesas Electronics Corporation | Lead frame, semiconductor device using the same and method of producing the semiconductor device |
7719096, | Aug 11 2006 | Vishay General Semiconductor LLC | Semiconductor device and method for manufacturing a semiconductor device |
8604568, | Nov 28 2011 | QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD | Multi-chip package |
8962470, | Dec 27 2002 | Fujitsu Limited | Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus |
9960105, | Sep 29 2012 | Intel Corporation | Controlled solder height packages and assembly processes |
Patent | Priority | Assignee | Title |
3644180, | |||
4600600, | Nov 30 1983 | Siemens Aktiengesellschaft | Method for the galvanic manufacture of metallic bump-like lead contacts |
5232651, | Dec 11 1989 | SANYU REC CO , LTD | Method of sealing electric parts mounted on electric wiring board with resin composition |
5318651, | Nov 27 1991 | NEC Corporation; Tokyo Ohka Kogyo Co., Ltd. | Method of bonding circuit boards |
5620927, | May 25 1995 | National Semiconductor Corporation | Solder ball attachment machine for semiconductor packages |
5641113, | Jun 30 1994 | LAPIS SEMICONDUCTOR CO , LTD | Method for fabricating an electronic device having solder joints |
5786271, | Jul 05 1995 | Kabushiki Kaisha Toshiba | Production of semiconductor package having semiconductor chip mounted with its face down on substrate with protruded electrodes therebetween and semiconductor package |
5789279, | Sep 20 1994 | SGS-Thomson Microelectronics S.r.l. | Method and apparatus for electrically insulating heat sinks in electronic power devices |
5837427, | Apr 30 1996 | Samsung Electro-Mechanics Co Co., Ltd. | Method for manufacturing build-up multi-layer printed circuit board |
5849608, | May 30 1996 | NEC Electronics Corporation | Semiconductor chip package |
5851845, | Dec 18 1995 | Micron Technology, Inc. | Process for packaging a semiconductor die using dicing and testing |
5907786, | Nov 11 1992 | Renesas Electronics Corporation | Process for manufacturing a flip-chip integrated circuit |
5977641, | May 14 1997 | TOSHIBA MEMORY CORPORATION | Semiconductor device and method for manufacturing the same |
5989982, | Oct 08 1997 | OKI SEMICONDUCTOR CO , LTD | Semiconductor device and method of manufacturing the same |
6103552, | Aug 10 1998 | Qualcomm Incorporated | Wafer scale packaging scheme |
6194250, | Sep 14 1998 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Low-profile microelectronic package |
6232563, | Nov 25 1995 | LG DISPLAY CO , LTD | Bump electrode and method for fabricating the same |
6260264, | Dec 08 1997 | 3M Innovative Properties Company | Methods for making z-axis electrical connections |
6423102, | Nov 30 1994 | Sharp Kabushiki Kaisha | Jig used for assembling semiconductor devices |
DE19754372, | |||
EP729182, | |||
JP10079362, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
May 16 2002 | Casio Computer Co., Ltd. | (assignment on the face of the patent) | / | |||
May 16 2002 | Sanyu Rec Co., Ltd. | (assignment on the face of the patent) | / | |||
Dec 12 2011 | CASIO COMPUTER CO , LTD | TERAMIKROS, INC | CHANGE OF OWNERSHIP BY CORPORATE SEPARATION | 027465 | /0812 | |
Dec 12 2011 | CASIO COMPUTER CO , LTD | TERAMIKROS, INC | CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE S ADDRESS ON REEL 027465, FRAME 0812 | 027492 | /0449 | |
Oct 01 2013 | TERAMIKROS, INC | TERA PROBE, INC | MERGER SEE DOCUMENT FOR DETAILS | 040772 | /0440 | |
Jan 24 2017 | TERA PROBE, INC | AOI ELECTRONICS CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 041169 | /0952 |
Date | Maintenance Fee Events |
Apr 14 2005 | ASPN: Payor Number Assigned. |
Sep 24 2007 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Oct 19 2011 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Jan 31 2009 | 4 years fee payment window open |
Jul 31 2009 | 6 months grace period start (w surcharge) |
Jan 31 2010 | patent expiry (for year 4) |
Jan 31 2012 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jan 31 2013 | 8 years fee payment window open |
Jul 31 2013 | 6 months grace period start (w surcharge) |
Jan 31 2014 | patent expiry (for year 8) |
Jan 31 2016 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jan 31 2017 | 12 years fee payment window open |
Jul 31 2017 | 6 months grace period start (w surcharge) |
Jan 31 2018 | patent expiry (for year 12) |
Jan 31 2020 | 2 years to revive unintentionally abandoned end. (for year 12) |