A content addressable memory (cam) cell that includes a static random access memory (sram) cell that operates in response to a VCC supply voltage. A first set of bit lines coupled to the sram cell are used to transfer data values to and from the sram cell. The signals transmitted on the first set of bit lines have a signal swing equal to the VCC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the VCC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the VCC supply voltage. A sensor circuit is provided for comparing the data value stored in the cam cell with the comparison data value. The sensor circuit pre-charges a match scan line prior to a compare operation. If the data value stored in the cam cell does not match the comparison data value, the match sense line is pulled down. The signal swing of the match sense line is smaller than the VCC supply voltage. For example, the signal swing on the match sense line can be as low as one transistor threshold voltage.
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20. A content addressable memory (cam) cell having a match line that carries a signal to indicate whether a match or a no-match condition exists within the cam cell, wherein the difference between a voltage on the match line during the match condition and a voltage on the the match line during the no-match condition in equal to one transistor threshold voltage.
0. 68. A cam cell, comprising:
a memory cell electrically coupled to a pair of read/write bit lines; and
a data comparison circuit electrically coupled to a pair of comparison bit lines, a match line and said memory cell, said data comparison circuit configured to indicate a mismatch between data stored in said memory cell and data applied to the pair of comparison bit lines during a comparison operation, by sinking current from the match line to at least one of the pair of comparison bit lines.
0. 56. A cam cell, comprising:
a memory cell electrically coupled to a pair of read/write bit lines; and
a data comparison circuit electrically coupled to a pair of comparison bit lines, a match line and said memory cell, said data comparison circuit configured to indicate a mismatch between data stored in said memory cell and data applied to the pair of comparison bit lines during a comparison operation, by transferring charge between the match line and at least one of the pair of comparison bit lines.
0. 55. A cam array, comprising:
a cam cell having a memory cell therein that is powered at a supply voltage;
a pair of read/write bit lines electrically coupled to said cam cell;
a pair of comparison data lines electrically coupled to said cam cell; and
a bit line control circuit electrically coupled to said pair of read/write bit lines and said pair of comparison bit lines, said bit line control circuit configured to support a signal swing on said pair of comparison bit lines that is less than a signal swing on said pair of read/write bit lines.
1. A content addressable memory (cam) cell comprising:
a static random access memory (sram) cell that operates in response to a VCC supply voltage, the sram cell storing a data value;
a first set of one or more bit lines coupled to the sram cell, wherein the data value is written to and read from the sram cell on the first set bit lines, the first set of bit lines having a signal swing equal to the VCC supply voltage; and
a second set of bit lines coupled to receive a comparison data value, the second set of bit lines having a signal swing less than the VCC supply voltage.
21. A method of operating a content addressable memory (cam) cell that includes a static random access (sram) cell, the method comprising:
operating the sram cell in response to a VCC supply voltage, the sram cell storing a data value;
writing a data value to the sram cell on a first set of one or more bit lines, the first set of bit lines having a signal swing equal to the VCC supply voltage;
reading data values from the sram cell on the first set of bit lines;
controlling the signal swing on the first set of bit lines to be equal to the VCC supply voltage;
providing comparison data values to the cam cell on a second set of bit lines; and
controlling the signal swing on the second set of bit lines to be less than the VCC supply voltage.
0. 33. A method of operating a content addressable memory (cam) array, comprising the steps of:
precharging first and second match sense lines that are electrically coupled to compare circuitry within a row of cam cells to first and second positive voltage levels, respectively, said second voltage level having a maximum value that is less than Vcc, where Vcc is a power supply voltage supplied to the row of cam cells;
applying a plurality of comparison data values to a plurality of comparison data lines that are electrically coupled to the row of cam cells; and
detecting a match/no-match condition between the applied comparison data values and data stored in the row of cam cells by sensing a voltage on the first match sense line in-sync with discharging the second match sense line from its precharged second positive voltage level.
0. 48. A method of operating a content addressable memory (cam) cell, comprising the steps of:
precharging first and second match sense lines that are electrically coupled to a compare circuit within the cam cell to first and second positive voltage levels, respectively, said second positive voltage level having a maximum value that is less than Vcc, where Vcc is a power supply voltage supplied to the cam cell;
applying a comparison data value to a pair of comparison data lines that are electrically coupled to the cam cell; and
comparing the applied comparison data value with a data value stored in the cam cell by discharging the second match sense line from its precharged second positive voltage level to a discharged voltage level and then sensing whether the first match sense line is maintained at its precharged first positive voltage level or is pulled down to the discharged voltage level by the compare circuit.
0. 36. A content addressable memory (cam) array, comprising the steps of:
a plurality of pairs of comparison data lines;
a row of cam cells having compare circuitry therein that is electrically coupled to said plurality of pairs of comparison data lines;
first and second match sense lines that are electrically coupled to the compare circuitry in said row of cam cells; and
a sensor circuit that is configured to disable the compare circuitry from indicating a match/no-match condition on the first match sense line by precharging the first and second match sense lines to first and second positive voltage levels, respectively, and is further configured to enable the compare circuitry to indicate a match/no-match condition on the first match sense line by discharging the second match sense line from its precharged second positive voltage level, said second positive voltage level having a maximum value that is less than Vcc by at least a transistor threshold voltage, where Vcc is a power supply voltage supplied to said row of cam cells.
0. 61. A cam array, comprising:
a first cam cell comprising a first memory cell electrically coupled to a first pair of read/write bit lines, and a first data comparison circuit electrically coupled to a first pair of comparison bit lines, a match line and said first memory cell, said first data comparison circuit configured to indicate a mismatch between data stored in said first memory cell and data applied to the first pair of comparison bit lines during a comparison operation, by transferring charge between the match line and at least one of the first pair of comparison bit lines; and
a second cam cell comprising a second memory cell electrically coupled to a second pair of read/write bit lines, and a second data comparison circuit electrically coupled to a second pair of comparison bit lines, the match line and said second memory cell, said second data comparison circuit configured to indicate a mismatch between data stored in said second memory cell and data applied to the second pair of comparison bit lines during the comparison operation, by transferring charge between the match line and at least one of the second pair of comparison bit lines.
2. The cam cell of
3. The cam cell of
a first transistor having a gate coupled to receive a signal representative of the data value;
and
a second transistor having a gate coupled to receive a signal representative of the inverse of the data value.
4. The cam cell of
a first bit line coupled to a source region of the first transistor; and
a second bit line coupled to a source region of the second transistor.
5. The cam cell of
7. The cam cell of
10. The cam cell of
11. The cam cell of
12. The cam cell of
13. The cam cell of
14. The cam cell of
15. The cam cell of
16. The cam cell of
17. The cam cell of
18. The cam cell of
19. The cam cell of
22. The method of
23. The method of
24. The method of
25. The method of
26. The method of
27. The method of
28. The method of
29. The method of
30. The method of
31. The method of
32. The method of
0. 34. The method of
0. 35. The method of
0. 37. The cam array of
0. 38. The cam array of
0. 39. The cam array of
0. 40. The cam array of
0. 41. The cam array of
0. 42. The cam array of
0. 43. The cam array of
0. 44. The cam array of
0. 45. The cam array of
0. 46. The cam array of
0. 47. The cam array of
0. 49. The method of
0. 50. The method of
0. 51. The method of
0. 52. The method of
0. 53. The cam array of
a plurality of pairs of read/write bit lines that are electrically coupled to the cam cells in said row of cam cells; and
a bit line control circuit electrically coupled to said plurality of pairs of comparison data lines and said plurality of pairs of read/write bit lines, said bit line control circuit configured to support signal swings on said plurality of pairs of comparison data lines that are less than signal swings on said plurality of pairs of read/write bit lines.
0. 54. The cam array of
0. 57. The cam cell of
0. 58. The cam cell of
0. 59. The cam cell of
0. 60. The cam cell of
0. 62. The cam array of
0. 63. The cam array of
0. 64. The cam array of
0. 65. The cam array of
0. 66. The cam array of
0. 67. The cam array of
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This application is a divisional of U.S. application Ser. No. 10/246,586, filed Sep. 18, 2002, now abandoned, which is a reissue of U.S. application Ser. No. 09/185,057, filed Nov. 2, 1998, now U.S. Pat. No. 6,128,207.
1. Field of the Invention
The present invention relates to content addressable memory (CAM) cells. More specifically, the present invention relates to nine transistor CAM cells and methods for operating these cells in an array.
2. Discussion of Related Art
CAM cells are defined as memory cells that are addressed in response to their content, rather than by a physical address within an array.
The array of CAM cells is addressed by providing a data value to each column of CAM cells. Thus data values D0, D1, D2 and D3 are provided to columns 0, 1, 2 and 3, respectively. Note that complementary data values D0#, D1#, D2# and D3# are also provided to columns 0, 1, 2 and 3, respectively. If the data values stored in a row of the CAM cells match the applied data values D0-D3, then a match condition occurs. For example, if the data values D0, D1, D2 and D3 are 0, 1, 0 and 0, respectively, then the data values stored in the CAM cells of row 0 match the applied data values. Under these conditions, the MATCHo signal is asserted high. Because the applied data values D0, D1, D2 and D3 do not match the data values store in the CAM cells of rows 1 or 2, the MATCH1 and MATCH2 signals are de-asserted low. The match signals Match0-MATCH2 can be used for various purposes, such as implementing virtual addressing, in a manner (known to those skilled in the art.
Many different types of CAM cells have been designed. Important considerations in the design of a CAM cell include: the number of transistors required to implement the cell, the power required to operate the CAM cell, and the speed of the CAM cell. In general, it is desirable to have a CAM cell that is implemented using a relatively small number of transistors, such that the layout area of the CAM cell is minimized. It is also desirable for the CAM cell to have a low power requirement and a fast operating speed.
SRAM cell 12 is written like a conventional SRAM cell. That is, a logic high value is applied to word line 28, and data values D and D# are applied to bit lines 24 and 26, respectively. As a result, the data values D and D# are latched by inverters 16 and 18, such that the data value D is provided as the output of inverter 18, and the inverted data value D# is provided at the output of inverter 16.
XOR gate 14 includes n-channel transistors 30 and 32, which are connected in series between bit lines 24 and 26. The output terminal of inverter 16 is connected to the gate of transistor 30, such that the inverted data value D# stored in SRAM cell 12 is provided to the gate of transistor 30. Similarly, the output terminal of inverter 18 is connected to the gate of transistor 32, such that the data value D stored in SRAM cell 12 is provided to the gate of transistor 30. Transistors 30 and 32 are commonly connected at node 34, which forms the output terminal of XOR gate 14. Node 34 is connected to the gate of n-channel transistor 38. Transistor 38 has a source coupled to ground line 42, and a drain coupled to match line 40.
CAM cell 10 performs a compare operation as follows. Driver circuitry 36 applies a comparison data value (C) and its complement (C#) to bit lines 24 and 26, respectively. If the comparison data value C matches the data value D stored in SRAM cell 12, then node 34 is connected to receive a logic “0” signal. As a result, transistor 38 is turned off, thereby isolating match line 40 from ground line 42. Under these conditions, match line 40 retains a pre-charged logic high value.
Conversely, if the comparison data value C does not match the data value D stored in SRAM cell 12, then node 34 is connected to receive a logic “1” signal. As a result, transistor 38 is turned on, thereby coupling match line 40 to ground line 42. Under these conditions, match line 40 is pulled down toward ground.
CAM cell 10 exhibits relatively high power consumption because the same driver circuitry 36 is used to supply the write data values as well as the comparison data values. Driver circuitry 36 is powered by the VCC supply voltage, such that both the write and comparison data values have logic high values of VCC. Moreover, the compare operation of CAM cell 10 is relatively slow because the capacitance of SRAM cell 12 is coupled to bit lines 24 and 26 during the compare operation.
It would therefore be desirable to have an improved CAM cell which allows a compare operation to be carried out using a supply voltage less than the VCC supply voltage. It would also be desirable for the improved CAM cell to have bit lines that are not coupled to the capacitance introduced by an SRAM cell during a compare operation. It would also be desirable for the improved CAM cell to be implemented using fewer transistors than conventional CAM cell 10. It would further be desirable for the improved CAM cell to have global and local masking capabilities.
Accordingly, the present invention provides a CAM cell that implements a match line having a signal swing equal to one transistor threshold voltage, or about 0.3 Volts. The operating power of the CAM cell of the present invention is relatively low because the match line only undergoes a small voltage swing during a compare operation.
A CAM in accordance with the present invention includes an SRAM cell that operates in response to a VCC supply voltage. One or more read/write bit lines are coupled to the SRAM cell, thereby allowing read and write data values to be transferred to and from the SRAM cell. The VCC and ground voltage supplies provide signals to the read/write bit lines. That is, the signals applied to the read/write bit lines vary between a high voltage of VCC and a low voltage of 0 Volts.
One or more comparison bit lines are coupled to receive a comparison data value. The signals transmitted on the comparison bit lines have a signal swing that is less than the VCC supply voltage. In one embodiment, the signal swing on the comparison bit lines is equal to two times the transistor threshold voltage. Thus, if the transistor threshold voltage is equal to 0.3 Volts, then the signal swing on the comparison bit lines is equal to 0.6 Volts. Because the comparison bit lines are not directly connected to the SRAM cell, the capacitance of the SRAM cell is advantageously not coupled to the comparison bit lines. This improves both operating speed and power consumption of the CAM cell.
Moreover, the signals transmitted on the comparison bit lines are generated by a bit line control circuit that is powered in response to a supply voltage VCC1 that is significantly lower than the VCC supply voltage. In one embodiment, the supply voltage VCC1 can have a value as low as 0.9 Volts. By lowering the supply voltage required to perform a compare operation, the power of operating the CAM is advantageously reduced.
A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value provided on the comparison bit lines. The sensor circuit pre-charges the match line prior to a compare operation. If the data value stored in the CAM cell does not match the comparison data value, the match line is pulled down. The signal swing of the match line is smaller than the VCC supply voltage. In one embodiment, the signal swing on the match line is equal to transistor threshold voltage, or 0.3 Volts.
The sensor circuit monitors the voltage on the match line to determine whether the comparison data value matches the data value stored in the CAM cell (a match condition), or whether the comparison data value fails to match the data value stored in the CAM cell (a no-match condition). The sensor circuit converts the small swing signal on the match line to a large swing output signal. This output signal has a signal swing equal to the VCC supply voltage.
In one embodiment of the invention, a bit line control circuit is provided to control the voltages on the comparison bit lines. The bit line control circuit equalizes the voltages on the comparison bit lines to an intermediate voltage prior to each compare operation. As a result, less power is consumed during the compare operation. In one embodiment the intermediate voltage is equal to a transistor threshold voltage (e.g., 0.3 Volts).
The present invention will be more fully understood in view of the following description and drawings.
N-channel transistor 114 is coupled as an access transistor between node N1 and read/write bit line 101. Similarly, n-channel transistor 115 is coupled as an access transistor between node N2 and read/write bit line 102. Read/write bit lines 101 and 102 are coupled to receive read/write data values D0 and D0#, respectively, from column decoder circuitry (not shown). Read/write data value D0 has a logic high value of VCC and a logic low level of 0 Volts during a write operation. Similarly, read/write data value D0 has a logic high value of VCC and a logic low level of VCC−CV during a read operation (where CV is about 300 mV). The gates of access transistors 114 and 115 are commonly connected to word line 105. Word line 105 is coupled to receive word line signal WL0 from row decoder circuitry (not shown). The word line signal VL0 has a logic high value of VCC and a logic low value of 0 Volts.
Comparison bit lines 103 and 104 are coupled to receive comparison data values CD0 and CD0# from bit line control circuit 120, which is described in more detail below in connection with FIG. 5. Comparison data value CD0 has a logic high value of 0.6 Volts, a logic low value of 0 Volts, and a pre-charge value of 0.3 Volts. Thus, the voltages used during a comparison operation are much lower than the VCC supply voltage. Moreover, bit line control circuit 120 operates in response to a supply voltage VCC1, which is much less than the VCC supply voltage. In the described embodiment, the VCC1 supply voltage is about 0.9 Volts. As a result, the power requirements of CAM cell 100 are much less than a conventional 9-T CAM cell. In addition, the bit lines 103-104 used to perform a comparison are not coupled to the 6-T SRAM cell. As a result, the comparison operation is not burdened by the capacitance introduced by the 6-T SRAM cell. N-channel transistors 116 and 117 are connected in series between bit lines 103 and 104. Transistors 116 and 117 are commonly connected at node N3. The gates of transistors 116 and 117 are connected to nodes N1 and N2, respectively. Node N3 is coupled to a match sense line 150 through diode element 119 and n-channel transistor 118. Match sense line 150 is coupled to sensor circuit 130.
Diode element 119 can be implemented in various ways, including a conventional p-n junction or a diode-connected transistor.
CAM cell 200 includes read/write bit lines 201-202, comparison bit lines 203-204, word line 105, p-channel transistors 210-211, n-channel transistors 212-218, and diode element 219. The elements of CAM cell 200 are connected in the same manner as the elements of CAM cell 100. CAM cell 200 is connected to word line 105 in the same manner as CAM cell 100. Similarly, CAM cell 200 is connected to match sense line 150 in the same manner as CAM cell 100. Read/write bit lines 201 and 202 of CAM cell 200 are coupled to receive read/write data values D1 and D1# from column control circuitry (not shown). Comparison bit lines 203 and 204 of CAM cell 200 are coupled to receive comparison data values CD1 and CD1# from bit line control circuit 220.
CAM cell 300 includes read/write bit lines 101-102, comparison bit lines 103-104, word line 106, p-channel transistors 310-311, n-channel transistors 312-318, and diode element 319. Similarly, CAM cell 400 includes read/write bit lines 201-202, comparison bit lines 203-204, word line 106, p-channel transistors 410-411, n-channel transistors 412-418, and diode element 419. The elements of CAM cells 300 and 400 are connected in the same manner as the elements of CAM cell 100. CAM cells 300 and 400 are coupled to a second word line 106 in the same manner that CAM cells 100 and 200 are coupled to word line 105. Similarly, CAM cells 300 and 400 are coupled to a second match sense line 151 in the same manner that CAM cells 100 and 200 are coupled to match sense line 150. Match sense line 151 is coupled to a sensor circuit 131, which is identical to sensor circuit 130. Note that CAM cells 100 and 300 share bit lines 101-104. Similarly, CAM cells 200 and 400 share bit lines 201-204.
Although the array illustrated in
Data values are written to a row of CAM cells (e.g., CAM cells 100 and 200), as follows. The voltage WL0 on word line 105 is pulled up to the VCC supply voltage (e.g., 2.5 Volts) by the row decoder circuitry. As a result, access transistors 114-115 and 214-215 are turned on, thereby coupling bit lines 101-102 and 201-202 to the storage latches in CAM cells 100 and 200. The voltage WL1 on the second word line 106 is pulled down to 0 Volts, thereby turning off access transistors 314-315 and 414-415 in CAM cells 300 and 400. As a result, bit lines 101-102 and 201-202 are isolated from the storage latches in CAM cells 300 and 400.
The column decoder circuitry applies write data values D0, D0#, D1, and D1# to bit lines 101, 102, 201 and 202, respectively. These write data values have a logic high value equal to the VCC supply voltage and a logic low value of 0 Volts. In the described example, data values D0, D0#, D1, and D1# have values of VCC, 0, 0 and VCC, respectively. The write data values D0, D0#, D1, and D1# are transmitted through turned on access transistors 114-115 and 214-215 to the storage latches in CAM cells 100 and 200. The word line signal WL0 is then de-asserted low, thereby turning off access transistors 114-115 and 214-215, and latching the write data values D0, D0#, D1, and D1# in the storage latches of CAM cells 100 and 200. Write operations are therefore performed in the same manner as in a conventional six-transistor SRAM array. In the present example, nodes N1, N2, N4 and N5 store voltages of VCC, 0 Volts, 0 Volts and VCC, respectively.
Data values are read from a row of CAM cells (e.g., CAM cells 100 and 200), as follows. The column decoder circuitry applies the VCC supply voltage to read/write bit lines 101, 102, 201 and 202. The voltage WL0 on word line 105 is pulled up to the VCC supply voltage (e.g., 2.5 Volts) by the row decoder circuitry. As a result, access transistors 114-115 and 214-215 are turned on, thereby coupling bit lines 101-102 and 201-202 to the storage latches in CAM cells 100 and 200. The voltage WL1 on the second word line 106 is pulled down to 0 Volts, thereby turning off access transistors 314-315 and 414-415 in CAM cells 300 and 400. As a result, bit lines 101-102 and 201-202 are isolated from the storage latches in CAM cells 300 and 400.
In the present example, nodes N2 and N4 are pulled down through transistors 113 and 212, respectively. When access transistors 115 and 214 are turned on, bit lines 102 and 201 are pulled down by transistors 113 and 212, respectively. Nodes N2 and N4 are pulled down to VCC-CV at this time, where CV is approximately 300 mV. Bit lines 101 and 202 are not pulled down in this manner. Sense amplifiers (not shown) coupled to bit lines 101-102 and 201-202 sense the different voltages on these bit lines to identify the data values stored by CAM cells 100 and 200. Read operations are therefore performed in the same manner as in a conventional six-transistor SRAM array.
During standby conditions, word lines 105 and 106 are maintained at 0 Volts, thereby isolating the CAM cells 100, 200, 300 and 400 from read/write bit lines 101-102 and 201-202. Read/write bit lines 101-102 and 201-202 are held at either VCC or 0 Volts during standby conditions.
A compare operation is performed as follows. During a compare operation, word lines 105 and 106 are maintained at a voltage of 0 Volts, thereby isolating the CAM cells 100, 200, 300 and 400 from bit lines 101-102 and 201-202. Read/write bit lines 101-102 and 201-202 are held at either VCC or 0 Volts during a compare operation. A compare operation is simultaneously performed within each CAM cell of the array, unless there is global or local masking that inhibits the compare operation within the CAM cell. For purposes of clarity, a compare operation within CAM cell 100 is described in detail. The compare operations performed within CAM cells 200, 300 and 400 are identical to the compare operation performed within CAM cell 100.
The compare operation within CAM cell 100 is controlled by bit line control circuit 120 and sensor circuit 130. In general, the data value in the storage latch of CAM cell 100 turns on one and only one of transistors 116 and 117, thereby coupling one of the comparison bit lines 103-104 to node N3. Prior to the comparison operation, node N3 and comparison bit lines 103-104 are maintained at 0.3 Volts (assuming there is no global masking enabled by bit line control circuit 120). Local masking transistor 118 is turned on (assuming there is no local masking enabled within CAM cell 100). Sensor circuit 130 maintains match sense line 150 at a voltage of 0.6 Volts. A 0.3 Volt forward voltage drop therefore exists across diode-connected transistor 119A.
To initiate the comparison operation, bit line control circuit 120 applies comparison data values CD0 and CD0# to comparison bit lines 103 and 104, respectively. The logic high comparison data value has a voltage of 0.6 Volts, and the logic low comparison data value has a voltage of 0 Volts. If the comparison data value matches the data value stored in CAM cell 100, then a voltage of 0.6 Volts is applied to node N3. Under these conditions, the voltage on match sense line 150 remains at 0.6 Volts. If the comparison data value does not match the data value stored in CAM cell 100, then a voltage of 0 Volts is applied to node N3. Under these conditions, the voltage on match sense line 150 is pulled down to 0.3 Volts. Sensor circuit 130 senses the voltage on match sense line 150, and indicates a match condition if match sense line 150 is maintained at 0.6 Volts, and indicates a no-match condition if match sense line 150 is pulled down to 0.3 Volts. Because the full signal swing on match sense line 150 is equal to 0.3 Volts, and because the comparison bit lines are operated at voltages much less than the VCC supply voltage, the power requirements of a compare operation are advantageously very low in CAM cell 100.
Local masking signal LM#1 is an active low signal. If the local masking signal LM#1 has a logic low value, local masking transistor 118 is turned off, thereby isolating node N3 from match sense line 150. Under these conditions, match sense line is maintained at 0.6 Volts, regardless of the results of the comparison within CAM cell 100. CAM cell 100 therefore performs as if a match condition exists, regardless of the results of the comparison within CAM cell 100. In this manner, local masking transistor 118 enables CAM cell 100 to be effectively masked from the comparison operation. Although
Bit line control circuit 120 and sensor circuit 130 will now be described in more detail.
Under these conditions, transistors 514 and 515 are turned on by current source 504. Each of transistors 514 and 515 has a threshold voltage of 0.3 Volts. As a result, the voltage on match sense line 150 is held at 0.6 Volts. At this time, the voltage on node N3 is equal to 0.3 Volts, or one threshold voltage below the voltage on match sense line 150.
The compare operation begins when the CLK2 signal goes high. The CLK2 signal transitions to a logic high state shortly before the CLK1 signal transitions to a logic high state. As a result, the output signal provided by NAND gate 505 remains high for a short time after the CLK2 signal goes high. This ensures that transistor 512 remains on while the CLK2 signal goes high, thereby preventing noise conditions from pulling down the voltage on match sense line 150. The CLK1 signal then transitions to a logic high value, such that the output voltage provided by NAND gate 505 is determined by the state of the voltage on match sense line 150. At this time, node N3 is either pulled up to 0.3 Volts (if a match condition exists) or pulled down to 0 Volts (if a no-match condition exists).
As described in more detail below, during a match condition node N3 will be coupled to a comparison bit line having a voltage of 0.6 Volts through either transistor 116 or transistor 117. Under these conditions, no current flows through transistor 513. As a result, the gate of transistor 513 is maintained at about 0.6 Volts. This 0.6 Volt signal represents a logic low input signal to NAND gate 505. As a result, NAND gate 505 provides a logic high output signal to transistor 512. Transistor 512 therefore remains on (even though there is no current flow). If the signal on match sense line 150 is pulled low by noise, then current source 503 will pull the voltage on match sense line 150 back up to 0.6 Volts through turned on transistor 512.
The logic high output of NAND gate 505 is also provided to inverter 502. In response, inverter 502 provides a logic low output signal having a voltage equal to the ground supply voltage (e.g., 0 Volts). This output signal is used to indicate a match condition to an encoder circuit (not shown). As described in more detail below, during a no-match condition node N3 will be coupled to a comparison bit line having a voltage of 0 Volts through either transistor 116 or transistor 117. As a result, node N3 is pulled down to 0 Volts. Under these conditions, current will flow through transistor 513. This current is greater than the current provided by current source 503. As a result, the voltage of match sense line 150 is pulled down to 0.3 Volts (i.e., one threshold voltage greater than the voltage on node N3). The 0.3 Volt signal on match sense line 150 causes the voltage on the gate of transistor 513 to be pulled up to the VCC supply voltage (e.g., 2.5 Volts) by current source 504. This VCC supply voltage represents a logic high input signal to NAND gate 505. Consequently, NAND gate 505 provides a logic low output signal to the gate of transistor 512. As a result, transistor 512 is turned off, thereby preventing DC current flow through transistor 513.
The logic low output of NAND gate 505 is also provided to inverter 502. In response, inverter 502 provides a logic high output signal having a voltage equal to the VCC supply voltage (e.g., 2.5 Volts). This output signal is used to indicate a no-match condition to an encoder circuit (not shown).
Although the operation of sensor circuit 130 has been described in connection with a single CAM cell 100, it is understood that a match condition must exist in all of the CAM cells coupled to match sense line 150 in order for sensor circuit 130 to provide a logic high output signal to the encoder. Conversely, if a no-match condition exists in any one of the CAM cells coupled to match sense line 150, then sensor circuit 130 will provide a logic low output signal to the encoder.
Bit line control circuit 120 operates as follows. Transistors 628-630 and current source 631 are connected to form a regulated voltage source 640. Current source 631, which operates in response to the VCC supply voltage, turns on transistors 629 and 630. Each of transistors 629 and 630 has a threshold voltage of 0.3 Volts. As a result, the voltage on voltage supply line 650 is held at 0.6 Volts. Transistor 628, which is coupled to the VCC1 voltage supply (0.9 Volts), is turned on to help pull up voltage supply line 650 to 0.6 Volts. In the described embodiment, the voltage on voltage supply line 650 is selected to be equal to two times the threshold voltage of an n-channel transistor (i.e., 0.3 Volts).
Global masking signal GM# is an active low signal. When the global masking signal GM# has a logic low value, inverters 602-604 provide a logic high signal to transistors 621 and 622, thereby turning on these transistors. The logic low GM# signal causes transistors 623-626 to be turned off. Transistor 627 is either turned off or turned on, depending on the state of the CLK2 signal. Under these conditions, both of comparison bit lines 103 and 104 are connected to receive a voltage of 0.6 Volts from voltage supply line 650. If both of comparison bit lines 103 have a voltage of 0.6 Volts, then all of the CAM cells in the column served by bit line control circuit 120 will indicate a match condition during a compare operation. As a result, the entire column is effectively masked during such a compare operation.
When the global masking signal GM# is de-asserted high, transistors 621 and 622 are turned off. During this time, the CLK2 signal can have a logic low or logic high value. A pre-charge operation is performed if the CLK2 signal has a logic low value, and a compare operation is performed if the CLK2 signal has a logic high value. If the CLK2 signal has a logic low value, transistor 627 is turned on, thereby connecting comparison bit lines 103 and 104. The logic low CLK2 signal further causes transistors 623-626 to turn off, thereby isolating comparison bit lines 103 and 104 from voltage supply line 650 and the ground voltage supply. As a result, the voltages on both bit lines 103 and 104 are equalized at 0.3 Volts by sensor circuit 130 during the pre-charge operation. Note that the comparison data input value DIN does not have any effect on transistors 623-627 when the CLK2 signal has a logic low value.
A compare operation occurs when the CLK2 signal transitions to a logic high value (and the GM# signal is de-asserted high). Under these conditions, transistors 621-622 and 627 are turned off. Comparison data input value DIN is asserted at this time. A comparison data input value DIN having a logic high state will turn on transistors 623 and 624 (and turn off transistors 625 and 626), thereby applying 0.6 Volts to comparison bit line 103 and 0 Volts to comparison bit line 104. Conversely, a comparison data input value DIN having a logic low state will turn on transistors 625 and 626 (and turn off transistors 623 and 624), thereby applying 0.6 Volts to comparison bit line 104 and 0 Volts to comparison bit line 103.
Although the present invention has been described in connection with particular embodiments, other embodiments are possible and are considered to be within the scope of the present invention.
CAM cells 2000, 3000 and 4000 include similar match transistors 2190, 3190 and 4190 and similar local masking transistors 2180, 3180 and 4180. CAM cells 3000 and 4000 share match sense lines 1520 and 1530, which in turn, are connected to sensor circuit 1310.
Bit line control circuits 1200 and 2200 are connected to comparison bit lines 103-104 and 203-204, respectively.
Although the array illustrated in
Because CAM cells 1000, 2000, 3000 and 4000 are identical, only CAM cell 1000 is described in detail. Similarly, because sensor circuits 1300 and 1310 are identical, only sensor circuit 1300 is described in detail.
CAM cell 1000 reverses the polarity of the comparison data values CD0 and CD0# provided by bit line control circuit 120, such that comparison data value CD0# is applied to comparison bit line 103, and comparison data value CD0 is applied to comparison bit line 104. In addition, voltage supply line 650 is directly connected to the VCC1 supply voltage of 0.9 Volts (3VT) instead of to regulated voltage source 640. Otherwise, the bit line control circuit 1200 is identical to bit line control circuit 120 (FIG. 6).
Read, write and standby operations are performed within CAM cell 1000 in the same manner described above in connection with CAM cell 100.
A compare operation is performed within CAM cell 1000 as follows. During a compare operation, word lines 105 and 106 are maintained at a voltage of 0 Volts, thereby isolating the CAM cells 1000, 2000, 3000 and 4000 from bit lines 101-102 and 201-202. Read/write bit lines 101-102 and 201-202 are held at either VCC or 0 Volts during a compare operation. A compare operation is simultaneously performed within each CAM cell of the array, unless there is global or local masking that inhibits the compare operation within the CAM cell. For purposes of clarity, a compare operation within CAM cell 1000 is described in detail. The compare operations performed within CAM cells 2000, 3000 and 4000 are identical to the compare operation performed within CAM cell 1000.
The compare operation within CAM cell 1000 is controlled by bit line control circuit 1200 and sensor circuit 1300. In general, the data value in the storage latch of CAM cell 1000 turns on one and only one of transistors 116 and 117, thereby coupling one of the comparison bit lines 103-104 to node N3. Prior to the comparison operation, node N3 and comparison bit lines 103-104 are maintained at 0.3 Volts (assuming there is no global masking enabled by bit line control circuit 1200). Local masking transistor 1180 is turned on (assuming there is no local masking enabled within CAM cell 1000). Sensor circuit 1300 maintains match sense lines 1500 and 1510 at 0.3 Volts.
To initiate the comparison operation, bit line control circuit 1200 applies comparison data values CD0 and CD0# to comparison bit lines 104 and 103, respectively. The logic high comparison data value has a voltage of 0.9 Volts (i.e., VCC1 or 3VT), and the logic low comparison data value has a voltage of 0 Volts. If the comparison data value matches the data value stored in CAM cell 1000, then a voltage of 0 Volts is applied to node N3. Under these conditions, match transistor 1190 is turned off, thereby allowing the voltage on match sense line 1500 to remain at 0.3 Volts. If the comparison data value does not match the data value stored in CAM cell 1000, then a voltage of 0.9 Volts is applied to node N3. Under these conditions, 1 match transistor 1190 turns on, thereby pulling down the voltage on match sense line 1500 down to 0 Volts. Sensor circuit 1300 senses the voltage on match sense line 1500, and indicates a no-match condition if match sense line 1500 is pulled down to 0 Volts, and indicates a match condition if match sense line 1500 remains at 0.3 Volts. Because the full signal swing on match sense line 1500 is equal to 0.3 Volts, and because the bit line control circuit 1200 is powered by the VCC1 supply voltage, the power requirements of a compare operation are advantageously very low in CAM cell 1000.
Local masking signal LM#1 is an active low signal. If the local masking signal LM#1 has a logic low value, local masking transistor 1180 is turned off, thereby isolating match sense lines 1500 and 1510. Under these conditions, match sense line is maintained at 0.3 Volts, regardless of the results of the comparison within CAM cell 1000. CAM cell 1000 therefore performs as if a match condition exists, regardless of the results of the comparison within CAM cell 1000. In this manner, local masking transistor 1180 enables CAM cell 1000 to be effectively masked from the comparison operation. Although
During a pre-charge period before the compare operation is performed, the CLK1 and CLK2 signals have logic low values. The logic low CLK2 signal causes transistor 511 to turn on, thereby coupling the VCC1 supply voltage to the drain of transistor 513. In the described example, the VCC1 supply voltage is equal to approximately three times the threshold voltage of an n-channel transistor, or about 0.9 Volts. The logic low CLK1 signal causes NAND gate 505 to provide a logic high output signal (e.g., 2.5 Volts) to the gate of transistor 512, thereby turning on this transistor. As a result, transistor 512 also helps to pull up the voltage on the drain of transistor 513 to the VCC1 supply voltage.
Under these conditions, transistor 514 is turned on by current source 504. Transistor 514 has a threshold voltage of 0.3 Volts. As a result, the voltage on match sense line 1500 is held at 0.3 Volts. The logic low CLK2 signal causes transistor 516 to turn on, thereby coupling match sense lines 1500 and 1510. Consequently, match sense line 1510 is also held at 0.3 Volts.
The compare operation begins when the CLK2 signal goes high. The logic high CLK2 signal causes transistors 511 and 516 to be turned off. The CLK2 signal transitions in a logic high state shortly before the CLK1 signal transitions to a logic high state. As a result, the output signal provided by NAND gate 505 remains high for a short time after the CLK2 signal goes high. This ensures that transistor 512 remains on while the CLK2 signal goes high, thereby preventing noise conditions from pulling down the voltage on match sense line 1500. The CLK1 signal then transitions to a logic high value, such that the output voltage provided by NAND gate 505 is determined by the state of the voltage on match sense line 1500. At this time, node N3 is either pulled up to 0.9 Volts (if a no-match condition exists) or pulled down to 0 Volts (if a match condition exists).
As previously described, during a no-match condition node N3 will be coupled to a comparison bit line having a voltage of 0.9 Volts through either transistor 116 or transistor 117. Under these conditions, match transistor 1190 turns on, and current flows through transistor 513. This current is greater than the current provided by current source 503. As a result, the voltage of match sense line 1500 is pulled down to 0 Volts. The 0 Volt signal on match sense line 1500 causes the voltage on the gate of transistor 513 to be pulled up to the VCC supply voltage (e.g., 2.5 Volts) by current source 304. This VCC supply voltage represents a logic high input signal to NAND gate 505. Consequently, NAND gate 505 provides a logic low output signal to the gate of transistor 512. As a result, transistor 512 is turned off, thereby preventing DC current flow through transistor 513.
The logic low output of NAND gate 505 is also provided to inverter 502. In response, inverter 502 provides a logic high output signal having a voltage equal to the VCC supply voltage (e.g., 2.5 Volts). This output signal is used to indicate a no-match condition to an encoder circuit (not shown).
As described above, during a match condition node N3 will be coupled to a comparison bit line having a voltage of 0 Volts through either transistor 116 or transistor 117. As a result, no current flows through transistor 513. Consequently, the gate of transistor 513 is maintained at about 0.3 Volts. This 0.3 Volt signal represents a logic low input signal to NAND gate 505. As a result, NAND gate 505 provides a logic high output signal to transistor 512. Transistor 512 therefore remains on (even though there is no current flow). If the signal on match sense line 1500 is pulled low by noise, then current source 503 will pull the voltage on match sense line 1500 back up to 0.3 Volts through turned on transistor 512.
The logic high output of NAND gate 505 is also provided to inverter 502. In response, inverter 502 provides a logic low output signal having a voltage equal to 0 Volts. This output signal is used to indicate a match condition to an encoder circuit (not shown).
Although the operation of sensor circuit 1300 has been described in connection with a single CAM cell 1000, it is understood that a match condition must exist in all of the CAM cells coupled to match sense line 1500 in order for sensor circuit 1300 to provide a logic low output signal to the encoder. Conversely, if a no-match condition exists in any one of the CAM cells coupled to match sense line 1500, then sensor circuit 1300 will provide a logic high output signal to the encoder.
Although the present invention has been described in connection with particular embodiments, other embodiments are possible and are considered to be within the scope of the present invention.
Although the present invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. Thus, the invention is limited only by the following claims.
Lien, Chuen-Der, Wu, Chau-Chin
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