A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system (10) which comprises a control and timing circuit (18), a microprogram store (20) and a multiplier circuit (34). The multiplier circuit (34) may comprise a rectangular aspect ratio multiplier circuit (40) having an additional ADDER INPUT to enable the repeated evaluation of first order polynomials to evaluate polynomial expansions associated with each mathematical function. A constant store (28) is used to store predetermined coefficients for the polynomial expansion associated with each mathematical functions function. The microprogram store (20) is used to store argument transformation routines, polynomial expansions and result transformation routines associated with each mathematical function. The questions raised in reexamination request No. 90/004,138, filed Feb. 12, 1996, have been considered and the results thereof are reflected in this reissue patent which constitutes the reexamination certificate required by 35 U.S.C. 307 as provided in 37 CFR 1.570(e).
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1. A numeric system for computing approximations of a plurality of mathematical functions, comprising:
a multiplier circuit;
a circuitry for receiving signals indicating a mathematical function to be evaluated, an interval for which an approximation is to be computer, a maximum allowable relative error in a result and an initial argument;
first circuitry, electrically coupled to said circuitry for receiving signals, for transforming said initial argument into first and second transformed arguments which may be used in a fixed-point evaluation of a polynomial approximation associated with said indicated mathematical function;
circuitry, electrically coupled to said circuitry for transforming, for evaluating said polynomial approximation associated with said indicated mathematical function, said polynomial approximation being a function of said second transformed argument, wherein said circuitry for evaluating said polynomial approximation comprises said multiplier circuit;
a first memory circuit, electrically coupled to said multiplier circuit, for storing constants associated with said indicated mathematical function;
control circuitry, electrically coupled to said first memory circuit, for selecting and inputting selected ones of said constants into said multiplier circuit;
circuitry, electrically coupled to said first circuitry for transforming, for determining a first value of an approximating function using said first transformed argument and a second value generated through evaluation of said polynomial approximation; and
second circuitry, electrically coupled to said first circuitry for determining, for transforming said first value of said approximating function to recover a result comprising the approximation of the mathematical function for said initial argument.
13. A method for computing approximations of a plurality of mathematical functions, said approximations having a significand and a precision defined by the number of bits in said significand, using a numeric system comprising a rectangular aspect ratio multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, a bus interface circuit, mantissa and exponent arithmetic logic units and associated file circuits, a constant store circuit, a microprogram store circuit and a timing and control circuit, said numeric system having hardware precision greater than that of said approximations, said method comprising the steps of:
receiving electrical signals indicating a mathematical function to be evaluated, electrical signals representing an interval for which the approximation of the indicated mathematical function is to be computed, electrical signals representing a maximum allowable relative error in a result and electrical signals representing an initial argument;
transforming the electrical signals representing the initial argument into electrical signals representing first and second transformed arguments, the electrical signals representing the arguments transformed such that the electrical signals representing the arguments may be used in a fixed-point evaluation of a polynomial approximation associated with the indicated mathematical function having values within intervals associated with an approximating function for the indicated mathematical function, said first and second transformed arguments having precision greater than that of said approximations;
determining a set of electrical signals representing constants to be used in the polynomial approximation associated with the indicated mathematical function;
evaluating a polynomial approximation associated with the indicated mathematical function by inputting the electrical signals representing the second transformed argument and a set of electrical signals representing constants for said polynomial approximation into the rectangular aspect ratio multiplier circuit, the polynomial approximation being a function of the second transformed argument and said evaluation being performed through a plurality of iterations in which values of primitive arithmetic operations required for said iterations are computed by said multiplier circuit and return to an input of the multiplier circuit at a precision greater than that of said approximations, said polynomial approximation being computed to a precision sufficient to allow monotonic behavior of the indicated mathematical function to the preserved in computing approximations of said indicated mathematical function; and
determining electrical signals representing a first value of an approximation the approximating function using the electrical signals representing the first transformed argument and electrical signals representing a second value generated by said step of evaluation evaluating the polynomial approximation; and
transforming the electrical signals representing the first value of the approximating function to recover electrical signals representing a result comprising the approximation of the mathematical function for the initial argument.
0. 42. A method for computing approximations of a plurality of transcendental functions using a numeric processing system comprising a microprogram store circuit programmed with control information for implementing routines to compute approximations of said plurality of transcendental functions, a timing and control circuit, a constant store circuit, a bus interface circuit, mantissa and exponent arithmetic logic units and associated file circuits, and a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations and a rectangular aspect ratio, the method comprising the steps of:
receiving electrical signals indicating a transcendental function to be evaluated and an initial argument, said transcendental function having an associated first interval for which the approximation of the transcendental function is to be computed and an associated approximating function comprising a polynomial approximation;
transforming the electrical signals representing the initial argument into electrical signals representing one or more transformed arguments, said first transformed argument being within the predetermined argument interval, said second transformed argument being a function of said first transformed argument and having precision greater than that of said approximations;
evaluating the polynomial approximation by inputting the electrical signals representing at least one of the transformed arguments into said multiplier circuit, and by selecting and inputting from said constant store circuit into said multiplier circuit electrical signals representing predetermined constants associated with said approximating function, said approximating function providing an iterative approximation which, over a predetermined interval, has sufficiently low relative error to preserve monotonic behavior of the transcendental function, and said polynomial approximation being a function of the inputted transformed argument, wherein said multiplier circuit computes and outputs results of a plurality of primitive operations required for iterative evaluation of said polynomial to a precision greater than said result; and
determining electrical signals representing a result comprising the approximation of the transcendental function for the initial argument, using electrical signals representing a first value generated by said step of evaluating the polynomial approximation;
wherein said step of evaluating the polynomial comprises the step of:
using electrical signals representing at least one of said computed values of said primitive operations to determine electrical signals representing an input value for use in computing another of said primitive operations, said input value being of greater precision than said result.
0. 34. A numeric processing system which provides approximations of the sine function, comprising:
a system bus;
interface circuitry coupled to said system bus and to an integrated data processing system by which said integrated data processing system provides an input argument to said numeric processing system, and by which said numeric processing system transfers approximation results to said integrated data processing system, each result having a significand and a precision defined by the number of bits in said significand;
a microprogram store circuit programmed with control information for implementing a routine to approximate the sine function of said input argument, said approximation routine comprising argument transformation routines for reducing said input argument and one or more polynomial evaluation routines each for determining a value of a polynomial by computing iterative arithmetic expressions;
a constant store circuit coupled to said system bus;
mantissa arithmetic processing circuitry coupled to said system bus;
exponent arithmetic processing circuitry coupled to said system bus;
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit being coupled to said system bus and having circuitry for receiving constants from said constant store circuit and operands from said mantissa arithmetic processing circuitry as input values and for computing and outputting iterative values of arithmetic expressions, at least one of said computed and outputted values being used as an input value for a subsequent iteration, said multiplier circuit having data paths capable of routing values with more bits of precision than said significand of said result, and said input and computed values having precision greater than the highest precision at which the system is capable of providing said results; and
a control and timing circuit coupled to said interface circuitry, said microprogram store circuit, said constant store circuit, said mantissa arithmetic processing circuitry, said exponent arithmetic processing circuitry and said multiplier circuit, said control and timing circuit cooperating with said microprogram store circuit to generate control signals for controlling operation of said numeric processing system in accordance with said sine function approximation routine;
wherein said numeric processing system preserves monotonic behavior of the sine function in computed approximation results by limiting error in said approximation results to less than one unit in the least significant bit position at the highest precision at which said system is capable of providing said results, said error being limited at least in part by employing internal hardware precision greater than said highest precision in intermediate computations throughout said one or more polynomial evaluation routines to maintain increased accuracy.
0. 43. A method for computing approximations of a plurality of transcendental functions using a numeric processing system comprising a microprogram store circuit programmed with control information for implementing routines to compute approximations of said plurality of transcendental functions, a timing and control circuit, a constant store circuit, a bus interface circuit, mantissa and exponent arithmetic logic units and associated file circuits, and a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations, the method comprising the steps of:
receiving electrical signals indicating a transcendental function to be evaluated and an initial argument, said transcendental function having an associated first interval for which the approximation of the transcendental function is to be computed and an associated approximating function comprising a polynomial approximation;
transforming the electrical signals representing the initial argument into electrical signals representing one or more transformed arguments, said first transformed argument being within the predetermined argument interval, said second transformed argument being a function of said first transformed argument and having precision greater than that of said approximations;
evaluating the polynomial approximation by inputting the electrical signals representing at least one of the transformed arguments into said multiplier circuit, and by selecting and inputting from said constant store circuit into said multiplier circuit electrical signals representing predetermined constants associated with said approximating function, said approximating function providing an iterative approximation which, over a predetermined interval, has sufficiently low relative error to preserve monotonic behavior of the transcendental function, and said polynomial approximation being a function of the inputted transformed argument, wherein said multiplier circuit computes and outputs results of a plurality of primitive operations required for iterative evaluation of said polynomial to a precision greater than said result; and
determining electrical signals representing a result comprising the approximation of the transcendental function for the initial argument, using electrical signals representing a first value generated by said step of evaluating the polynomial approximation;
wherein said step of evaluating the polynomial comprises the step of:
using electrical signals representing at least one of said computed values of said primitive operations to determine electrical signals representing an input value for use in computing another of said primitive operations, said input value being of greater precision than said result; and
wherein said transforming step is performed by computing to a greater precision than said result; and
wherein said transforming and evaluating steps are performed by computing to a precision sufficient to allow the monotonic behavior of said transcendental functions to be preserved in said result.
0. 32. A numeric system for computing approximations of a plurality of transcendental functions, said approximations having a significand and a precision defined by the number of bits in said significand, comprising:
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations and circuitry for outputting computed values at a precision greater than that of said approximations, said multiplier circuit having a rectangular aspect ratio;
a bus interface circuit for receiving signals indicating a transcendental function to be evaluated and an initial argument, said transcendental function having an associated first interval for which the approximation is to be computed and an associated approximating function comprising a polynomial;
mantissa and exponent arithmetic logic units and associated file circuits;
a first memory circuit for storing predetermined constants associated with said approximating function, said predetermined constants providing an associated maximum relative error in a computed approximation;
bus means electrically coupling said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said memory circuit, for routing data between said circuits of said system; and
control circuitry, electrically coupled to and controlling operation of said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit;
wherein said multiplier circuit, under control of said control circuitry and in cooperation with said mantissa and exponent arithmetic logic units, said associated file circuits, and said first memory circuit, comprises computing means for:
(a) transforming said initial argument into one or more transformed arguments with values within one or more intervals associated with said approximating function;
(b) evaluating said polynomial using at least one of said computed values to determine an input value for use in computing another of said computed values, and each such input value being of a greater precision than said result, said polynomial being a function of at least one of said transformed arguments, wherein said multiplier circuit receives as inputs predetermined constants from said first memory circuit and computes a plurality of values of primitive operations required for evaluation of said polynomial to a precision greater than that of said result, said evaluation being performed through a plurality of iterations in which values of primitive operations computed by the multiplier circuit are returned to an input of the multiplier circuit at a precision greater than that of said approximations; and
(c) determining said result comprising the approximation of the transcendental function for said initial argument, using a first value generated through said evaluation of said polynomial, wherein said numeric system increases accuracy of said approximations by maintaining increased precision throughout calculation of said approximations.
0. 33. A numeric system for computing approximations of a plurality of transcendental functions, said approximations having a significand and a precision defined by the number of bits in said significand, comprising:
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations and circuitry for outputting computed values at a precision greater than that of said approximations;
a bus interface circuit for receiving signals indicating a transcendental function to be evaluated and an initial argument, said transcendental function having an associated first interval for which the approximation is to be computed and an associated approximating function comprising a polynomial;
mantissa and exponent arithmetic logic units and associated file circuits;
a first memory circuit for storing predetermined constants associated with said approximating function, said predetermined constants providing an associated maximum relative error in a computed approximation;
bus means electrically coupling said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said memory circuit, for routing data between said circuits of said system; and
control circuitry, electrically coupled to and controlling operation of said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit;
wherein said multiplier circuit, under control of said control circuitry and in cooperation with said mantissa and exponent arithmetic logic units, said associated file circuits, and said first memory circuit, comprises computing means for:
(a) transforming said initial argument into one or more transformed arguments with values within one or more intervals associated with said approximating function;
(b) evaluating said polynomial using at least one of said computed values to determine an input value for use in computing another of said computed values, and each such input value being of a greater precision than said result, said polynomial being a function of at least one of said transformed arguments, wherein said multiplier circuit receives as inputs predetermined constants from said first memory circuit and computes a plurality of values of primitive operations required for evaluation of said polynomial to a precision greater than that of said result, said evaluation being performed through a plurality of iterations in which values of primitive operations computed by the multiplier circuit are returned to an input of the multiplier circuit at a precision greater than that of said approximations; and
(c) determining said result comprising the approximation of the transcendental function for said initial argument, using a first value generated through said evaluation of said polynomial, wherein said numeric system increases accuracy of said approximations by maintaining increased precision throughout calculation of said approximations; and
wherein said multiplier circuit, in cooperation with said mantissa and exponent arithmetic logic units and said associated file circuits, computes to a greater precision than said result when transforming said initial argument and to a precision sufficient to allow the monotonic behavior of said transcendental functions to be preserved in said result.
0. 30. A numeric system for computing approximations of a plurality of mathematical functions, said approximations having a significant and a precision defined by the number of bits in said significant, said numeric system comprising:
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations for providing computed values at a precision greater than of that said approximations for use in subsequent operations of said numeric system;
a bus interface circuit for receiving signals indicating a mathematical function to be evaluated, an interval for which an approximation of said indicated mathematical function is to be computed, a maximum allowable relative error in a result and an initial argument;
mantissa and exponent arithmetic logic units and associated file circuits;
a first memory circuit which stores and supplies constants for computing approximations of said plurality of mathematical functions;
bus means electrically coupling said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said bus means including circuitry for returning values computed by the multiplier circuit to an input of said multiplier circuit, said circuitry having a hardware precision greater than that of said approximations; and
control circuitry, electrically coupled to and controlling operation of said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said control circuitry selecting and inputting selected ones of said constants into said multiplier circuit;
wherein said multiplier circuit, operating under control of said circuitry and in cooperation with said bus interface circuit, said mantissa and exponent arithmetic logic units, said associated file circuits, and said first memory circuit, comprises circuitry for:
(a) transforming an initial argument indicated by signals received by said bus interface circuit into first and second transformed arguments with values within intervals associated with an approximating function for a mathematical function indicated by signals received by said bus interface circuit, said first and second transformed arguments having precision greater than that of said approximations;
(b) evaluating a polynomial approximation associated with said indicated mathematical function as a function of said second transformed argument through a plurality of iterations in which values of primitive arithmetic operations required for said iterations are computed by said multiplier circuit and returned to an input of said multiplier circuit at a precision greater than that of said approximations,
(c) determining a first value of said approximating function using said first transformed argument and a second value generated through evaluation of said polynomial approximation; and
(d) transforming said first value of said approximating function to recover a result comprising the approximation of the mathematical function for said initial argument;
wherein the available precision of the numeric system is sufficient to allow monotonic behavior of the indicated mathematical function to be preserved in computed approximations of said indicated mathematical functions; and
wherein said multiplier circuit computes said arithmetic expressions used in evaluating said polynomial approximation to a greater precision then said result and said multiplier circuit computes to a precision sufficient to allow the monotonic behavior of said mathematical functions to be preserved in said result.
0. 31. A numeric system for computing approximations of a plurality of mathematical functions, said approximations having a significant and a precision defined by the number of bits in said significant, said numeric system comprising:
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations for providing computed values at a precision greater than of that said approximations for use in subsequent operations of said numeric system;
a bus interface circuit for receiving signals indicating a mathematical function to be evaluated, an interval for which an approximation of said indicated mathematical function is to be computed, a maximum allowable relative error in a result and an initial argument;
mantissa and exponent arithmetic logic units and associated file circuits;
a first memory circuit which stores and supplies constants for computing approximations of said plurality of mathematical functions;
bus means electrically coupling said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said bus means including circuitry for returning values computed by the multiplier circuit to an input of said multiplier circuit, said circuitry having a hardware precision greater than that of said approximations; and
control circuitry, electrically coupled to and controlling operation of said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said control circuitry selecting and inputting selected ones of said constants into said multiplier circuit;
wherein said multiplier circuit, operating under control of said circuitry and in cooperation with said bus interface circuit, said mantissa and exponent arithmetic logic units, said associated file circuits, and said first memory circuit, comprises circuitry for:
(a) transforming an initial argument indicated by signals received by said bus interface circuit into first and second transformed arguments with values within intervals associated with an approximating function for a mathematical function indicated by signals received by said bus interface circuit, said first and second transformed arguments having precision greater than that of said approximations;
(b) evaluating a polynomial approximation associated with said indicated mathematical function as a function of said second transformed argument through a plurality of iterations in which values of primitive arithmetic operations required for said iterations are computed by said multiplier circuit and returned to an input of said multiplier circuit at a precision greater than that of said approximations,
(c) determining a first value of said approximating function using said first transformed argument and a second value generated through evaluation of said polynomial approximation; and
(d) transforming said first value of said approximating function to recover a result comprising the approximation of the mathematical function for said initial argument;
wherein the available precision of the numeric system is sufficient to allow monotonic behavior of the indicated mathematical function to be preserved in computed approximations of said indicated mathematical functions;
wherein said multiplier circuit computes said arithmetic expressions used in evaluating said polynomial approximation to a greater precision then said result;
wherein said multiplier circuit, in cooperation with said mantissa and exponent arithmetic logic units and said associated file circuits, computes to a greater precision than said result when transforming said initial argument and when transforming said first value of said approximating function; and
wherein said multiplier circuit, in cooperation with said mantissa and exponent arithmetic logic units and said associated file circuits, computes to a precision sufficient to allow the monotonic behavior of said mathematical functions to be preserved in said result.
0. 39. A numeric processing system for computing approximations of transcendental functions, comprising:
a command and data interface coupled to an integrated data processing system by which said integrated data processing system provides commands and associated data values to said numeric processing system specifying respectively particular transcendental functions and input arguments for which approximations of said specified transcendental functions are to be computed, and by which said numeric processing system returns data values to said integrated data processing system representing computed approximations of said specified transcendental functions, said approximations of said specified transcendental functions each having a significand and a precision defined by the number of bits in said significand;
a bus interface unit coupled to said command and data interface and to control signal paths and a system bus of said numeric processing system, said bus interface unit including decode and route circuitry which decodes commands received from said integrated data processing system and routes said decoded commands and associated data values received from said integrated data processing system to said control signal paths and system bus respectively;
a microprogram store circuit programmed with control information for implementing transcendental function approximation routines, at least one of said transcendental function approximation routines comprising one or more argument transformation routines for generating a transformed argument from an input argument received from said integrated data processing system, and one or more polynomial evaluation routines for determining a value of a polynomial by computing iterative arithmetic expressions using said transformed argument and a plurality of constants;
a constant store circuit coupled to said system bus in which said plurality of constants are permanently stored;
mantissa arithmetic processing circuitry coupled to said system bus, including a mantissa memory circuit and arithmetic logic unit;
exponent arithmetic processing circuitry coupled to said system bus, including an exponent memory circuit and arithmetic logic unit;
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit being coupled to said system bus and having circuitry for receiving constants from said constant store circuit and operands from said mantissa arithmetic processing circuitry as inputs and for computing values of arithmetic expressions, said computed values having precision greater than the highest precision at which said numeric processing system is capable of returning said approximations of said specified transcendental functions to said integrated data processing system, said multiplier circuit also including wide data paths and latches for returning said computed values to an input of the multiplier circuit at precision greater than said highest precision, whereby iterations are performed without rounding to said highest precision; and
a control and timing circuit coupled to said control signal paths of said bus interface unit, said microprogram store circuit, said constant store circuit, said mantissa arithmetic processing circuitry, said exponent arithmetic processing circuitry and said multiplier circuit, said control and timing circuit cooperating with said microprogram store circuit to generate control signals for controlling operation of said numeric processing system in accordance with said transcendental function approximation routines;
wherein said control signals include control signals directing said multiplier circuit to compute and return to an input of the multiplier circuit values of iterative arithmetic expressions of a polynomial evaluation routine at precisions greater than said highest precision such that a precision greater than said highest precision is retained in intermediate computations throughout said polynomial evaluation routine,
said numeric system limiting error in a result such that the result is accurate to one unit in the least significant bit position at said highest precision, and such that approximates computed by the numeric system preserve monotonic behavior of the mathematical function.
2. The system of
circuitry for evaluating a first first-order polynomial comprising a first sum of a first constant and a product of a second constant and said second transformed argument;
circuitry for evaluating a second first-order polynomial comprising a second sum of a third constant and a product of a fourth constant and said first sum; and
circuitry for repeating the calculation of said second first order polynomial substituting for each repetition predetermined constants associated with said selected mathematical function for said third and fourth constants and substituting a value obtained from evaluating the first order polynomial of an immediately prior repetition for said first sum, a value generated by a final repetition constituting said second value generated by said polynomial approximation.
3. The system of
said multiplier circuit having an adder input, a multiplier input and a multiplicand input, such that said multiplier circuit can evaluate a product and a sum required in the calculation of each first order polynomial simultaneously, said memory circuit electrically coupled to said multiplier input and said adder input.
4. The system of
a feedback data path operating to selectably route a result output by said multiplier circuit to either said adder input of said multiplier circuit or said multiplicand input of said multiplier circuit responsive to control signals received from said control circuitry.
5. The system of
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations for providing computed values at a precision greater than of that said approximations for use in subsequent operations of said numeric system;
a bus interface circuit for receiving signals indicating a mathematical function to be evaluated, an interval for which an approximation of said indicated mathematical function is to be computed, a maximum allowable relative error in a result and an initial argument;
mantissa and exponent arithmetic logic units and associated file circuits;
a first memory circuit which stores and supplies constants for computing approximations of said plurality of mathematical functions;
bus means electrically coupling said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said bus means including circuitry for returning values computed by the multiplier circuit to an input of said multiplier circuit, said circuitry having a hardware precision greater than that of said approximations; and
control circuitry, electrically coupled to and controlling operation of said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said control circuitry selecting and inputting selected ones of said constants into said multiplier circuit;
wherein said multiplier circuit, operating under control of said circuitry and in cooperation with said bus interface circuit, said mantissa and exponent arithmetic logic units, said associated file circuits, and said first memory circuit, comprises circuitry for:
(a) transforming an initial argument indicated by signals received by said bus interface circuit into first and second transformed arguments with values within intervals associated with an approximating function for a mathematical function indicated by signals received by said bus interface circuit, said first and second transformed arguments having precision greater than that of said approximations;
(b) evaluating a polynomial approximation associated with said indicated mathematical function as a function of said second transformed argument through a plurality of iterations in which values of primitive arithmetic operations required for said iterations are computed by said multiplier circuit and returned to an input of said multiplier circuit at a precision greater than that of said approximations,
(c) determining a first value of said approximating function using said first transformed argument and a second value generated through evaluation of said polynomial approximation; and
(d) transforming said first value of said approximating function to recover a result comprising the approximation of the mathematical function for said initial argument;
wherein the available precision of the numeric system is sufficient to allow monotonic behavior of the indicated mathematical function to be preserved in computed approximations of said indicated mathematical functions; and
wherein said multiplier circuit, in cooperation with said mantissa and exponent arithmetic logic units and said associated file circuits, determines said first value of said approximating function by:
forming a product of said second value generated through evaluation of said polynomial approximation, said first transformed argument and a scaling factor, said product constituting said first value of said approximating function.
6. The system of
a multiplier circuit of the type including partial product generators and a plurality of adders capable of accumulating the partial products in a single pass, said multiplier circuit having internal hardware precision greater than that of said approximations for providing computed values at a precision greater than of that said approximations for use in subsequent operations of said numeric system;
a bus interface circuit for receiving signals indicating a mathematical function to be evaluated, an interval for which an approximation of said indicated mathematical function is to be computed, a maximum allowable relative error in a result and an initial argument;
mantissa and exponent arithmetic logic units and associated file circuits;
a first memory circuit which stores and supplies constants for computing approximations of said plurality of mathematical functions;
bus means electrically coupling said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said bus means including circuitry for returning values computed by the multiplier circuit to an input of said multiplier circuit, said circuitry having a hardware precision greater than that of said approximations; and
control circuitry, electrically coupled to and controlling operation of said multiplier circuit, said bus interface circuit, said mantissa and exponent arithmetic logic units and associated file circuits, and said first memory circuit, said control circuitry selecting and inputting selected ones of said constants into said multiplier circuit;
wherein said multiplier circuit, operating under control of said circuitry and in cooperation with said bus interface circuit, said mantissa and exponent arithmetic logic units, said associated file circuits, and said first memory circuit, comprises circuitry for:
(a) transforming an initial argument indicated by signals received by said bus interface circuit into first and second transformed arguments with values within intervals associated with an approximating function for a mathematical function indicated by signals received by said bus interface circuit, said first and second transformed arguments having precision greater than that of said approximations;
(b) evaluating a polynomial approximation associated with said indicated mathematical function as a function of said second transformed argument through a plurality of iterations in which values of primitive arithmetic operations required for said iterations are computed by said multiplier circuit and returned to an input of said multiplier circuit at a precision greater than that of said approximations,
(c) determining a first value of said approximating function using said first transformed argument and a second value generated through evaluation of said polynomial approximation; and
(d) transforming said first value of said approximating function to recover a result comprising the approximation of the mathematical function for said initial argument;
wherein the available precision of the numeric system is sufficient to allow monotonic behavior of the indicated mathematical function to be preserved in computed approximations of said indicated mathematical functions; and
wherein said multiplier circuit has a rectangular aspect ratio.
7. The system of
8. The system of
a second memory circuit coupled to said first circuitry for transforming said second circuitry for transforming and said circuitry for evaluating, said second memory circuit operating to store a polynomial approximation, an argument transformation routine for generating said first and second transformed arguments and a result transformation routine for each mathematical function; and
said control circuitry coupled to said second memory circuit for selecting and implementing an appropriate polynomial approximation, an appropriate argument transformation routine and an appropriate result transformation routine responsive to said selected function inputted.
9. The system of
an arithmetic logic unit for performing said addition and subtraction operations; and
said multiplier circuit for use in performing said multiplication, division and square root operations.
10. The system of
11. The system of
circuitry for generating a product of said first transformed argument and said second value generated through evaluation of said polynomial approximation using a floating point multiplication operation.
12. The system of
14. The method of
evaluating in the rectangular aspect ratio multiplier circuit a first first order first-order polynomial comprising a first sum of a first constant and a product of a second constant and the second transformed argument by inputting into the rectangular aspect ratio multiplier circuit electrical signals representing the first constant, the second constant and the second transformed argument;
evaluating a second first order first-order polynomial using the rectangular aspect ratio multiplier circuit, the second first order first-order polynomial comprising a second sum of a third constant and the product of a fourth constant the second transformed argument and the first sum, the second first order first-order polynomial evaluated by inputting into the rectangular aspect ratio multiplier circuit electrical signals representing the third constant, the fourth constant second transformed argument and the first sum; and
repeating said step of evaluating a second first order first-order polynomial substituting for each repetition electrical signals representing a predetermined constants associated with the selected mathematical function for the electrical signals representing the third and fourth constants and substituting electrical signals representing a value obtained from the evaluation of the first order first-order polynomial of the immediately prior repetition for the electrical signals representing the first sum, the electrical signals representing a value generated by a final repetition of said step of repeating constituting the electrical signals representing the second value generated by the said step of evaluating the polynomial approximation.
15. The method of
storing a set of electrical signals representing constants associated with each polynomial approximation associated with each mathematical function.
16. The method of
forming a product of the second value generated through the evaluation of the polynomial approximation, the first transformed argument and a scaling factor using the rectangular aspect ratio multiplier circuit by inputting into the rectangular aspect ratio multiplier circuit electrical signals representing the second value, the first transformed argument and the scaling factor, the product constituting the first value of the approximating function.
17. The method of
evaluating the polynomial approximation using fixed point computations.
18. The method of
storing in a memory circuit associated with the rectangular aspect ratio multiplier circuit electrical signals representing a polynomial approximation, argument transformation routine and a result transformation routine for each mathematical function; and
selecting electrical signals representing an appropriate polynomial approximation, an appropriate argument transformation routine and an appropriate result transformation routine responsive to said step of receiving signals indicating a function to be evaluated.
19. The method of
generating a product using the rectangular aspect ratio multiplier circuit of the first transformed argument and the second value generated by evaluating the polynomial approximation using a floating point multiplication operation by inputting into the rectangular aspect ratio multiplier circuit electrical signals representing the first transformed argument and the second value.
0. 20. The method of
receiving as inputs electrical signals representing a plurality of values of primitive operations required for evaluation of the polynomial approximation; and
computing electrical signals representing a plurality of values of primitive operations required for evaluation of the polynomial approximation;
wherein the electrical signals representing at least one of the input and computed values is of a greater precision than said result.
0. 21. The method of
0. 22. The method of
0. 23. The method of
0. 24. The method of
0. 25. The method of
0. 26. The method of
0. 27. The method of
0. 28. The method of
0. 29. The method of
0. 35. The numeric processing system of
0. 36. The numeric processing system of
0. 37. The numeric processing system of
0. 38. The numeric processing system of
0. 40. The numeric processing system of
0. 41. The numeric processing system of
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This invention relates in general to the field of performing mathematical functions using electronic devices. More specifically, the present invention relates to a method and apparatus for performing mathematical functions using polynomial approximations in a system comprising a rectangular aspect ratio multiplier circuit.
Computation of elementary and transcendental mathematical functions such as sine, cosine, logarithms and others is a required function in modern computing systems. These functions may be evaluated for any point in their domain by any of several methods. Best known among these methods are the Taylor series expansion, the Chebyshev series expansion, the CORDIC method and derivatives, Brigg's method for logarithms, Newton's method and polynomial approximation. These methods vary principally in the primitive operations they require, such as addition,:addition,
This generation of leading ones can present a problem when trying to truncate leading
Thus, the entire string of obeying
where,
The equation is evaluated with two passes through the multiplier core 58. The divisor is loaded into the D-latch 48. The seed value of the reciprocal is loaded into the C-latch 44. When the value in the D-latch 18 is converted to signed digit notation in converter 64, it is negated. The constant generator 138 adds in a constant two into the level three adder 136. The product of the first pass is equal to (2−yy′). The most significant seventy-five bits of this product are stored in the feedback latch 82. The second pass through the multiplier core 58 multiplies the result of the first pass times the starting approximation of the reciprocal.
Because the multiplier 58 can accept the MULTIPLICAND input in signed digit format, a conversion to non-redundant format is not required, and the two passes through the multiplier core 58 can be on back to back clock cycles. On the second pass through multiplier core
where,
Each iteration of the above equations are evaluated with three passes through the multiplier core 58 and two iterations are required such that the value of the reciprocal may be generated with six passes through multiplier core 58. Prior to the first pass, a seed value for the reciprocal is loaded from a look-up table (not shown) through system bus 42 into the C-latch 44. The operand is loaded initially in the D-latch 48.
For the first pass of the first iteration, the MUX 66 selects the operand stored in D-latch 48 and inputs it through the MULTIPLICAND input into multiplier core 58. The reciprocal seed value is input from the C-latch 44 through the MUX 62 into the MULTIPLIER input of multiplier core 58. Multiplier core 58 then forms the product of the seed value and the operand corresponding to y•y′or y/2•y′ in the above equations. This product is then loaded into feedback latch
where z=(x′)2 is the square of the reduced argument x′.
Here P(z) is the polynomial
P(z)=a0+a1*z+z2*z2+a3*Z3+a4*z4+a5*z5+z6*z6+z7*z7
of degree 7 whose coefficients, in decimal form, are presented in FIG. 8. For arguments x′ whose magnitude is less than π/4, the magnitude of the relative error in approximating sin(x′) by x′*P(z) is less than 10(−20.7). Once the coefficients of P(z) are determined, they are taken from constant store 28 via system busses 16 and 42 and input as necessary into multiplier circuit 40 shown in
The determination of the value of the approximation P(z) using Horner's rule proceeds as follows. Horner's rule for the evaluation of P(z) requires the following seven iterations:
In summary, the present invention provides an improved method for computation of approximations to mathematical functions. The method comprises three main steps: (1) reducing the magnitude of a starting argument x to a range where polynomial base approximations are more effective; (2) computing the result using this reduced argument and the special facilities of the proposed circuit; and (3) transformation of the computed result to a value which approximates the value of the mathematical function being approximated.
An important technical advantage of the method of the present invention inheres in its use of a rectangular aspect ratio multiplier with an associated adder port and associated circuitry to perform rapid and accurate multiplication, division, and square root operations. The additional adder port feature enables the system to perform a multiplication and an addition in one iteration. These features enable the system to evaluate a polynomial of degree N using Horner's rule in N iterations and to perform the required multiplication operations more quickly by utilizing the leading zeros in one of the numbers to be multiplied.
Another advantageous feature of the invention is its use of relatively few constants to achieve a given level of accuracy. This feature allows the system to allocate less space to the storage of constants in the constant store.
The present method also overcomes the objections of nonmonotonic behavior frequently made regarding the use of polynomial based methods of function approximation. The nonmonotonic behavior of polynomial based approximations can be eliminated by performing each of the add, multiply, divide, and square root operations to a precision sufficiently greater than that required by the precision of the final answer.
A further time and space saving feature is the scaling of constants and operands through transformations which may be performed quickly using the rectangular aspect ratio multiplier. This scaling allows for a less complex multiplier to be used in the multiplication of constants and operands with no associated loss of accuracy. This scaling also allows for the answer of a full by full multiply to be performed as an equivalent short by full multiply which requires fewer clock cycles.
Although the method of the present invention has been described in connection with a particular circuit embodiment, it should be understood that the method of function approximation of the present invention is equally applicable to a large number of multipliers with widely varying aspect ratios and widely varying numbers of adder ports using numbers using either signed digit redundant or non-redundant formats. The disclosure of the particular circuit described herein is for the purposes of teaching the present invention and should not be construed to limit the scope of the present invention which is solely defined by the scope and spirit of the appended claims.
Brightman, Thomas B., Briggs, Willard S., Ferguson, Warren E.
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| Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
| Feb 21 1991 | BRIGHTMAN, THOMAS B | Cyrix Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 007119 | /0298 | |
| Mar 01 1991 | FERGUSON, WARREN E , JR | Cyrix Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 007119 | /0298 | |
| Mar 01 1991 | BRIGGS, WILLARD STUART | Cyrix Corporation | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 007119 | /0298 | |
| Aug 19 1993 | VIA-Cyrix, Inc. | (assignment on the face of the patent) | / | |||
| Sep 23 1994 | Cyrix Corporation | FIRST INTERSTATE BANK OF TEXAS, N A , AS AGENT | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 007152 | /0313 | |
| Jun 19 1995 | CYRIX, CORPORATION | IBM CREDIT CORPORATION | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 007757 | /0320 | |
| Mar 09 1998 | Cyrix Corporation | National Semiconductor Corp | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 009089 | /0068 | |
| Sep 08 1999 | National Semiconductor Corporation | VIA-Cyrix, Inc | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 020794 | /0633 |
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