Low friction polish-stop stratum for endpointing chemical-mechanical planarization processing of semiconductor wafers

Abstract

The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application Methods in accordance with the invention are accordingly useful for planarizing a wafer using polishing pads having a Rockwell hardness between approximately 75 and 90. Therefore, even when hard polishing pads are used, a low friction stratum 180 made from graphitic carbon stops the CMP process at a desired endpoint.

Compared to typical DLC polish-stop layers, the graphitic carbon stratum of the present invention has a much lower polishing rate with hard polishing pads. The graphitic carbon stratum of the invention is essentially free of carbon-hydrogen bonds and has an SP-3 lattice structure to allow the layers of carbon atoms in the stratum to slide with respect to each other. Conversely, DLC has an SP-4 lattice structure and an important aspect of most DLC polish-stop layers is the incorporation of hydrogen into the DLC material, both of which act to restrict the layers of carbon atoms in the polish-stop layer from moving with respect to each other. DLC, in fact, is usually deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition processes that use a carrier gas containing hydrogen that enhances the incorporation of hydrogen into the DLC material. As stated above, however, the present invention preferably deposits the graphitic carbon stratum by plasma vapor deposition from a carbon target. Thus, by providing a graphitic carbon stratum that is essentially free of carbon-hydrogen bons and has an SP-3 lattice structure, the present invention uses a low friction layer instead of a hard layer to reduce the polishing rate with hard pads.

Another advantage of the present invention is that a low friction stratum made from graphitic carbon enhances the throughput of the CMP process because only a thin layer of graphitic carbon is required to provide an effective polish-stop layer. Unlike the DLC, a graphite carbon stratum with a thickness of only 100 Å provides an effective polish-stop layer for both hard and soft polishing pads. The throughput of the CMP process is accordingly enhanced because it takes less time to deposit and clean a thin stratum of graphitic carbon than a thicker layer of DLC.

Still another advantage of the present invention is that the graphitic carbon stratum may be deposited on the wafer at a low temperature that does not damage or alter other electrical components. Many electrical components of integrated circuits are formed in silicon, which anneals at approximately 450° C. A low friction stratum 180 made from graphitic carbon is preferably deposited at a temperature of between approximately 50° C. and 150° C. Therefore, the deposition temperature of a low friction stratum 180 made from graphitic carbon does not damage or alter the other electrical components on the wafer.

An additional advantage of the present invention is that it enhances the throughput of the CMP process because a low friction stratum 180 made from graphitic carbon effectively stops further planarization even when higher down forces are used to increase the polishing rate. Higher down forces on the order of 7-9 psi generally reduce the effectiveness of polish-stop layers. In the case of a low friction stratum 180 made from graphitic carbon, however, the above-listed tests were performed with a down force of approximately 7.0-7.5 psi. Therefore, CMP processes that use higher down forces to achieve higher polishing rates may be effectively end-pointed with a low friction stratum 180 made from graphitic carbon.

FIGS. 5A-5D illustrate a process for making an interconnect wafer 150(b) in accordance with the invention. Referring to FIG. 5A, the insulation layer 70 is deposited over the substrate 60 and the device feature 62. The low friction stratum 180 is deposited on the insulative layer 70, and a resist layer 64 is deposited on the low friction stratum 180 so that a hole 68 in the resist 64 is positioned over the device feature 62. Referring to FIG. 5B, a via 74 is cut through the graphitic stratum 180 and etched through the insulative layer 70. After the via 74 is formed, the resist layer 64 is removed from the polish-stop surface 181 of the low friction stratum 180. Referring to FIG. 5C, an upper layer 190 of conductive material is deposited over the low friction stratum 180 and into the via 74. The portion of the upper layer 190 in the via 74 forms an interconnect 192 coupled to the device feature 62. FIG. 5D illustrates the interconnect water 150(b) after the upper layer 190 has been planarized with a CMP process. As discussed above with respect to FIGS. 3 and 4, the polish-stop surface 181 of the low friction stratum 180 effectively stops further planarization even when hard polishing pads, aggressive slurries, and high down forces are used in the CMP process.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.

Claims

1. A semiconductor wafer for use in a chemical-mechanical planarization process, comprising:

a substrate having a device feature formed on the substrate;

a graphitic carbon stratum positioned over the substrate, the stratum having a polish-stop surface positioned at a level substantially proximate to a desired end-point of the chemical-mechanical planarization process, and the stratum having a thickness between approximately 100 Å and 600 Å; and

an upper layer deposited on the stratum, the upper layer having a higher polishing rate than that of the stratum, wherein the stratum substantially resists chemical-mechanical planarization with a polishing pad in a slurry to substantially stop the planarization process at the desired end-point.

2. The wafer of claim 1, further comprising:

an insulative layer between the stratum and the substrate; and

a via through the stratum and the insulative layer wherein the upper layer is made from a conductive material to form an interconnect in the via.

3. The wafer of claim 1 wherein the stratum has a thickness between approximately 300 Å and 500 Å.

4. The wafer of claim 2 wherein the device feature is coupled to the interconnect.

5. The wafer of claim 2 wherein the insulative layer comprises silicon dioxide.

6. The wafer of claim 2 wherein the insulative layer comprises borophosphate silicon glass.

7. The wafer of claim 3 wherein the stratum is approximately 100 Å to 500 Å thick.

8. The wafer of claim 3 wherein the interconnect comprises tungsten.

9. The wafer of claim 3 wherein the interconnect comprises aluminum.

10. The wafer of claim 3 wherein the interconnect comprises polysilicon.

11. Title The wafer of claim 1, further comprising a device feature under the stratum, and wherein the upper layer is made from an insulative material.

12. A microelectronic-device substrate assembly, comprising:

a substrate member;

a graphitic carbon stratum carbon over at least a portion of the substrate, the graphitic carbon stratum having a thickness between approximately 100 Å and 600 Å and a first polishing rate in planarization ; and

an upper layer over the graphitic carbon stratum, the upper layer having a second polishing rate less than the first polishing rate of the graphitic carbon stratum.

13. The substrate assembly of claim 12, further comprising:

an insulative layer between the graphitic stratum and the substrate; and

a via through the graphitic carbon stratum and the insulative layer, wherein the upper layer comprises a conductive material to form an interconnect in the via.

14. The substrate assembly of claim 12 wherein the graphitic carbon stratum has a thickness between approximately 100 Å and 500 Å.

15. The substrate assembly of claim 12 further comprising a device feature formed on the substrate, and wherein the substrate assembly further comprises:

an insulative layer between the graphitic stratum and the substrate; and

a via through the graphitic carbon stratum and the insulative layer, the via being positioned over the device feature, and wherein the upper layer comprises a conductive material to form an interconnect in the via coupled to the device feature.

16. The substrate assembly of claim 15 wherein the insulative layer comprises silicon dioxide.

17. The substrate assembly of claim 15 wherein the insulative layer comprises borophosphate silicon glass.

18. The substrate assembly of claim 12 wherein the graphitic carbon stratum is approximately 100 Å and 300 Å thick.

19. The substrate assembly of claim 12 further comprising a device feature formed on the substrate, and wherein the substrate assembly further comprises:

an insulative layer between the graphitic stratum and the substrate; and

a via through the graphitic carbon stratum and the insulative layer, the via being positioned over the device feature, and wherein the upper layer comprises tungsten to form a tungsten interconnect in the via coupled to the device feature.

20. The substrate assembly of claim 12 further comprising a device feature formed on the substrate, and wherein the substrate assembly further comprises:

an insulative layer between the graphitic stratum and the substrate; and

a via through the graphitic carbon stratum and the insulative layer, the via being positioned over the device feature, and wherein the upper layer comprises aluminum to form an aluminum interconnect in the via coupled to the device feature.

21. The substrate assembly of claim 12 further comprising a device feature formed on the substrate, and wherein the substrate assembly further comprises:

an insulative layer between the graphitic stratum and the substrate; and

a via through the graphitic carbon stratum and the insulative layer, the via being positioned over the device feature, and wherein the upper layer comprises polysilicon to form a polysilicon interconnected in the via coupled to the device feature.