An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked container capacitor. The present invention develops the container capacitor by etching an opening (or contact opening) into a low etch rate oxide. The contact opening is used as a form for deposited polysilicon that conforms to the sides of the opening walls. Within the thin poly lining of the oxide container a high etch-rate oxide, such as ozone TEOS, is deposited over the entire structure thereby bridging across the top of the oxide container. The high etch-rate oxide is planarized back to the thin poly and the resulting exposed poly is then removed to separate neighboring containers. The two oxides, having different etch rates, are then etched thereby leaving a free-standing poly container cell with 100% (or all) of the higher etch rate oxide removed and a pre-determined oxide surrounding the container still intact.
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0. 61. A process for fabricating a capacitor on a substrate, said process comprising the steps of:
providing a first insulating layer on said substrate, said first insulating layer having an opening therein forming a container;
forming a generally conformal first conductive layer, over said first insulating layer and in said container;
forming a second insulating layer over the entire said first conductive layer; and
removing a portion of said second insulating layer overlying an uppermost portion of portion of said first conductive layer through use of chemical mechanical planarization until said uppermost portion of said first conductive layer is exposed.
0. 66. A process for fabricating a dram containing storage capacitor on a silicon substrate having an existing topography including active areas, word lines and digit lines, said process comprising the steps of:
providing a first insulating layer having a first etch rate, over said existing topography;
forming an opening into said first insulating layer, said opening thereby forming a container;
forming a conformal first conductive layer over said first insulating layer and said container, thereby lining said container;
forming a second insulating layer, having a second etch rate, over the entire said first conductive layer; and
removing said second insulating layer through use of chemical mechanical planarization until an uppermost portion of said conductive layer is exposed.
0. 71. A process for fabricating a dram container storage capacitor on a silicon substrate having an existing topography including active areas, word lines and digit lines, said process comprising the steps of:
providing a first insulating layer, having a first etch rate, over said existing topography;
forming an opening into said first insulating layer, said opening thereby forming a container;
forming a conformal first conductive layer over said first insulating layer and said container, thereby lining said container;
forming a second insulating layer, having a second etch rate, over the entire said first conductive layer; and
removing said second insulating layer through use of chemical mechanical planarization until an uppermost portion of said first conductive layer is exposed;
removing at least a portion of said upper portion of said first conductive layer until said first insulating layer is exposed, thereby forming a conductive container having inner and outer walls.
0. 1. A process for fabricating a uniform and repeatable conductive container structure on a starting substrate's existing topography, said process comprising the steps of:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive upper layer until underlying said first insulating layer is exposed thereby separating said first conductive layer into individual said conductive containers having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said conductive container and said first insulating layer is partially removed thereby exposing an upper portion of said outer walls of said conductive container, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive said exposed walls and inner bottom portion of said container and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive said third insulating layer.
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0. 11. A process for fabricating a uniform and repeatable conductive container structure on a starting substrate's existing topography, said process comprising the steps of:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer until upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive upper layer via chemical mechanical planarization until underlying said first insulating layer is exposed thereby separating said first conductive layer into individual said conductive containers having inner and outer walls;
g) removing said first and second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said conductive container and said first insulating layer is partially removed thereby exposing an upper portion of said outer walls of said conductive container, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive said exposed walls and inner bottom portion of said container and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive said third insulating layer.
0. 12. A process as recited in
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0. 21. A process for fabricating a uniform and repeatable conductive container structure on a starting substrate's existing topography, said process comprising the steps of:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive upper layer via chemical mechanical planarization until underlying said first insulating layer is exposed thereby separating said first conductive layer into individual said conductive containers having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said conductive container and said first insulating layer is partially removed thereby exposing an upper portion of said outer walls of said conductive container, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive said exposed walls and inner bottom portion of said container and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive said third insulating layer.
0. 22. A process as recited in
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0. 30. A process as recited in
0. 31. A process for fabricating a dram container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive upper layer until underlying said first insulating layer is exposed thereby separating said first conductive layer into individual said container storage capacitors having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said container storage capacitor and said first insulating layer is partially removed thereby exposing an upper portion of said outer walls of said container storage capacitor, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive said exposed walls and inner bottom portion of said capacitor and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive said third insulating layer.
0. 32. A process as recited in
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0. 40. A process as recited in
0. 41. A process for fabricating a dram container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form,
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer until upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive upper layer via chemical mechanical planarization until underlying said first insulating layer is exposed thereby separating said first conductive layer into individual said container storage capacitors having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said container storage capacitor and said first insulating layer is partially removed thereby exposing an upper portion of said outer walls of said container storage capacitor, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive said exposed walls and inner bottom portion of said capacitor and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive said third insulating layer.
0. 42. A process as recited in
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0. 50. A process as recited in
0. 51. A process for fabricating a dram container storage capacitor on a silicon substrate having active areas, word lines and digit lines, said process comprising the following sequence of steps:
a) forming a blanketing first insulating layer, having a first etch rate, over said existing topography;
b) patterning and etching an opening into said first insulating layer, said opening thereby forming a container form;
c) forming a conformal first conductive layer superjacent said first insulating layer and said container form thereby lining said container form;
d) forming a blanketing second insulating layer, having a second etch rate, superjacent said first conductive layer;
e) removing said second insulating layer via chemical mechanical planarization until upper portion of said first conductive layer is exposed;
f) removing said exposed first conductive upper layer via chemical mechanical planarization until underlying said first insulating layer is exposed thereby separating said first conductive layer into individual said container storage capacitors having inner and outer walls;
g) removing said first and said second insulating layers such that said second insulating layer is completely removed thereby exposing the entire inner walls of said container storage capacitor and said first insulating layer is partially removed thereby exposing an upper portion of said outer walls of said container storage capacitor, wherein the partially remaining first insulating layer provides insulation between said underlying substrate topography and subsequently formed layers;
h) forming a third insulating layer superjacent and coextensive said exposed walls and inner bottom portion of said capacitor and said partially remaining first insulating layer; and
i) forming a second conductive layer superjacent and coextensive said third insulating layer.
0. 52. A process as recited in
0. 53. A process as recited in
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0. 55. A process as recited in
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0. 62. The process of
0. 63. The process of
0. 64. The process of
0. 65. The method of
0. 67. The process of
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0. 70. The process of
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of , thereby forming individual containers 51 residing in contact openings 22 and exposing underlying oxide 21. The areas of poly 23 that are removed may be accomplished by performing a poly etch selective to oxide, which could be a timed wet etch or an optimized CMP poly etch. A very significant advantage of this process flow when a CMP etch step is utilized is that the inside of the future container 51 is protected from ‘slurry’ contamination that is inherent in the CMP step which proves difficult to remove in high aspect ratio storage containers (0.5μ inside diameter by 1.5μ high).
Referring now to
Referring now to
It is to be understood that although the present invention has been described with reference to a preferred embodiment, various modifications, known to those skilled in the art, may be made to the structures and process steps presented herein without departing from the invention as recited in the several claims appended hereto.
Walker, Michael A., Dennison, Charles H.
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