Photoelectric converter, its driving method, and system including the photoelectric converter

Abstract

A photoelectric converter of a high signal-to-noise ratio, low cost, high productivity and stable characteristics and a system including the above photoelectric converter. The photoelectric converter includes a photoelectric converting portion in which a first electrode layer, an insulating layer for inhibiting carriers from transferring, a photoelectric converting semiconductor layer of a non-single-crystal type, an injection blocking layer for inhibiting a first type of carriers from being injected into the semiconductor layer and a second electrode layer are laminated in this order on an insulating substrate.

Description

This application is a

Accordingly, V_o(refresh) can be altered at will depending on a size of the capacitor C_x to be inserted, which makes it possible to design more freely.

As apparent from the above description, signal charges can be stored in a condition that the positive inrush current is almost zero by applying the positive potential to the electrode G for the photoelectric converting section via the capacitor 1,200.

In this embodiment, a second electrode layer is not specifically transparent. Further, an n-type injection blocking layer is used between an i-layer and the second electrode layer and carriers inhibited from being injected are holes. Therefore, assuming that q is a charge for a carrier inhibited from being injected, q>0 is satisfied in this condition.

In the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result can be achieved as for the above embodiment by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.

[13th embodiment]

Using FIGS. 35 to 37, the 13th embodiment of this invention is described below.

FIG. 35 is a schematic equivalent circuit diagram illustrating the photoelectric converter of the 13th embodiment of the present invention. The explanation is made by giving an example of a photoelectric converting element array including nine photoelectric converting elements being one-dimensionally arranged. FIG. 36 is a typical plan view illustrating a photoelectric converting section including a plurality of pixels in a longitudinal direction, a refresh capacitor section, a refresh-TFT section, a reset-TFT section, and a line section for a single pixel. FIG. 37 is a sectional view of a single pixel. FIG. 37 is typically drawn for understanding and the position of the line section does not match the position in FIG. 36 completely. Additionally, the reset-TFT section 1,400 is not shown. The same reference numerals in FIGS. 35 to 37 indicate the same corresponding parts as for FIG. 33.

In FIG. 36, the photoelectric converting section 100 includes a lower electrode 2 which also serves as a light shielding film against light from a substrate side. Light from the substrate is reflected on a surface of an original copy (not shown) located perpendicularly upward against the drawing through a light window 17, and the reflected light impinges on the photoelectric converting section 100. Photocurrent caused by carriers generated at this point is stored in equivalent capacitive components of the photoelectric converting element 100 and other stray capacitance. The stored charges are transferred to a matrix line section 1,500 by the transfer-TFT 1,300 and read as a voltage by a signal processing section (not shown).

Using FIG. 37, a layer structure of the sections is roughly described below.

In FIG. 37, the photoelectric converting section 100, the refresh capacitor 1,200, the transfer-TFT 1,300, and the line section 1,500 have an identical layer structure consisting of five layers; a first electrode layer including 2-1, 2-2, 2-3, and 2-4, an insulating layer 70, an i-layer 4, an n-layer 5, and a second electrode layer including 6-1, 6-2, 6-3, and 6-4. The second electrode layer is not specifically transparent.

Since the photoelectric converting section 100 in this embodiment has also the same structure as for the first embodiment, an n-type injection blocking layer is used between the i-layer 4 and the second electrode layer 6-1 and carriers inhibited from being injected are holes. Therefore, assuming that q is a charge for a carrier inhibited from being injected, q>0 is satisfied in this condition, too.

Then, how to drive the photoelectric converter of this embodiment is described below by using FIG. 35.

In FIG. 35, photoelectric converting elements S1 to S9 constitute a photoelectric converting element array consisting of three blocks each of which is composed of three photoelectric converting elements. This configuration is also used for refresh capacitors C1 to C9 each correspondingly coupled to the photoelectric converting elements S1 to S9, TFTs R1 to R9 for initializing potential of the electrode G for the photoelectric converting elements S1 to S9, and TFTs T1 to T9 for transferring signal charges.

An individual electrode having an identical order in each block of the photoelectric converting elements S1 to S9 is connected to one of common lines 1,102 to 1,104 via the transfer-TFTs T1 to T9. More specifically, the transfer-TFTs T1, T4, and T7 which belong to a first group of each block are coupled to the common line 1,102, the transfer-TFTs T2, T5, and T8 which belong to a second group of each block are to the common line 1,103, and then the transfer-TFTs T3, T6, and T9 which belong to a third group of each block are to the common line 1,104. The common lines 1,102 to 1,104 are coupled to an amplifier 1,126 via switching transistors T100 to T120, respectively.

Further in FIG. 35, the common lines 1,102 to 1,104 are grounded via common capacitors C100 to C120, respectively and also grounded via switching transistors CT1 to CT3. Each gate electrode for the switching transistors CT1 to CT3 is coupled via each common line to discharge remaining charges of the common lines 1,102 to 1,104 to GND for potential initialization by being turned on at the same timing as for the Pa pulse in FIG. 34.

In this embodiment, a refresh means includes the capacitors C1 to C9, a shift register 1,108, and a power supply 114, and a signal detecting section includes a detecting means enclosed by a dashed line in FIG. 35, the TFTs T1 to T9, and a shift register 1,106.

Next, the operation of this embodiment is described in time series below.

If signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored from the power supply 114 into refresh capacitors C1 to C9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance depending on its intensity. Then, when a high level is output from a first parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the refresh capacitors C1 to C3, the capacitive components, and the stray capacitance are transferred to common capacitors C100 to C120. After that, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.

After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 and it increases potential across the refresh capacitors C1 to C3. Then, the holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403.

Next, a high level is output from a first parallel terminal of a shift register 1,109 and the reset-TFTs R1 to R3 are turned on, which initializes potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the refresh capacitors C4 to C6, the stray capacitance, and the sensor equivalent capacitive components in the second block to the common capacitors C100 to C120. After that, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential readout of light signals of the second block stored in the common capacitors C100 to C120.

Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.

Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.

As explained in this embodiment by using FIG. 37, the photoelectric converting elements, the refresh capacitors, the transfer-TFTs, the reset-TFTs, and the matrix signal line section have an identical layer structure consisting of five layers including the first electrode layer, the insulating layer, the i-layer, the n-layer, and the second electrode layer, but all the elements do not need to have the same layer structure necessarily. It is only required that at least the photoelectric converting elements have this (MIS) structure and that other elements each have a layer structure which allows it to serve as each element. If they have the identical layer structure, however, it is more effective to improve a yielding ratio and to lower the cost.

In addition, in the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the first embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.

Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.

As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the TFTs, and the matrix signal line section in this embodiment, the layers can be formed in an identical process at a time, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost.

As apparent from the above description, the photoelectric converting elements are not limited to those shown by the embodiment. More specifically, it is only required that there are the first electrode layer, the insulating layer for blocking the movement of holes and electrons, the photoelectric converting semiconductor layer, and the second electrode layer, in addition to the injection blocking layer for blocking injection of holes into the photoelectric converting semiconductor layer between the second electrode layer and the photoelectric converting semiconductor layer. In addition, the photoelectric converting semiconductor layer only needs to have a photoelectric converting function of generating electron-hole pairs due to incident light. As for a layer structure, not only a single layer structure, but a multiple layer structure can be used and its characteristics can be altered repeatedly.

In the same manner, the TFTs each only need to have a gate electrode, a gate insulating layer, a semiconductor layer in which channels can be formed, an ohmic contact layer, and a main electrode. For example, the ohmic contact layer can be a p-layer. If it is so, a hole can be used as a carrier by reversing a control voltage of the gate electrode.

Additionally in the same manner, the capacitors each only need to have a lower electrode layer, a middle layer including an insulating layer, and an upper electrode layer, for example, they need not be especially separated from the photoelectric converting elements or the TFTs and it is possible to have a configuration in which they also serve as the electrode section for the photoelectric converting elements.

Further, the insulating substrate need not be always an insulator, and it can be a conductor or a semiconductor on which an insulator is laid.

In addition, since the photoelectric converting element itself has a function of accumulating charges, it is possible to obtain an integrated value of light information for a certain period without specific capacitors.

[14th embodiment]

The photoelectric converter illustrated in the schematic equivalent circuit diagram in FIG. 33 described in the 13th embodiment can be driven at a timing illustrated in a timing diagram in FIG. 38.

Now referring to FIG. 38, the operation of the photoelectric converter of this embodiment is described below.

In the refresh operation of photoelectric converting elements, the potential of the electrode G is increased in this configuration only when a Pc high-level pulse is generated by supplying the refresh high-level pulse Pc to an electrode opposite to the electrode G of the capacitor 1,200 as shown in FIG. 38. Accordingly, holes remaining in the photoelectric converting section 100 are swept out to the electrode D and the photoelectric converting section 100 is refreshed.

Afterward, the potential of the electrode G opposite to the capacitor 1,200 also falls instantly at the same time when the Pc refresh pulse falls, therefore, the sweep-out of the holes remaining in the photoelectric converting section 100 to the electrode D is completed to enter a photoelectric converting operation. Practically, since positive inrush current shown in FIG. 38 occurs in the photoelectric converting section 100 and then gradually attenuates, the photoelectric converting operation starts after the inrush current flows.

Next, the TFT 1,400 is turned off by a Pd low potential (also referred to as “low level” hereinafter) pulse and the electrode G is opened for a direct current. Practically, however, the potential is kept by a capacitance of the capacitor 1,200 and equivalent capacitive components of the photoelectric converting section 100 or their stray capacitance. At this point, if a light signal of the photoelectric converting section 100 is incident, the corresponding current flows out of the electrode G to increase the potential of the electrode G.

In other words, the incident light information is stored in a capacitance of the electrode G as electric charges. After a certain storing time, the transfer-TFT 1,300 is shifted from the off state to an on state by a Pb high-level pulse and the stored charges flow to the capacitor 1,124. The quantity of the charges is proportional to an integrated value of the current flowing out of the photoelectric converting section 100; in other words, it is detected by the detecting section through the operational amplifier 1,126 as a total quantity of the incident light. It is desirable that the potential of the capacitor 1,124 is initialized to GND potential by a Pa high-level pulse from the TFT 1,125 before this transfer operation.

When the transfer-TFT 1,300 becomes off, the refresh-TFT 1,700 is set on by a Pc high-level pulse, and then the sequential operation is repeated after that. In this embodiment, the refresh means includes the capacitor 1,200, the high-level pulse Pc supplying means, and a power supply 114, and the signal detecting section includes the detecting means enclosed by the dashed line in FIG. 33, the TFT 1,300, and the high-level pulse Pb supplying means.

In this embodiment, positive inrush current (which does not have a condition indicated by a solid line on 1s in FIG. 38) is inhibited from occurring when signal charges are stored by supplying positive potential which is smaller than a fixed potential to the electrode G for the photoelectric converting elements via the capacitor 1,200 in the refresh operation (If the potential is greater than the fixed potential, the current shows a condition indicated by a dashed line).

As a method of reducing the positive inrush current, the time for the Pd initialization pulse can be extended. There, however, is a limit to the extended time, the time extension also elongates the entire signal read time of the apparatus, which causes speed-down or lowering performance of the apparatus.

Accordingly, if the refresh operation is performed by the capacitor and timing is set appropriately in this embodiment, for example, if the photoelectric converter is operated at a speed of approx. 100 μs from the Pc pulse fall to the Pd G electrode potential initialization pulse fall, the inrush current stored as V_o is lowered to substantially zero as shown in FIG. 38. Accordingly, almost all the electric charges started to be stored from the Pd pulse fall are charges generated by signal light incident on the photoelectric converting section 100, which makes it possible to obtain information with a high signal-to-noise ratio by reading its signal voltage. In addition, calculation is made to obtain potential V_o(refresh) of the electrode G when the Pc high-level pulse (V_res) is supplied to it. Supposing that C_o is a sum of stray capacitance coupled to the electrode G and equivalent capacitive components of the photoelectric converting section 100 and C_x is a capacitance of the capacitor 1,200, V_o(refresh) can be represented by the following expression:
V_o(refresh)={C_x/(C_o+C_x)}×V_res

Accordingly, V_o(refresh) can be altered at will depending on a size of the capacitor C_x to be inserted, which makes it possible to design more freely.

As apparent from the above description, signal charges can be stored in a condition that the positive inrush current is almost zero by applying the positive potential to the electrode G for the photoelectric converting elements via the capacitor 1,200. Furthermore, it is also possible to reduce a decay time by adjusting the potential applied to the electrode G via the capacitor 1,200 to lower a value of the positive inrush current.

The potential of the electrode D and the electrode G for the photoelectric converting elements in the refresh operation is described in detail by using FIGS. 24 and 27A to 27C in the ninth embodiment, therefore, their explanation is omitted here.

In this embodiment, superior characteristics can be obtained by driving the photoelectric converter under the conditions below.

In the refresh operation of the photoelectric converting section 100, the potential V_rG of the power supply 1,115 for applying positive potential to the electrode G is lower than the potential V_D of the power supply 114 for applying positive potential to the electrode D. More specifically, since the photoelectric converting section 100 has a flat-band voltage (V_FB) to be applied to the electrode G to flat an energy band of the i-layer, practically the photoelectric converter is driven in a condition of V_rG<V_D−V_FB.

As its concrete operation is described in detail in the 10th embodiment by using FIGS. 29 and 30, the explanation is omitted here.

In this embodiment, there are very little electrons in defects on the interface between the i-layer 4 and the insulating layer 70; therefore, it does not take a long time for injection or ejection of electrons, which leads to a considerable reduction of inrush current to be noise elements as a result.

Supposing that C_x is a capacitance of the capacitor 1,200, C_o is a sum of stray capacitance coupled to the electrode G and equivalent capacitive components of the photoelectric converting section 100, and (V_res) is a Pc high-level pulse, the G electrode potential at the refresh operation V_rG can be represented by the following expression:
V_rG=V_o(refresh)={C_x/(C_o+C_x)}×V_res
If the photoelectric converter is driven under a condition that a value of {C_x/(C_o+C_x)}×V_resis smaller than V_D−V_FB, the above effects can be obtained and it is possible to reduce the accumulated inrush current further in comparison with V_o which can be obtained under a condition of V_rG=V_o(refresh)≧(V_D−V_FB) shown in FIG. 38.

In this embodiment, the second electrode layer is not specifically transparent. Further, an n-type injection blocking layer is used between the i-layer and the second electrode layer in the photoelectric converting section 100 and carriers inhibited from being injected are holes. Therefore, assuming that q is an electric charge for a carrier inhibited from being injected, q>0 is satisfied in this condition. In the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result can be achieved as for the above embodiment by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.

[15th embodiment]

By using the photoelectric converter described in the 13th embodiment, an example of another driving method is described below.

Now the operation of this embodiment will be explained in time series.

If signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored in refresh capacitors C1 to C9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance from the power supply 114 depending on its intensity. Then, when a high level is output from a first parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the refresh capacitors C1 to C3, the capacitive components, and the stray capacitance are transferred to common capacitors C100 to C120. After that, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.

After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 and it increases potential across the refresh capacitors C1 to C3. For the potential of the electrode D and the electrode G for the photoelectric converting elements S1 to S3 at this point, the conditions described in the first embodiment are applied. In other words, supposing that V_D1 to V_D3, V_rG1 to V_rG3, and V_FB1 to V_FB3 are the potential of the electrode D, the potential of the electrode G, and the flat-band voltage for the photoelectric converting elements at the refresh operation, respectively, the following expressions are satisfied:
V_rG1<V_D1−V_FB2, V_rG2<V_D2−V_FB2, V_rG3<V_D3−V_FB3
Then, the holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403.

Next, a high level is output from a first parallel terminal of shift register 1,109 and the reset-TFTs R1 to R3 are turned on, which initializes the potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of the potential of the common capacitors C10 to C120. When the potential of the common capacitors C10 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the refresh capacitors C4 to C6, the stray capacitance, and the sensor equivalent capacitive components in the second block to the common capacitors C100 to C120. After that, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential read out of light signals of the second block stored in the common capacitors C100 to C120. Conditions of the potential of the both electrodes for the photoelectric converting elements S4 to S6 at the refresh operation are the same as for the photoelectric converting elements S1 to S3.

Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.

Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.

As explained in this embodiment by using FIG. 37, the photoelectric converting elements, the refresh capacitors, the transfer-TFTs, the reset-TFTs, and the matrix signal line section have an identical layer structure consisting of five layers including the first electrode layer, the insulating layer, the i-layer, the n-layer, and the second electrode layer, but all the elements do not need to have the same layer structure necessarily. It is only required that at least the photoelectric converting elements have this (MIS) structure and that other elements each have a layer structure which allows it to serve as each element. If they have the identical layer structure, however, it is more effective to improve an yielding ratio and to lower the cost.

In addition, in the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the first embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.

Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be used by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.

As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the TFTs, and the matrix signal line section in this embodiment, the layers can be formed in an identical process at a time, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost.

As apparent from the above description, the photoelectric converting elements are not limited to those shown by the embodiment. More specifically, it is only required that there are the first electrode layer, the insulating layer for blocking the movement of holes and electrons, the photoelectric converting semiconductor layer, and the second electrode layer, in addition to the injection blocking layer for blocking injection of holes into the photoelectric converting semiconductor layer between the second electrode layer and the photoelectric converting semiconductor layer. In addition, the photoelectric converting semiconductor layer only needs to have a photoelectric converting function of generating electron-hole pairs due to incident light. As for a layer structure, not only a single layer structure, but a multiple layer structure can be used and its characteristics can be altered repeatedly.

In the same manner, the TFTs each only need to have a gate electrode, a gate insulating layer, a semiconductor layer in which channels can be formed, an ohmic contact layer, and a main electrode. For example, the ohmic contact layer can be a p-layer. If it is so, a hole can be used as a carrier by reversing a control voltage of the gate electrode.

Additionally in the same manner, the capacitors each only need to have a lower electrode layer, a middle layer including an insulating layer, and an upper electrode layer, for example, they need not be especially separated from the photoelectric converting elements or the TFTs and it is possible to have a configuration in which they also serve as the electrode section for the photoelectric converting elements.

Further, the insulating substrate need not be always an insulator, and it can be a conductor or a semiconductor on which an insulator is laid.

In addition, since the photoelectric converting element itself has a function of accumulating charges, it is possible to obtain an integrated value of light information for a certain period without specific capacitors.

[16th embodiment]

FIG. 39 is a schematic equivalent circuit diagram of a photoelectric converter illustrating the 16th embodiment of the present invention. The explanation is made by giving an example of a photoelectric converting element array including nine photoelectric converting elements being one-dimensionally arranged. FIG. 40 is a timing diagram illustrating an operation of the equivalent circuit in FIG. 39.

As for a configuration of a photoelectric converting section, the configuration shown in FIGS. 36 and 37 can be applied.

Next, how to drive the photoelectric converter of this embodiment is explained by using FIGS. 39 and 40. In FIG. 39, photoelectric converting elements S1 to S9, refresh capacitors C1 to C9 coupled to each photoelectric converting elements S1 to S9, and TFTs R1 to R9 for initializing potential of an electrode G for the photoelectric converting elements S1 to S9 (also referred to as “G electrode reset-TFTs” hereinafter), and signal charge transfer-TFTs T1 to T9 each constitute an array consisting of three blocks each of which is composed of three elements.

An individual electrode having an identical order in each block of the photoelectric converting elements S1 to S9 is connected to one of common lines 1,102 to 1,104 via the transfer-TFTs T1 to T9. More specifically, the transfer-TFTs T1, T4, and T7 which belong to a first group of each block are coupled to the common line 1,102, the transfer-TFTs T2, T5, and T8 which belong to a second group of each block are to the common line 1,103, and then the transfer-TFTs T3, T6, and T9 which belong to a third group of each block are to the common line 1,104. The common lines 1,102 to 1,104 are coupled to an amplifier 1,126 via switching transistors T100 to T120, respectively.

Further in FIG. 39, the common lines 1,102 to 1,104 are grounded via common capacitors C100 to C120, respectively and also grounded via switching transistors CT1 to CT3.

Each gate electrode for the switching transistors CT1 to CT3 is coupled to a terminal 1,116 via each common line. Therefore, by setting the terminal 1,116 to a high level to turn on the switching transistors CT1 to CT3, remaining charges of the common lines 1,102 to 1,104 are discharged to GND for charge initialization. Further in FIG. 39, respective electrodes opposite to the electrode G for the refresh capacitors C1 to C3 in the first block are coupled via a common line to a common gate electrode for the transfer-TFTs T4 to T6 in the second block, and respective electrodes opposite to the electrode G for the refresh capacitors C4 to C6 in the second block via a common line to a common gate electrode for the transfer-TFTs T7 to T9 in the third block and to a common gate electrode for the reset-TFTs R1 to R3 in the first block. In the same manner, respective electrodes opposite to the electrode G for the refresh capacitors C7 to C9 in the third block are coupled via a common line to a common gate electrode for the reset-TFTs R4 to R6 in the second block. In this embodiment, the refresh means can include capacitors C1 to C9, a shift register 1,106, and the power supply 1,114, and a signal detecting section can include a detecting means enclosed by a dashed line in FIG. 39, the TFTs T1 to T9, and a shift register 1,106.

Next, the operation of this embodiment is described in time series below.

If signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored in refresh capacitors C1 to C9 and their stray capacitance depending on its intensity. Then, when a high level is output from a first parallel terminal of the shift register 1,106 [(a) in FIG. 40] and the transfer-TFTs T1 to T3 are turned on, the charges stored in the refresh capacitors C1 to C3 and the stray capacitance are transferred to common capacitors C100 to C120. After the transfer-TFTs T1 to T3 are turned on, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on [(j) to (1) in FIG. 40]. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126. Then, a terminal 1,116 is set to a high level [(m) in FIG. 40] and switching transistors CT1 to CT3 are turned on to initialize the potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, a high level is output from a second parallel terminal of the shift register 1,106 [(d) in FIG. 40] and it increases potential across the refresh capacitors C1 to C3. And then, holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403. Simultaneously with this, the transfer-TFTs T4 to T6 in the second block are turned on [(b) in FIG. 40] to transfer the signal charges stored in the refresh capacitors C4 to C6 and the stray in the second block to common capacitors C100 to C120. In the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107 [(j) to (1) in FIG. 40] and light signals of the second block stored in the common capacitors C100 to C120 are sequentially read out, then the potential of the common capacitors C100 to C120 is initialized by the switching transistors CT1 to CT3 [(m) in FIG. 40].

Next, after potential of the common electrode for the refresh capacitors C1 to C3 in the first block becomes a low level, a high level is output from a third parallel terminal of the shift register 1,106 [(g) in FIG. 40] and the G electrode reset-TFTs R1 to R3 are turned on to initialize the potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. At the same time, potential across the refresh capacitors C4 to C6 in the second block goes up [(e) in FIG. 40]. Further at this point, the transfer-TFTs T7 to T9 in the third block are also turned on [(c) in FIG. 40] and it starts a transfer of the signal charges stored in the refresh capacitors C7 to C9 in the third block and the stray capacitance to common capacitors C100 to C120. Then, in the same manner as for the first and second blocks, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 107 [(j) to (1) in FIG. 40] to read out light signals in the third block stored in the common capacitors C100 to C120 sequentially. After that, the potential of the common capacitors C100 to C120 is initialized by the switching transistors CT1 to CT3 [(m) in FIG. 40].

In the same manner, afterward, the G electrode reset-TFTs R4 to R6 in the second block are turned on by an output of a high level from a fourth parallel terminal of the shift register 1,106 [(h) in FIG. 40]. At the same time, potential across the refresh capacitors C7 to C9 in the third block goes up [(f) in FIG. 40]. After that, a high level is output from a fifth parallel terminal of the shift register 1,106, which turns on the G electrode reset-TFT R7 to R9 in the third block [(i) in FIG. 40].

Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.

The above explanation is given for the operation of the photoelectric converter including nine photoelectric converting elements divided to three blocks for a sensor array for a single line. For reading other lines, the charge transfer operation and the light signal read operation are performed repeatedly in the same manner. As explained in this embodiment by using FIG. 37, the photoelectric converting elements, the refresh capacitors, the TFTs, the matrix signal line section have an identical layer structure consisting of five layers including the first electrode layer, the insulating layer, the semiconductor layer, the n-layer, and the second electrode layer, but all the elements need not to have the same layer structure necessarily. It is only required that at least the photoelectric converting elements have this (MIS) structure and that other elements each have a layer structure which allows it to serve as each element. If they have the identical layer structure, however, it is more effective to improve an yielding ratio and to lower the cost.

In addition, in the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the above embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment.

Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.

As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the capacitors, the TFTs, and the matrix line section in this embodiment, the layers can be formed in an identical process at a time, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost. In addition, a conventionally used refresh power supply can be reduced, which is effective to produce a high signal-to-noise ratio and low cost photoelectric converter. Furthermore, a plurality of photoelectric converting elements are divided into blocks and two or more operations in other blocks (for example, a signal transfer operation, a sensor refresh operation, and a potential reset operation) can be driven simultaneously by an identical driving line, which makes it possible to achieve a further higher yielding ratio and lower cost photoelectric converter due to speedup of the operation and miniaturization of the apparatus.

[17th embodiment]

FIG. 41 is a single-bit schematic equivalent circuit diagram of a photoelectric converter of the 17th embodiment of the present invention.

Referring to FIG. 41, reference numeral 100 indicates a photoelectric converting section. A layer structure of the photoelectric converting section is the same as that described in FIG. 4A; accordingly, D is an electrode in a transparent electrode 6 side and G is an electrode in a lower electrode 1 side. Reference numerals 114, 1,115, and 1,700 indicate a power supply for applying a positive potential (V_D) to the electrode D, a power supply for applying positive potential (V_rG) to the electrode G in a refresh operation of the photoelectric converting section 100, and a refresh-TFT, respectively. It is desirable that the power supply 1,115 is set to a voltage lower than that of the power supply 114. Reference numeral 1,800 is a signal charge storage capacitor having the same layer structure as for the photoelectric converting section 100. The electrode G of the storage capacitor is grounded to GND and the electrode D is grounded to the electrode G of the photoelectric converting section 100. Further, a TFT 1,300 transfers signal charges in a detecting operation and a G electrode initialize-TFT 1,400 initializes potential of the electrode G (also referred to as “G electrode reset-TFT” hereinafter). A part enclosed by a dashed line is a detecting means, which generally comprises IC or other components and is shown as an example in FIG. 41. Reference numerals 1,124, 1,125, and 1,126 indicate a read capacitor, a switching element for initializing the read capacitor, and an operational amplifier, respectively. The detecting means is not limited to this example, but it is only required that it can detect current or charges directly or by integrated values. For example, if signal charges are not stored in the read capacitor 1,124, but are read out with a current meter, the read capacitor 1,124 and the switching element 1,125 for initializing potential can be omitted.

Now, using FIG. 41, the operation of the photoelectric converter of this embodiment is described below.

In the refresh operation of the photoelectric converting section, the TFT 1,700 is shifted from an off state to an on state by a Pc high potential (also referred to as “high level”hereinafter) pulse and the power supply 1,115 applies positive potential to the electrode G. Positive potential is applied to the electrode D by the power supply 114, therefore, positive potential is applied to potential V_DG of the electrode D opposite to the electrode G. Then, a part of holes in the photoelectric converting section 100 are swept out to the electrode D for refreshment. Next, the TFT 1,400 is shifted from an off state to an on state by a Pd high-level pulse and GND potential is applied to the electrode G. At this point, larger positive potential is applied to V_DG, and the photo-electric converting section 100 starts a photoelectric converting operation after inrush current flows. Then, the TFT 1,400 is turned off by a Pd low potential (also referred to as “low level” hereinafter) pulse and the electrode G is grounded via the charge storage capacitor 1,800. If signal light is incident on the photoelectric converting section 100, corresponding current flows out of the electrode G and the potential of the electrode G is increased. In other words, incident light information is stored in a capacitance of the electrode G as electric charges. After a certain storage time, the transfer-TFT 1,300 is shifted from an off state to an on state by a Pb high-level pulse and the stored charges flow to the capacitor 1,124. The quantity of the charges is proportional to an integrated value of the current flowing out of the photoelectric converting section 100 in the photoelectric converting operation, in other words, it is detected by the detecting means through the operational amplifier 1,126 as a total quantity of the incident light. It is desirable that the potential of the capacitor 1,124 is initialized to GND potential by a Pa high-level pulse from the TFT 1,125 before this transfer operation. When the transfer-TFT 1,300 is turned off, the refresh-TFT 1,700 is turned on by a Pc high-level pulse, and then the sequential operation is repeated afterward.

Accordingly, a photoelectric conversion can be performed with a high signal-to-noise ratio and superior characteristics.

[18th embodiment]

FIG. 42 is a single-bit schematic equivalent circuit diagram of a photoelectric converter of this embodiment of the present invention. FIG. 43 is a timing diagram illustrating an example of practically driving the photoelectric converter in FIG. 42.

A configuration in FIG. 42 corresponds to the configuration in FIG. 41, and the same reference numerals designate the same corresponding parts. Explanation of the same parts as for FIG. 41 is simplified or omitted.

In this embodiment, a refresh means can include a TFT 1,700, a means for applying a high-level pulse Pc, a power supply 1,115, and a power supply 1,114.

Further, a signal detecting section can include a detecting means enclosed by a dashed line in FIG. 42, a TFT 1,300, a means for applying a high-level pulse Pb, and a storage capacitor 1,800.

FIG. 42 is different from FIG. 41 in a point that a terminal of the storage capacitor 1,800 connected to an electrode G of a photoelectric converting section 100 is not an electrode D, but an electrode G.

Next, referring to FIG. 43, the operation is described. FIG. 43 focuses on current l_s of the photoelectric converting section 100 and behavior of potential V_o of the electrode G caused by the current l_s.

In FIG. 43, when a Pc refresh pulse rises and a voltage is applied to the electrode G of the photoelectric converting section 100, a part of the holes remaining in the i-layer are swept out to the electrode D.

Next, a Pd G electrode reset pulse rises and the electrode G of the photoelectric converting section 100 is grounded to GND, all of some electrons remaining in the i-layer flow out to the electrode D. Then, the Pd G electrode reset pulse falls. Signal charges begin to be stored from the Pd pulse fall, wherein a charge storage electrode for the storage capacitor 1,800 is the electrode G and an electrode to be grounded is the electrode D, therefore, an energy band of the i-layer 4 in the storage capacitor 1,800 is almost flat showing so-called a flat-band condition. Generally, zero or a small positive voltage is applied to a side of an insulating layer to make a flat-band condition of an MIS-type capacitor as so-called a flat-band voltage. Accordingly, if the flat-band voltage is zero, the capacitor 1,800 is not put in a depression state from a start of the charge storage to its termination as mentioned above. If the flat-band voltage is a small positive voltage, the storage capacitor 1,800 can be used not in the depression state, but in an accumulation state from the start of the charge storage to its termination by inserting a power supply having a voltage equivalent to or greater than the positive flat-band voltage between a G electrode reset-TFT 1,400 and the GND in FIG. 42. In other words, there occurs no leak current which flows via a storage capacitor 1,800 in the photoelectric converter described by using FIG. 41. Accordingly, almost all the electric charges stored in the storage capacitors and other stray capacitance are charges generated by signal light incident on the photoelectric converting section 100, and it is possible to obtain information with a high signal-to-noise ratio by reading its signal voltage. A signal detecting element within a rectangular range indicated by a dashed line in FIG. 42 is not limited specifically and it is only required that it can detect current or charges directly or with integrated values. In addition, if signal charges are read out by means of a current meter or the like without being stored into a readout capacitor 1,124, the readout capacitor 1,124 and a potential initialization switching element 1,125 can be omitted, as mentioned in the explanation of the photoelectric converter in FIG. 41.

In this embodiment, as described above, it is possible to use the signal storage capacitor always in the accumulation state by storing signal charges in the electrode G in the insulating layer 70 for the signal storage capacitor, therefore, there occurs apparently almost no leak current caused by a leakage of signal charges through the signal charge storage capacitor, which makes it possible to provide a further higher signal-to-noise ratio photoelectric converter.

[19th embodiment]

The 19th embodiment of the present invention is described below by using FIGS. 44 to 46.

FIG. 44 is a schematic equivalent circuit diagram illustrating a photoelectric converter of this embodiment. The explanation is made by giving an example of a photoelectric converting element array including nine photoelectric converting elements being one-dimensionally arranged. FIG. 45 is a plan view illustrating a photoelectric converting section including a plurality of pixels in a longitudinal direction, a storage capacitor section, a refresh-TFT section, a transfer-TFT section, a reset-TFT section, and a line section for a single pixel. FIG. 46 is a sectional view of a single pixel. FIG. 46 is typically drawn for understanding and a position of the line section does not match the position in FIG. 4A completely. Further, a reset-TFT section 1,400 is not shown in FIG. 46. The same reference numerals in FIGS. 44 to 46 designate the same parts as for FIG. 42.

In FIG. 45, the photoelectric converting section 100 includes a lower electrode 2 which also serves as a light shielding film against light from a substrate side. Light from the substrate side is reflected on a surface of an original copy (not shown) located perpendicularly upward against the drawing through a light window 17, and the reflected light impinges on the photoelectric converting section 100. Light current caused by carriers generated at this point is stored in equivalent capacitive components of a storage capacitor 1,800 and the photoelectric converting element 100 and other stray capacitance. The stored charges are transferred to the matrix line section 1,500 for signal lines by the transfer-TFT 1,300 and read as a voltage by a signal processing section (not shown).

Referring to FIG. 46, the layer structure of the components is roughly explained.

In FIG. 46, reference numerals 100, 1,800, 1,700, 1,300, and 1,500 indicate the photoelectric converting section, the storage capacitor, a refresh-TFT, the transfer-TFT, and the line section, respectively. These components have an identical layer structure consisting of five layers, a first electrode layer including 2-1, 2-2, and 2-3, an insulating layer 70, an i-layer 4, an n-layer 5, and a second electrode layer including 6-1, 6-2, 6-3, 6-4, and 6-5. The second electrode layer is not specifically transparent.

Next, how to drive the photoelectric converter of the 19th embodiment is described below by using the circuit diagram.

In FIG. 44, photoelectric converting elements S1 to S9 constitute a photoelectric converting element array consisting of three blocks each of which is composed of three photoelectric converting elements. This configuration is also used for storage capacitors D1 to D9 each connected to corresponding photoelectric converting elements S1 to S9, refresh-TFTs F1 to F9, TFTs F1 to F9 for initializing potential of the electrode G for the photoelectric converting elements S1 to S9, and TFTs T1 to T9 for transferring signal charges. An individual electrode having an identical order in each block of the photoelectric converting elements S1 to S9 is connected to one of common lines 1,102 to 1,104 via the transfer-TFTs T1 to T9. More specifically, the transfer-TFTs T1, T4, and T7 which belong to a first group of each block are coupled to the common line 1,102, the transfer-TFTs T2, T5, and T8 which belong to a second group of each block are coupled to the common line 1,103, and then the transfer-TFTs T3, T6, and T9 which belong to a third group of each block are to the common line 1,104. The common lines 1,102 to 1,104 are coupled to an amplifier 1,126 via switching transistors T100 to T120, respectively.

Further in FIG. 44, the common lines 1,102 to 1,104 are grounded via common capacitors C100 to C120, respectively, and also grounded via switching transistors CT1 to CD. Each gate electrode for the switching transistors CT1 to CD is coupled via each common line to discharge remaining charges of the common lines 1,102 to 1,104 to GND for potential initialization by being turned on at the same timing as for the Pa pulse in FIG. 43.

In this embodiment, photoelectric converting means include TFTs R1 to R9, a shift register 1,109, and a power supply 114, and refresh means include TFTs F1 to F9, a shift register 1,108, a power supply 1,115, and a power supply 1,114. Further, a signal detecting section includes a detecting means enclosed by a dashed line in FIG. 44, the TFTs T1 to T9, a shift register 1,106, a storage capacitors D1 to D9.

Next, the operation of the 19th embodiment is described in time series.

If signal light is incident on the photoelectric converting elements S1 to S9 first, electric charges are stored in the storage capacitors D1 to D9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance depending on its intensity. At this point, as mentioned for the 18th embodiment, electrons and holes in each i-layer of the storage capacitors D1 to D9 do not flow out to the electrode G since the electrode G in the insulating layer side is a charge storage electrode, therefore, apparent leak current does not occur in the storage capacitors D1 to D9. Then, when a high level is output from a parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the storage capacitors D1 to D3, the capacitive components, and the stray capacitance are transferred to the common capacitors C100 to C120. Subsequently, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.

After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 to turn on the refresh-TFTs F1 to F3 and it increases potential of the electrode G for the photoelectric converting elements S1 to S3. Then, a part of holes in the photoelectric converting elements S1 to S3 are swept out to the common power supply line 1,403.

Next, a high level is output from a first parallel terminal of a shift register 1,109 and the reset-TFTs R1 to R3 are turned on, which initializes potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the storage capacitors D4 to D6, the equivalent capacitive components of the photoelectric converting elements S4 to S6, and their stray capacitance in the second block to the common capacitors C100 to C120. After that, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential readout of light signals of the second block stored in the common capacitors C100 to C120.

Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.

Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.

As explained in this embodiment by using FIG. 46, the photoelectric converting elements, the storage capacitors, the refresh-TFTs, the transfer-TFTs, the reset-TFTs, and the matrix signal line section have an identical layer structure consisting of five layers including the first electrode layer, the insulating layer, the i-layer, the n-layer, and the second electrode layer, but all the elements do not need to have the same layer structure necessarily. It is only required that at least the photoelectric converting elements and the storage capacitors have this (MIS) structure and that other elements each have a layer structure which allows it to serve as each element. If they have the identical layer structure, however, it is more effective to improve an yielding ratio and to lower the cost.

In addition, in the above explanation of the 18th or 19th embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the above embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in the 18th or 19th embodiment.

Although a one-dimensional line sensor is explained in the 19th embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.

As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the storage capacitors, the TFTs and the matrix signal line section, the layers can be formed in an identical process at a time in the 19th embodiment in addition to the effect of the 18th embodiment, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost.

[20th embodiment]

The 20th embodiment is described below by using FIGS. 47 to 49.

FIG. 47 is a schematic equivalent circuit diagram illustrating the photoelectric converter of the 20th embodiment of the present invention. In the same manner as for the 19th embodiment, the explanation is made by giving an example of a photoelectric converting element array including nine photoelectric converting elements being one-dimensionally arranged.

FIG. 48 is a plan view illustrating a photoelectric converting element section including a plurality of pixels in a longitudinal direction, a storage capacitor/refresh capacitor section, a transfer-TFT section, a reset-TFT section, and a line section for a single pixel.

FIG. 49 is a sectional view of a single pixel. FIG. 49 is typically drawn for understanding and the position of the line section does not match the position in FIG. 49 completely. In addition, the reset-TFT section 1,400 is not shown in FIG. 49. The same reference numerals in FIGS. 47 to 49 designate the same parts as for FIGS. 42 and 44 to 46.

In FIG. 48, the photoelectric converting section 100 includes a lower electrode 2 which also serves as a light shielding film against light from a substrate side. Light from the substrate is reflected on a surface of an original copy (not shown) located perpendicularly upward against the drawing through a light window 17, and the reflected light impinges on the photoelectric converting section 100. By means of carriers generated at this point, photocurrent is stored in a storage/refresh capacitor 1,200, equivalent capacitive components of the photoelectric converting section 100, and other stray capacitance. The stored charges are transferred to a matrix line section 1,500 by a transfer-TFT 1,300 and read as a voltage by a signal processing section (not shown).

Using FIG. 49, a layer structure is roughly described below.

In FIG. 49, the photoelectric converting section 100, the storage/refresh capacitor 1,200, the transfer-TFT 1,300, and the line section 1,500 have an identical layer structure consisting of five layers, a first electrode layer including 2-1, 2-2, and 2-3, an insulating layer 70, an i-layer 4, an n-layer 5, and a second electrode layer including 6-1, 6-2, 6-3, and 6-4. In the same manner as for the 19th embodiment, the second electrode layer is not specifically transparent.

Now, how to drive the photoelectric converter of this embodiment is described below by using the circuit diagram.

In FIG. 47, photoelectric converting elements S1 to S9 constitute a photoelectric converting element array consisting of three blocks each of which is composed of three photoelectric converting elements. This configuration is also used for storage/refresh capacitors C1 to C9 each correspondingly coupled to the photoelectric converting elements S1 to S9, TFTs R1 to R9 for initializing potential of the electrode G for the photoelectric converting elements S1 to S9, and TFTs T1 to T9 for transferring signal charges.

An individual electrode having an identical order in each block of the photoelectric converting elements S1 to S9 is connected to one of common lines 1,102 to 1,104 via the transfer-TFTs T1 to T9. More specifically, the transfer-TFTs T1, T4, and T7 which belong to a first group of each block are coupled to the common line 1,102, the transfer-TFTs T2, T5, and T8 which belong to a second group of each block are to the common line 1,103, and then the transfer-TFTs T3, T6, and T9 which belong to a third group of each block are to the common line 1,104. The common lines 1,102 to 1,104 are connected to an amplifier 1,126 via switching transistors T100 to T120, respectively.

Further in FIG. 47, the common lines 1,102 to 1,104 are grounded via common capacitors C100 to C120, respectively, and also grounded via switching transistors CT1 to CD. Each gate electrode for the switching transistors CT1 to CD is coupled via each common line to discharge remaining charges of the common lines 1,102 to 1,104 to GND for potential initialization by being turned on at the same timing as for the Pa pulse in FIG. 43.

In this embodiment, photoelectric converting means include TFTs R1 to R9, a shift register 1,109, and a power supply 114 and refresh means include the capacitors C1 to C9, a shift register 1,108, and a power supply 114. Further, a signal detecting section include detecting means enclosed by a dashed line in FIG. 47, the TFTs T1 to T9, a shift register 1,106, and the capacitors C1 to C9. In other words, the capacitors C1 to C9 accumulate signal charges and also constitute a part of the refresh means.

Next, the operation of this embodiment is described in time series below.

First, if signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored in storage/refresh capacitors C1 to C9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance depending on its intensity. At this point, as mentioned for the 18th embodiment, electrons and holes in each i-layer of the storage/refresh capacitors C1 to C9 do not flow out to the electrode G since the electrode G in the insulating layer side is a charge storage electrode, therefore, apparent leak current does not occur in the storage/refresh capacitors C1 to C9. Then, when a high level is output from a parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the storage/refresh capacitors C1 to C3, the capacitive components, and the stray capacitance are transferred to the common capacitors C100 to C120. Subsequently, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.

After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 and it increases potential across the storage/refresh capacitors C1 to C3 or potential of the electrode G for the photoelectric converting elements S1 to S3. Then, holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403.

Next, turning on the reset-TFTs R1 to R3 for which a high level is output from a first parallel terminal of a shift register 1,109 initializes potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the storage/refresh capacitors C4 to C6, the equivalent capacitive components of the photoelectric converting elements S4 to S6, and the stray capacitance in the second block to the common capacitors C100 to C120. Then, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential readout of light signals of the second block stored in the common capacitors C100 to C120.

Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.

Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.

In this embodiment, the photoelectric converting elements, the storage/refresh capacitors, the transfer-TFTs, the reset-TFTs, and the matrix signal line section have an identical layer structure consisting of five layers including the first electrode layer, the insulating layer, the i-layer, the n-layer and the second electrode layer, but all the elements do not need to have the same layer structure necessarily. It is only required that at least the photoelectric converting elements and the storage/refresh capacitors have this (MIS) structure and that other elements each have a layer structure which allows it to serve as each element. If they have the identical layer structure, however, it is more effective to improve an yielding ratio and to lower the cost.

Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment, in the same manner as for the 19th embodiment.

In this embodiment, it is possible that the storage capacitors have a refresh function in addition to the effects of the 18th and 19th embodiments as mentioned above, therefore, due to miniaturization and a high yielding ratio, a lower cost photoelectric converter can be achieved.

[21st embodiment]

FIG. 50 is a schematic circuit diagram of a photoelectric converter according to this embodiment of the present invention.

In FIG. 50, there are included photoelectric converting elements S11 to Smn arranged in a matrix shape, and numeral G indicates electrodes at the lower sides of the photoelectric converting elements S11 to Smn and numeral D indicates electrodes at the upper side thereof. Also, numerals C11 to Cmn indicate storage capacitors and numerals T11 to Tnm indicate transfer-TFTs. A read power supply Vs and a refresh power supply Vg are connected with the electrodes G of all photoelectric converting elements S11 to Smn through a switch Sws and a switch Swg, respectively. The switch Sws is connected to a refresh control circuit RF through an invertor and the switch Swg is directly connected to the refresh control circuit RF. Both switches Sws and Swg are controlled so that the Swg is turned on during a refresh time and the Sws is turned on at the other time. One pixel is constituted of one photoelectric converting element, a capacitor to which the photoelectric converting element is connected in parallel and a TFT. The signal output of the pixel is connected to an integrated circuit IC for detection by a signal line SIG. The photoelectric converter of this embodiment includes pixels of m×n numbers which are divided into m blocks so that the signal outputs of n pixels are transferred simultaneously every block to the integrated circuit IC for detection through the signal line SIG. The transferred signal outputs are converted by the integrated circuit IC for detection in due order and output (V_out). The respective pixels are constituted two-dimentionally by arranging n pixels in a lateral direction every block and m blocks in a longitudinal direction in order.

In addition, the photoelectric converter shown in FIG. 50 operates in the same manner as that shown in FIG. 19 but different in polarity of Vg and magnitude of Vs.

Next, the photoelectric converter according to this embodiment will be described.

Shift registers SR1 and SR2 first applies a Hi (High voltage) to control lines g1 to gm and sg1 to sgn. Thus, the transfer-TFTs T11 to Tmn and switches M1 to M3 are turned on to be in a conductive state, and then, the electrodes D of all photoelectric converting elements S11 to Smn become GND potential (because an input terminal of an integral detector Amp. is designed to be GND potential). At the same time, the refresh control circuit RF outputs the Hi to turn on the switch Swg so that the electrodes G of all the photoelectric converting elements S11 to Smn are turned by the refresh power supply Vg to negative potential whose magnitude of the absolute value is small. As a result, all the photoelectric converting elements S11 to Smn are turned to a refresh mode to be refreshed. The refresh control circuit RF next outputs a Lo (Low voltage signal) to turn on the switch SWs so that the electrodes G of all the photoelectric converting elements S11 to Smn are turned by the read power supply V_s to negative potential whose magnitude of the absolute value is large. As a result, all the photoelectric converting elements S11 to Smn are turned to a photoelectric conversion mode to initialize the capacitors C11 to Cmn simultaneously.

As described above, in the refresh mode of this embodiment, the potential of the electrodes G is set to the negative potential in comparison with the potential of the electrodes D and the potential of the electrodes G does not reach a flat-band voltage V_FB. Accordingly, as described in the foregoing embodiments, electrons can not reach the interface between the insulating layer and the photoelectric converting semiconductor layer and this makes it possible to inhibit the electrons from coming in and out of the interface defects. For this reason, inrush currents can be reduced and a photoelectric converter of high signal-to-noise ratio can be realized.

In this embodiment, while each electrode D of the photoelectric converting elements is connected to the TFT and each electrode G of the photoelectric converting elements is connected commonly, the electrode G may be connected to the TFT and the electrode D may be connected commonly. In this case, the same operations can be performed by reversing the polarities of Vg and Vs.

Also in this embodiment, while the number of pixels has been defined as mxn, in actuality, it can be selected properly in accordance with system structure. For example, when pixels are arranged on one substrate of 20 cm×20 cm size, assuming that n is 2,000 and m is 2,000, the pixels of m×n numbers, i.e., the photoelectric converting elements of 4,000,000 numbers are arranged with a density of 100 μm pitches on the substrate.

In FIG. 50, while the shift register SR1 and the integrated circuit IC for detection are respectively represented by only one component, in actuality, they can be constituted in proper numbers in accordance with numbers of m and n.

FIG. 51 is a schematic block diagram illustrating the whole system. In this drawing, a plurality of shift registers SR1 are arranged in parallel and the integrated circuit IC for detection is constituted in plural numbers and driven. The output from each integrated circuit IC for detection is input to a corresponding ND converter 6002 in a processing circuit 6008 to be digitalized. The output from the A/D converter 6002 is memorized in a corresponding memory 6004 through a subtracter 6003. The information stored in the memory is controlled by a controller 6005 and then transferred to an image processor 6007 as a signal processing means through a buffer 6006 so that an image-processing of the information is performed therein.

FIGS. 52A and 52B show an X-ray detecting photoelectric converter which adapts the present invention; FIG. 52A is a schematically structural diagram and FIG. 52B is a schematically sectional view.

The photoelectric converting element and the TFT are constituted in plural numbers inside an a-Si sensor substrate 6011 and connected with flexible circuit substrates 6010 on which shift registers SR1 and integrated circuits IC for detection are mounted. The opposite side of the flexible circuit substrates 6010 are connected with a PCB1 or a PCB2. A plurality of the a-Si sensor substrates 6011 are adhered onto a base 6012 so as to constitute a large-sized photoelectric converter. A lead plate 6013 is mounted under the base 6012 so as to protect memories 6014 in a processing circuit 6018 from X rays. A phosphor 6030 such as Cs1 or the like is coated on or adhered to the a-Si sensor substrate 6011. On the basis of the same principle as the X-ray detecting method described above in FIGS. 19 and 20, the X rays can be detected. In this embodiment, as shown in FIG. 52B, the whole is packed in a case 6020 made of carbon fiber.

FIG. 53 shows an applied example in which the photoelectric converter of the present invention is applied to an X-ray diagnosis system.

X rays 6060 emitted from an X-ray tube 6050 are transmitted through the chest 6062 of a patient or an examinee 6061 to be incident to a photoelectric converter 6040 on which a phosphor has been mounted. The incident X rays include the internal information of the patient. Here, the phosphor emits light in response to the incident X rays and the emitted light is photoelectrically converted to obtain the electric information. The electric information is then converted to be digitalized and an image on the electric information is processed by an image processor 6070 to be able to observe on a display 6080 in a control room. This information can be transferred to a remote place, such as a doctor room located in other place or the like, by way of a transmission means such as a telephone line 6090 and displayed on a display 6081 or stored in a storage means such as an optical disk, and this makes it possible to be diagnosed by a doctor in a remote place. Also, this information can be recorded on a film 6110 by a film processor 6100.

[Effect]

As described above, the present invention can provide a photoelectric converter having a high signal-to-noise ratio and stable characteristics and a system having the above photoelectric converter.

Also, the present invention can provide a photoelectric converter having a high yield and high productivity.

In addition, the present invention can provide a photoelectric converter which can be composed in the same process as for the TFT, will not complicate fabrication processes, and can be fabricated at a low cost, its driving method and a system including the above photoelectric converter.

According to the present invention, the photoelectric converting section (photoelectric element) in the photoelectric converter can detect the incident amount of light only in one place of the injection blocking layer, so that the processes can be easily optimized, the yield can be improved and the manufacturing cost can be also reduced. Accordingly, a photoelectric converter of a high signal-to-noise ratio and low cost can be provided. Also, according to the present invention, any tunnel effect or Schottky barrier is not used in the interfaces between the first electrode layer, the insulating layer and the photoelectric converting semiconductor layer, so that the electrode material can be selected freely as well as the thickness of the insulating layer or other control. Furthermore, the photoelectric element matches well with the switching and capacitive elements such as thin-film field effect transistors (TFT), both being formed at the same time as the photoelectric element, and can be formed simultaneously as the common films with the TFTs due to the same film structure. The film structure important to the photoelectric element and the TFTs can be also formed in an identical vacuum at the same time. Accordingly, an excellent photoelectric converter of a further high signal-to-noise ratio and low cost can be provided.

The present invention can also provide a photoelectric converter having complex functions with a simplified structure since the photoelectric element itself has a property to store optical information as carriers, with simultaneously flowing the current at a real-time. Further, the capacitor of the above photoelectric converter includes an insulating layer in its middle layer and can be formed with a preferable properties, and this makes it possible to provide a photoelectric converter of high functions so that the integral values of the optical information obtained in the photoelectric element can be output with a simplified structure.

Furthermore, according to the present invention, the refresh operation of the photoelectric element can be performed through the capacity of the capacitor or the like and this makes it possible to generate an inrush current at the instant the applied voltage was dropped down. In comparison with the case the refresh operation is performed by using the TFT, this reduces the stored inrush currents extremely, therefore, an excellent photoelectric converter of a further high signal-to-noise ratio and low cost can be provided.

Furthermore, in the refresh operation of the photoelectric element, for example, if the semiconductor injection blocking layer of the photoelectric element has an n-type structure, i.e., if an electric charge q of carriers inhibited from their injections is positive, electrons can be inhibited from coming in and out of the interface defects generated between the insulating layer and the photoelectric converting semiconductor layer by a condition represented by {(V_rg·q)<(V_D·q−V_FB·q)}, where the potential of the electrode D is set higher than the potential of the electrode G. On the contrary, if the semiconductor injection blocking layer of the photoelectric element has a p-type structure, i.e., if the electric charge q of carriers inhibited from their injections is negative, electrons can be inhibited from coming in and out of the interface defects generated between the insulating layer and the photoelectric converting semiconductor layer by the condition represented by {(V_rg·q)<(V_D·q−V_FB·q)}, where the potential of the electrode D is set lower than the potential of the electrode G. Accordingly, an excellent photoelectric converter of a further high signal-to-noise ratio and low cost which can reduce the inrush currents can be provided.

Furthermore, a capacitive element for signal-charge storage is formed by the identical laminating structure with the photoelectric element and the electric charge is stored at the electrode of insulating side of the capacitive element, so that the capacitive element for signal-charge storage can be used in the accumulation state at any time and the apparent leak currents generated by leaking the signal charge through the capacitive element for signal-charge storage can be reduced, thereby providing a photoelectric converter of a high signal-to-noise ratio and low cost.

Furthermore, according to the present invention, a plurality of photoelectric elements are divided into blocks so that the refresh operation in a block and the signal transfer operation in other block can be driven by an identical driving line at the same time. As a result, the read operation can be performed at a high speed and the converter can be decreased in size. Accordingly, a photoelectric converter of a high yield and low cost can be provided.

By utilizing the above photoelectric converter of excellent properties, a facsimile machine or a roentgen (X-ray) scope of a low cost, wide area, high functions and high characteristics can be also provided.

The present invention, however, is not limited to the structures and the embodiments described above, it will be understood that any modification and combination can be realized properly within the scope of the present invention.

Claims

1. A system having a photoelectric converter comprising:

a plurality of photoelectric converting elements sections formed on a substrate, each of the photoelectric converting elements sections including a first electrode layer and a second electrode layer, an insulating layer formed between the first and second electrode layers for inhibiting a first type of carriers both of electrons and holes from passing through the layer, a semiconductor layer, and an injection blocking layer for inhibiting said first type of carriers either of electrons or holes from being injected into the semiconductor layer;

a switch section for applying an electric field to each layer of said photoelectric converting elements sections in a direction so that said first type of carriers are one type of carrier, electrons or holes, is introduced from said semiconductor layer to said second electrode layer in a refresh mode or and in a direction so that said first type of carriers the one type of carrier generated by light incident on said semiconductor layer remain in said semiconductor layer and said second type of carriers are the other type of carrier generated by light incident on said semiconductor layer is introduced to said second electrode layer in a photoelectric conversion mode; and

a signal processing means for processing signals output from connected to the photoelectric converting elements.

2. A system according to claim 1, further comprising a record means for recording signals output from said signal processing means.

3. A system according to claim 1, further comprising a display means for displaying signals output from said signal processing means.

4. A system according to claim 1, further comprising a transmission means for transmitting signals output from said signal processing means.

5. A system according to claim 1, wherein said photoelectric converter has a phosphor.

6. A system according to claim 1, further comprising a light source for emitting light to generate optical information input to said photoelectric converter.

7. A system according to claim 6, wherein said light source emits X-rays.

8. A method of driving a photoelectric converting element apparatus having a photoelectron converting section formed on a substrate, the photoelectric converting element and including a first electrode layer; an insulating layer for inhibiting both of two types of carriers, a first type of carriers and a second type of carriers whose positive or negative characteristics are opposite to those of the first type of carriers, from passing through the layer; a semiconductor layer including the first and second types of carriers ; an injection blocking layer for inhibiting the a first type of said carriers from being injected into the semiconductor layer; and a second electrode layer arranged adjacent to said injection blocking layer,

the driving method having a refresh and a photoelectric conversion mode, wherein an electric field is applied so that the first type of said carriers are brought from said semiconductor layer into said second electrode layer in the refresh mode, and

detecting, while an electric field is applied so that the first type of said carriers generated by light incident in said semiconductor layer remain in said semiconductor layer and the a second type of said carriers are introduced into said second electrode in the photoelectric conversion mode, and, under an influence of an electric field having the same direction as in the photoelectric conversion mode, the first and second types of said carriers stored in said semiconductor layer are detected .

9. A method according to claim 8, wherein the photoelectric converting apparatus further comprising comprises a capacitive storing element wherein integral values depending upon said carriers are stored and read out.

10. A method according to claim 8, wherein the photoelectric converting apparatus further comprising comprises a plurality of said photoelectric converting sections wherein the plurality of said photoelectric converting sections are electrically connected in each within a respective block and, when one of the blocks is in the photoelectric conversion mode, at least one of the other blocks is turned to the refresh mode.

11. A method according to claim 8, wherein an electric field is applied to said photoelectric converting elements sections in said refresh mode in accordance with a condition represented by (V_rG·q<V_D·q−V_FB·q), where the product (V_rG·q) of a voltage (V_rG) of said first electrode layer in said photoelectric converting section and an electric charge (q) of said first type of carriers becomes smaller than the product (V_D·q−V_FB·q) of a voltage (V_D−V_FB), the voltage subtracting a threshold voltage (V_FB) from a voltage (V_D) of said second electrode layer, and the electric charge (q) of said first type of carriers.

12. A method according to claim 9, wherein said capacitive storing element has two electrode layers, an insulating layer held between the electrode layers and a semiconductor layer to be operated in the accumulation state.

13. A photoelectric converter having a photoelectric converting section provided on a substrate having a surface which is at least isolative , and first and second integrated circuit element groups provided outside of said photoelectric converting section, wherein:

said photoelectric converting section has plural combinations of a photoelectric converting element and a thin film transistor arranged correspondingly to said photoelectric converting element, one electrode of said photoelectric converting element is connected to a line capable of being set at a predetermined voltage, the other another electrode of said photoelectric converting element is connected to either one of the source and or drain electrodes of said thin film transistor, a gate electrode of said thin film transistor is connected to said first integrated circuit element group arranged outside of said photoelectric converting section through a driving line provided commonly to said plural combinations of a photoelectric converting element and a thin film transistor and said and second first integrated circuit element groups group for supplying to said gate electrode a signal for driving said thin film transistor, and the other of the source and drain electrodes different from the one of the source and the other of the source or drain electrodes of said thin film transistor are is connected to the second integrated circuit element group through an output line common to a group of said plural combinations of a photoelectric converting element and a thin film transistor and arranged in a direction crossing said driving line;

said photoelectric converting element has first and second electrode layers on said substrate, and has an insulating layer, between said first and second electrode layers, an insulating layer for blocking passage of a hole and an electron therethrough, a semiconductor layer, and a carrier blocking layer for blocking passage of one of the hole and the electron; and

said thin film transistor has, on said substrate, a gate electrode, and source and drain electrodes arranged in spaced relation, and has between said gate electrode and said source and drain electrodes, an insulating layer to be a gate insulating film, a semiconductor layer and an ohmic contact layer, said ohmic contact layer is arranged correspondingly to said source and drain electrodes, and said ohmic contact layer and said source and drain electrodes are provided at one side surface of said semiconductor layer.

14. A photoelectric converter according to claim 13, wherein said first electrode layer of said photoelectric converting element, and said gate electrode of said thin film transistor, said second electrode layer of said photoelectric converting element, and said source and drain electrodes of said thin film transistor, said insulating layer on said photoelectric converting element, and said gate insulating film of said thin film transistor, said semiconductor layer of said photoelectric converting element, and said semiconductor layer of said thin film transistor, said carrier blocking layer of said photoelectric converting element, and said ohmic contact layer of said thin film transistor, are respectively, produced from the same material, and have respectively the same thickness.

15. A photoelectric converter according claim 13, wherein said first and second integrated circuit element groups are respectively arranged at a periphery of said photoelectric converting section.

16. A photoelectric converter according to claim 13, wherein said photoelectric converting section is quadrilateral, and said first and second integrated circuit element groups are arranged separately along sides of the quadrilateral.

17. A photoelectric converter having a photoelectric converting section provided on a substrate having a surface which is at least insolative , wherein said photoelectric converting section has in matrix arrangement plural combinations of a photoelectric converting element and a thin film transistor arranged correspondingly to said photoelectric converting element, one electrode of said photoelectric converting element is connected to a line capable of being set at a predetermined voltage, the other another electrode of said photoelectric converting element is connected to one of the source and or drain electrodes of said thin film transistor, the other of the source and or drain electrodes drain electrodes of said thin film transistor are is connected to an output line common to a group of said plural combinations of a photoelectric converting element and a thin film transistor for outputting a signal derived by a photoelectric conversion of said photoelectric conversion elements of the group, and a gate electrode of said thin film transistor is connected to a driving line common to a group of said plural combinations of a photoelectric converting element and a thin film transistor for supplying said gate electrode with a signal for driving said thin film transistors of this group in a direction crossing the output line for outputting the signal , and said photoelectric converter further comprises a passivation film provided on a group of said photoelectric conversion elements and thin film transistors, and a fluorescent body provided on said passivation film.

18. A photoelectric converter according to claim 17, wherein said photoelectric converting element has first and second electrode layers on said substrate, an insulating layer between said first and second electrode layers for inhibiting a passage of a hole and an electron therethrough, a semiconductor layer, and a blocking layer for blocking a passage therethrough of one of the hole and the electron, in this order.

19. A photoelectric converter according to claim 18, wherein said thin film transistor has, on said substrate, a gate electrode, separately arranged source and drain electrodes, an insulating layer to be a gate insulating film between said gate electrode and said source and drain electrodes, a semiconductor layer and an ohmic contact layer, wherein said ohmic contact layer is provided correspondingly to the source and drain electrodes, and said ohmic contact layer and said source and drain electrodes are provided at one side surface of said semiconductor layer.

20. A method for driving a photoelectric converting section which comprises a first electrode layer; an insulating layer for preventing carriers of both of two types from passing through said insulating layer, the two types of carriers being a first type of carrier and a second type of carrier whose positive or negative polarity is opposite that of the first type of carrier ; a semiconductor layer; an injection blocking layer for preventing said a first type of carrier from being injected into said semiconductor layer; and a second electrode layer disposed in contact with said injection blocking layer, said method comprising:

a refreshment refresh mode for applying an electric field for guiding said first type of carrier from said semiconductor layer toward said second electrode layer; and

a photoelectric converting mode for applying an electric field for remaining to said first type of carrier generated by incident light in said semiconductor layer and for introducing said a second type of carrier from said semiconductor layer into said second electrode layer;

wherein, according to the electric field in the direction in said photoelectric converting mode, a charge corresponding to a carrier stored in said semiconductor layer in the photoelectric converting mode is detected .

21. A method according to claim 20, wherein:

the photoelectric converting section further comprising comprises a storage capacitor element, and

wherein a process for storing the carrier first type of carriers in said storage capacitor element for reading is provided.

22. A method according to claim 20, wherein a plurality of photoelectric converting sections are provided, and are connected within a respective block that includes a respective group of the photoelectric converting sections, and, when a selected block is in the photoelectric converting mode, at least one other block is in the refreshment refresh mode.

23. A method according to claim 20, wherein the electric field applied in the refreshment refresh mode is set to meet a condition that a product (VrG×q) of a voltage (VrG) of the first electrode layer of said photoelectric converting section and a charge (q) of the first type of carrier is not greater than a product ((VD−VFB)×q) of a voltage (VD−VFB) obtained by subtracting a threshold voltage (VFB) from a voltage (VD) of said second electrode layer and the charge (q) of the first type of carrier.

24. A method according to claim 21, wherein said storage capacitor element comprises two electrode layers and an insulating layer sandwiched between said electrode layers.

25. A method according to claim 21, wherein the charge corresponding to the stored carrier has a quantity of a charge flowing at the application of the electric field in the same direction as in the refreshment refresh mode.

26. A method according to claim 21, wherein a charge quantity corresponding to the stored carrier is a charge quantity flowing in the photoelectric converting mode.

27. A method according to claim 21, further comprising a step of subtracting from the charge corresponding to the stored carrier a charge corresponding to the stored carrier in a case of non-incident light at the photoelectric converting mode.

28. A photoelectric converter according to claim 13, further comprising a fluorescent substance on said photoelectric converting element.

29. A photoelectric converter according to claim 13, wherein said photoelectric converting element and said thin film transistor have thereon a passivation film, on which a fluorescent substance is provided.