A photoelectric converter of a high signal-to-noise ratio, low cost, high productivity and stable characteristics and a system including the above photoelectric converter. The photoelectric converter includes a photoelectric converting portion in which a first electrode layer, an insulating layer for inhibiting carriers from transferring, a photoelectric converting semiconductor layer of a non-single-crystal type, an injection blocking layer for inhibiting a first type of carriers from being injected into the semiconductor layer and a second electrode layer are laminated in this order on an insulating substrate.
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20. A method for driving a photoelectric converting section which comprises a first electrode layer; an insulating layer for preventing carriers of both of two types from passing through said insulating layer, the two types of carriers being a first type of carrier and a second type of carrier whose positive or negative polarity is opposite that of the first type of carrier ; a semiconductor layer; an injection blocking layer for preventing said a first type of carrier from being injected into said semiconductor layer; and a second electrode layer disposed in contact with said injection blocking layer, said method comprising:
a refreshment refresh mode for applying an electric field for guiding said first type of carrier from said semiconductor layer toward said second electrode layer; and
a photoelectric converting mode for applying an electric field for remaining to said first type of carrier generated by incident light in said semiconductor layer and for introducing said a second type of carrier from said semiconductor layer into said second electrode layer;
wherein, according to the electric field in the direction in said photoelectric converting mode, a charge corresponding to a carrier stored in said semiconductor layer in the photoelectric converting mode is detected .
1. A system having a photoelectric converter comprising:
a plurality of photoelectric converting elements sections formed on a substrate, each of the photoelectric converting elements sections including a first electrode layer and a second electrode layer, an insulating layer formed between the first and second electrode layers for inhibiting a first type of carriers both of electrons and holes from passing through the layer, a semiconductor layer, and an injection blocking layer for inhibiting said first type of carriers either of electrons or holes from being injected into the semiconductor layer;
a switch section for applying an electric field to each layer of said photoelectric converting elements sections in a direction so that said first type of carriers are one type of carrier, electrons or holes, is introduced from said semiconductor layer to said second electrode layer in a refresh mode or and in a direction so that said first type of carriers the one type of carrier generated by light incident on said semiconductor layer remain in said semiconductor layer and said second type of carriers are the other type of carrier generated by light incident on said semiconductor layer is introduced to said second electrode layer in a photoelectric conversion mode; and
a signal processing means for processing signals output from connected to the photoelectric converting elements.
8. A method of driving a photoelectric converting element apparatus having a photoelectron converting section formed on a substrate, the photoelectric converting element and including a first electrode layer; an insulating layer for inhibiting both of two types of carriers, a first type of carriers and a second type of carriers whose positive or negative characteristics are opposite to those of the first type of carriers, from passing through the layer; a semiconductor layer including the first and second types of carriers ; an injection blocking layer for inhibiting the a first type of said carriers from being injected into the semiconductor layer; and a second electrode layer arranged adjacent to said injection blocking layer,
the driving method having a refresh and a photoelectric conversion mode, wherein an electric field is applied so that the first type of said carriers are brought from said semiconductor layer into said second electrode layer in the refresh mode, and
detecting, while an electric field is applied so that the first type of said carriers generated by light incident in said semiconductor layer remain in said semiconductor layer and the a second type of said carriers are introduced into said second electrode in the photoelectric conversion mode, and, under an influence of an electric field having the same direction as in the photoelectric conversion mode, the first and second types of said carriers stored in said semiconductor layer are detected .
17. A photoelectric converter having a photoelectric converting section provided on a substrate having a surface which is at least insolative , wherein said photoelectric converting section has in matrix arrangement plural combinations of a photoelectric converting element and a thin film transistor arranged correspondingly to said photoelectric converting element, one electrode of said photoelectric converting element is connected to a line capable of being set at a predetermined voltage, the other another electrode of said photoelectric converting element is connected to one of the source and or drain electrodes of said thin film transistor, the other of the source and or drain electrodes drain electrodes of said thin film transistor are is connected to an output line common to a group of said plural combinations of a photoelectric converting element and a thin film transistor for outputting a signal derived by a photoelectric conversion of said photoelectric conversion elements of the group, and a gate electrode of said thin film transistor is connected to a driving line common to a group of said plural combinations of a photoelectric converting element and a thin film transistor for supplying said gate electrode with a signal for driving said thin film transistors of this group in a direction crossing the output line for outputting the signal , and said photoelectric converter further comprises a passivation film provided on a group of said photoelectric conversion elements and thin film transistors, and a fluorescent body provided on said passivation film.
13. A photoelectric converter having a photoelectric converting section provided on a substrate having a surface which is at least isolative , and first and second integrated circuit element groups provided outside of said photoelectric converting section, wherein:
said photoelectric converting section has plural combinations of a photoelectric converting element and a thin film transistor arranged correspondingly to said photoelectric converting element, one electrode of said photoelectric converting element is connected to a line capable of being set at a predetermined voltage, the other another electrode of said photoelectric converting element is connected to either one of the source and or drain electrodes of said thin film transistor, a gate electrode of said thin film transistor is connected to said first integrated circuit element group arranged outside of said photoelectric converting section through a driving line provided commonly to said plural combinations of a photoelectric converting element and a thin film transistor and said and second first integrated circuit element groups group for supplying to said gate electrode a signal for driving said thin film transistor, and the other of the source and drain electrodes different from the one of the source and the other of the source or drain electrodes of said thin film transistor are is connected to the second integrated circuit element group through an output line common to a group of said plural combinations of a photoelectric converting element and a thin film transistor and arranged in a direction crossing said driving line;
said photoelectric converting element has first and second electrode layers on said substrate, and has an insulating layer, between said first and second electrode layers, an insulating layer for blocking passage of a hole and an electron therethrough, a semiconductor layer, and a carrier blocking layer for blocking passage of one of the hole and the electron; and
said thin film transistor has, on said substrate, a gate electrode, and source and drain electrodes arranged in spaced relation, and has between said gate electrode and said source and drain electrodes, an insulating layer to be a gate insulating film, a semiconductor layer and an ohmic contact layer, said ohmic contact layer is arranged correspondingly to said source and drain electrodes, and said ohmic contact layer and said source and drain electrodes are provided at one side surface of said semiconductor layer.
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15. A photoelectric converter according
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the photoelectric converting section further comprising comprises a storage capacitor element, and
wherein a process for storing the carrier first type of carriers in said storage capacitor element for reading is provided.
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29. A photoelectric converter according to
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This application is a
Accordingly, Vo(refresh) can be altered at will depending on a size of the capacitor Cx to be inserted, which makes it possible to design more freely.
As apparent from the above description, signal charges can be stored in a condition that the positive inrush current is almost zero by applying the positive potential to the electrode G for the photoelectric converting section via the capacitor 1,200.
In this embodiment, a second electrode layer is not specifically transparent. Further, an n-type injection blocking layer is used between an i-layer and the second electrode layer and carriers inhibited from being injected are holes. Therefore, assuming that q is a charge for a carrier inhibited from being injected, q>0 is satisfied in this condition.
In the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result can be achieved as for the above embodiment by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.
[13th embodiment]
Using
In
Using
In
Since the photoelectric converting section 100 in this embodiment has also the same structure as for the first embodiment, an n-type injection blocking layer is used between the i-layer 4 and the second electrode layer 6-1 and carriers inhibited from being injected are holes. Therefore, assuming that q is a charge for a carrier inhibited from being injected, q>0 is satisfied in this condition, too.
Then, how to drive the photoelectric converter of this embodiment is described below by using FIG. 35.
In
An individual electrode having an identical order in each block of the photoelectric converting elements S1 to S9 is connected to one of common lines 1,102 to 1,104 via the transfer-TFTs T1 to T9. More specifically, the transfer-TFTs T1, T4, and T7 which belong to a first group of each block are coupled to the common line 1,102, the transfer-TFTs T2, T5, and T8 which belong to a second group of each block are to the common line 1,103, and then the transfer-TFTs T3, T6, and T9 which belong to a third group of each block are to the common line 1,104. The common lines 1,102 to 1,104 are coupled to an amplifier 1,126 via switching transistors T100 to T120, respectively.
Further in
In this embodiment, a refresh means includes the capacitors C1 to C9, a shift register 1,108, and a power supply 114, and a signal detecting section includes a detecting means enclosed by a dashed line in
Next, the operation of this embodiment is described in time series below.
If signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored from the power supply 114 into refresh capacitors C1 to C9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance depending on its intensity. Then, when a high level is output from a first parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the refresh capacitors C1 to C3, the capacitive components, and the stray capacitance are transferred to common capacitors C100 to C120. After that, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.
After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 and it increases potential across the refresh capacitors C1 to C3. Then, the holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403.
Next, a high level is output from a first parallel terminal of a shift register 1,109 and the reset-TFTs R1 to R3 are turned on, which initializes potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the refresh capacitors C4 to C6, the stray capacitance, and the sensor equivalent capacitive components in the second block to the common capacitors C100 to C120. After that, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential readout of light signals of the second block stored in the common capacitors C100 to C120.
Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.
Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.
As explained in this embodiment by using
In addition, in the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the first embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.
Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.
As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the TFTs, and the matrix signal line section in this embodiment, the layers can be formed in an identical process at a time, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost.
As apparent from the above description, the photoelectric converting elements are not limited to those shown by the embodiment. More specifically, it is only required that there are the first electrode layer, the insulating layer for blocking the movement of holes and electrons, the photoelectric converting semiconductor layer, and the second electrode layer, in addition to the injection blocking layer for blocking injection of holes into the photoelectric converting semiconductor layer between the second electrode layer and the photoelectric converting semiconductor layer. In addition, the photoelectric converting semiconductor layer only needs to have a photoelectric converting function of generating electron-hole pairs due to incident light. As for a layer structure, not only a single layer structure, but a multiple layer structure can be used and its characteristics can be altered repeatedly.
In the same manner, the TFTs each only need to have a gate electrode, a gate insulating layer, a semiconductor layer in which channels can be formed, an ohmic contact layer, and a main electrode. For example, the ohmic contact layer can be a p-layer. If it is so, a hole can be used as a carrier by reversing a control voltage of the gate electrode.
Additionally in the same manner, the capacitors each only need to have a lower electrode layer, a middle layer including an insulating layer, and an upper electrode layer, for example, they need not be especially separated from the photoelectric converting elements or the TFTs and it is possible to have a configuration in which they also serve as the electrode section for the photoelectric converting elements.
Further, the insulating substrate need not be always an insulator, and it can be a conductor or a semiconductor on which an insulator is laid.
In addition, since the photoelectric converting element itself has a function of accumulating charges, it is possible to obtain an integrated value of light information for a certain period without specific capacitors.
[14th embodiment]
The photoelectric converter illustrated in the schematic equivalent circuit diagram in
Now referring to
In the refresh operation of photoelectric converting elements, the potential of the electrode G is increased in this configuration only when a Pc high-level pulse is generated by supplying the refresh high-level pulse Pc to an electrode opposite to the electrode G of the capacitor 1,200 as shown in FIG. 38. Accordingly, holes remaining in the photoelectric converting section 100 are swept out to the electrode D and the photoelectric converting section 100 is refreshed.
Afterward, the potential of the electrode G opposite to the capacitor 1,200 also falls instantly at the same time when the Pc refresh pulse falls, therefore, the sweep-out of the holes remaining in the photoelectric converting section 100 to the electrode D is completed to enter a photoelectric converting operation. Practically, since positive inrush current shown in
Next, the TFT 1,400 is turned off by a Pd low potential (also referred to as “low level” hereinafter) pulse and the electrode G is opened for a direct current. Practically, however, the potential is kept by a capacitance of the capacitor 1,200 and equivalent capacitive components of the photoelectric converting section 100 or their stray capacitance. At this point, if a light signal of the photoelectric converting section 100 is incident, the corresponding current flows out of the electrode G to increase the potential of the electrode G.
In other words, the incident light information is stored in a capacitance of the electrode G as electric charges. After a certain storing time, the transfer-TFT 1,300 is shifted from the off state to an on state by a Pb high-level pulse and the stored charges flow to the capacitor 1,124. The quantity of the charges is proportional to an integrated value of the current flowing out of the photoelectric converting section 100; in other words, it is detected by the detecting section through the operational amplifier 1,126 as a total quantity of the incident light. It is desirable that the potential of the capacitor 1,124 is initialized to GND potential by a Pa high-level pulse from the TFT 1,125 before this transfer operation.
When the transfer-TFT 1,300 becomes off, the refresh-TFT 1,700 is set on by a Pc high-level pulse, and then the sequential operation is repeated after that. In this embodiment, the refresh means includes the capacitor 1,200, the high-level pulse Pc supplying means, and a power supply 114, and the signal detecting section includes the detecting means enclosed by the dashed line in
In this embodiment, positive inrush current (which does not have a condition indicated by a solid line on 1s in
As a method of reducing the positive inrush current, the time for the Pd initialization pulse can be extended. There, however, is a limit to the extended time, the time extension also elongates the entire signal read time of the apparatus, which causes speed-down or lowering performance of the apparatus.
Accordingly, if the refresh operation is performed by the capacitor and timing is set appropriately in this embodiment, for example, if the photoelectric converter is operated at a speed of approx. 100 μs from the Pc pulse fall to the Pd G electrode potential initialization pulse fall, the inrush current stored as Vo is lowered to substantially zero as shown in FIG. 38. Accordingly, almost all the electric charges started to be stored from the Pd pulse fall are charges generated by signal light incident on the photoelectric converting section 100, which makes it possible to obtain information with a high signal-to-noise ratio by reading its signal voltage. In addition, calculation is made to obtain potential Vo(refresh) of the electrode G when the Pc high-level pulse (Vres) is supplied to it. Supposing that Co is a sum of stray capacitance coupled to the electrode G and equivalent capacitive components of the photoelectric converting section 100 and Cx is a capacitance of the capacitor 1,200, Vo(refresh) can be represented by the following expression:
Vo(refresh)={Cx/(Co+Cx)}×Vres
Accordingly, Vo(refresh) can be altered at will depending on a size of the capacitor Cx to be inserted, which makes it possible to design more freely.
As apparent from the above description, signal charges can be stored in a condition that the positive inrush current is almost zero by applying the positive potential to the electrode G for the photoelectric converting elements via the capacitor 1,200. Furthermore, it is also possible to reduce a decay time by adjusting the potential applied to the electrode G via the capacitor 1,200 to lower a value of the positive inrush current.
The potential of the electrode D and the electrode G for the photoelectric converting elements in the refresh operation is described in detail by using
In this embodiment, superior characteristics can be obtained by driving the photoelectric converter under the conditions below.
In the refresh operation of the photoelectric converting section 100, the potential VrG of the power supply 1,115 for applying positive potential to the electrode G is lower than the potential VD of the power supply 114 for applying positive potential to the electrode D. More specifically, since the photoelectric converting section 100 has a flat-band voltage (VFB) to be applied to the electrode G to flat an energy band of the i-layer, practically the photoelectric converter is driven in a condition of VrG<VD−VFB.
As its concrete operation is described in detail in the 10th embodiment by using
In this embodiment, there are very little electrons in defects on the interface between the i-layer 4 and the insulating layer 70; therefore, it does not take a long time for injection or ejection of electrons, which leads to a considerable reduction of inrush current to be noise elements as a result.
Supposing that Cx is a capacitance of the capacitor 1,200, Co is a sum of stray capacitance coupled to the electrode G and equivalent capacitive components of the photoelectric converting section 100, and (Vres) is a Pc high-level pulse, the G electrode potential at the refresh operation VrG can be represented by the following expression:
VrG=Vo(refresh)={Cx/(Co+Cx)}×Vres
If the photoelectric converter is driven under a condition that a value of {Cx/(Co+Cx)}×Vresis smaller than VD−VFB, the above effects can be obtained and it is possible to reduce the accumulated inrush current further in comparison with Vo which can be obtained under a condition of VrG=Vo(refresh)≧(VD−VFB) shown in FIG. 38.
In this embodiment, the second electrode layer is not specifically transparent. Further, an n-type injection blocking layer is used between the i-layer and the second electrode layer in the photoelectric converting section 100 and carriers inhibited from being injected are holes. Therefore, assuming that q is an electric charge for a carrier inhibited from being injected, q>0 is satisfied in this condition. In the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result can be achieved as for the above embodiment by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.
[15th embodiment]
By using the photoelectric converter described in the 13th embodiment, an example of another driving method is described below.
Now the operation of this embodiment will be explained in time series.
If signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored in refresh capacitors C1 to C9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance from the power supply 114 depending on its intensity. Then, when a high level is output from a first parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the refresh capacitors C1 to C3, the capacitive components, and the stray capacitance are transferred to common capacitors C100 to C120. After that, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.
After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 and it increases potential across the refresh capacitors C1 to C3. For the potential of the electrode D and the electrode G for the photoelectric converting elements S1 to S3 at this point, the conditions described in the first embodiment are applied. In other words, supposing that VD1 to VD3, VrG1 to VrG3, and VFB1 to VFB3 are the potential of the electrode D, the potential of the electrode G, and the flat-band voltage for the photoelectric converting elements at the refresh operation, respectively, the following expressions are satisfied:
VrG1<VD1−VFB2, VrG2<VD2−VFB2, VrG3<VD3−VFB3
Then, the holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403.
Next, a high level is output from a first parallel terminal of shift register 1,109 and the reset-TFTs R1 to R3 are turned on, which initializes the potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of the potential of the common capacitors C10 to C120. When the potential of the common capacitors C10 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the refresh capacitors C4 to C6, the stray capacitance, and the sensor equivalent capacitive components in the second block to the common capacitors C100 to C120. After that, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential read out of light signals of the second block stored in the common capacitors C100 to C120. Conditions of the potential of the both electrodes for the photoelectric converting elements S4 to S6 at the refresh operation are the same as for the photoelectric converting elements S1 to S3.
Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.
Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.
As explained in this embodiment by using
In addition, in the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the first embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment, where q<0 is satisfied for the electric charge q for the carrier inhibited from being injected by the injection blocking layer.
Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be used by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.
As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the TFTs, and the matrix signal line section in this embodiment, the layers can be formed in an identical process at a time, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost.
As apparent from the above description, the photoelectric converting elements are not limited to those shown by the embodiment. More specifically, it is only required that there are the first electrode layer, the insulating layer for blocking the movement of holes and electrons, the photoelectric converting semiconductor layer, and the second electrode layer, in addition to the injection blocking layer for blocking injection of holes into the photoelectric converting semiconductor layer between the second electrode layer and the photoelectric converting semiconductor layer. In addition, the photoelectric converting semiconductor layer only needs to have a photoelectric converting function of generating electron-hole pairs due to incident light. As for a layer structure, not only a single layer structure, but a multiple layer structure can be used and its characteristics can be altered repeatedly.
In the same manner, the TFTs each only need to have a gate electrode, a gate insulating layer, a semiconductor layer in which channels can be formed, an ohmic contact layer, and a main electrode. For example, the ohmic contact layer can be a p-layer. If it is so, a hole can be used as a carrier by reversing a control voltage of the gate electrode.
Additionally in the same manner, the capacitors each only need to have a lower electrode layer, a middle layer including an insulating layer, and an upper electrode layer, for example, they need not be especially separated from the photoelectric converting elements or the TFTs and it is possible to have a configuration in which they also serve as the electrode section for the photoelectric converting elements.
Further, the insulating substrate need not be always an insulator, and it can be a conductor or a semiconductor on which an insulator is laid.
In addition, since the photoelectric converting element itself has a function of accumulating charges, it is possible to obtain an integrated value of light information for a certain period without specific capacitors.
[16th embodiment]
As for a configuration of a photoelectric converting section, the configuration shown in
Next, how to drive the photoelectric converter of this embodiment is explained by using
An individual electrode having an identical order in each block of the photoelectric converting elements S1 to S9 is connected to one of common lines 1,102 to 1,104 via the transfer-TFTs T1 to T9. More specifically, the transfer-TFTs T1, T4, and T7 which belong to a first group of each block are coupled to the common line 1,102, the transfer-TFTs T2, T5, and T8 which belong to a second group of each block are to the common line 1,103, and then the transfer-TFTs T3, T6, and T9 which belong to a third group of each block are to the common line 1,104. The common lines 1,102 to 1,104 are coupled to an amplifier 1,126 via switching transistors T100 to T120, respectively.
Further in
Each gate electrode for the switching transistors CT1 to CT3 is coupled to a terminal 1,116 via each common line. Therefore, by setting the terminal 1,116 to a high level to turn on the switching transistors CT1 to CT3, remaining charges of the common lines 1,102 to 1,104 are discharged to GND for charge initialization. Further in
Next, the operation of this embodiment is described in time series below.
If signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored in refresh capacitors C1 to C9 and their stray capacitance depending on its intensity. Then, when a high level is output from a first parallel terminal of the shift register 1,106 [(a) in FIG. 40] and the transfer-TFTs T1 to T3 are turned on, the charges stored in the refresh capacitors C1 to C3 and the stray capacitance are transferred to common capacitors C100 to C120. After the transfer-TFTs T1 to T3 are turned on, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on [(j) to (1) in FIG. 40]. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126. Then, a terminal 1,116 is set to a high level [(m) in FIG. 40] and switching transistors CT1 to CT3 are turned on to initialize the potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, a high level is output from a second parallel terminal of the shift register 1,106 [(d) in FIG. 40] and it increases potential across the refresh capacitors C1 to C3. And then, holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403. Simultaneously with this, the transfer-TFTs T4 to T6 in the second block are turned on [(b) in FIG. 40] to transfer the signal charges stored in the refresh capacitors C4 to C6 and the stray in the second block to common capacitors C100 to C120. In the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107 [(j) to (1) in FIG. 40] and light signals of the second block stored in the common capacitors C100 to C120 are sequentially read out, then the potential of the common capacitors C100 to C120 is initialized by the switching transistors CT1 to CT3 [(m) in FIG. 40].
Next, after potential of the common electrode for the refresh capacitors C1 to C3 in the first block becomes a low level, a high level is output from a third parallel terminal of the shift register 1,106 [(g) in FIG. 40] and the G electrode reset-TFTs R1 to R3 are turned on to initialize the potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. At the same time, potential across the refresh capacitors C4 to C6 in the second block goes up [(e) in FIG. 40]. Further at this point, the transfer-TFTs T7 to T9 in the third block are also turned on [(c) in FIG. 40] and it starts a transfer of the signal charges stored in the refresh capacitors C7 to C9 in the third block and the stray capacitance to common capacitors C100 to C120. Then, in the same manner as for the first and second blocks, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 107 [(j) to (1) in FIG. 40] to read out light signals in the third block stored in the common capacitors C100 to C120 sequentially. After that, the potential of the common capacitors C100 to C120 is initialized by the switching transistors CT1 to CT3 [(m) in FIG. 40].
In the same manner, afterward, the G electrode reset-TFTs R4 to R6 in the second block are turned on by an output of a high level from a fourth parallel terminal of the shift register 1,106 [(h) in FIG. 40]. At the same time, potential across the refresh capacitors C7 to C9 in the third block goes up [(f) in FIG. 40]. After that, a high level is output from a fifth parallel terminal of the shift register 1,106, which turns on the G electrode reset-TFT R7 to R9 in the third block [(i) in FIG. 40].
Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.
The above explanation is given for the operation of the photoelectric converter including nine photoelectric converting elements divided to three blocks for a sensor array for a single line. For reading other lines, the charge transfer operation and the light signal read operation are performed repeatedly in the same manner. As explained in this embodiment by using
In addition, in the above explanation of this embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the above embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in this embodiment.
Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.
As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the capacitors, the TFTs, and the matrix line section in this embodiment, the layers can be formed in an identical process at a time, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost. In addition, a conventionally used refresh power supply can be reduced, which is effective to produce a high signal-to-noise ratio and low cost photoelectric converter. Furthermore, a plurality of photoelectric converting elements are divided into blocks and two or more operations in other blocks (for example, a signal transfer operation, a sensor refresh operation, and a potential reset operation) can be driven simultaneously by an identical driving line, which makes it possible to achieve a further higher yielding ratio and lower cost photoelectric converter due to speedup of the operation and miniaturization of the apparatus.
[17th embodiment]
Referring to
Now, using
In the refresh operation of the photoelectric converting section, the TFT 1,700 is shifted from an off state to an on state by a Pc high potential (also referred to as “high level”hereinafter) pulse and the power supply 1,115 applies positive potential to the electrode G. Positive potential is applied to the electrode D by the power supply 114, therefore, positive potential is applied to potential VDG of the electrode D opposite to the electrode G. Then, a part of holes in the photoelectric converting section 100 are swept out to the electrode D for refreshment. Next, the TFT 1,400 is shifted from an off state to an on state by a Pd high-level pulse and GND potential is applied to the electrode G. At this point, larger positive potential is applied to VDG, and the photo-electric converting section 100 starts a photoelectric converting operation after inrush current flows. Then, the TFT 1,400 is turned off by a Pd low potential (also referred to as “low level” hereinafter) pulse and the electrode G is grounded via the charge storage capacitor 1,800. If signal light is incident on the photoelectric converting section 100, corresponding current flows out of the electrode G and the potential of the electrode G is increased. In other words, incident light information is stored in a capacitance of the electrode G as electric charges. After a certain storage time, the transfer-TFT 1,300 is shifted from an off state to an on state by a Pb high-level pulse and the stored charges flow to the capacitor 1,124. The quantity of the charges is proportional to an integrated value of the current flowing out of the photoelectric converting section 100 in the photoelectric converting operation, in other words, it is detected by the detecting means through the operational amplifier 1,126 as a total quantity of the incident light. It is desirable that the potential of the capacitor 1,124 is initialized to GND potential by a Pa high-level pulse from the TFT 1,125 before this transfer operation. When the transfer-TFT 1,300 is turned off, the refresh-TFT 1,700 is turned on by a Pc high-level pulse, and then the sequential operation is repeated afterward.
Accordingly, a photoelectric conversion can be performed with a high signal-to-noise ratio and superior characteristics.
[18th embodiment]
A configuration in
In this embodiment, a refresh means can include a TFT 1,700, a means for applying a high-level pulse Pc, a power supply 1,115, and a power supply 1,114.
Further, a signal detecting section can include a detecting means enclosed by a dashed line in
Next, referring to
In
Next, a Pd G electrode reset pulse rises and the electrode G of the photoelectric converting section 100 is grounded to GND, all of some electrons remaining in the i-layer flow out to the electrode D. Then, the Pd G electrode reset pulse falls. Signal charges begin to be stored from the Pd pulse fall, wherein a charge storage electrode for the storage capacitor 1,800 is the electrode G and an electrode to be grounded is the electrode D, therefore, an energy band of the i-layer 4 in the storage capacitor 1,800 is almost flat showing so-called a flat-band condition. Generally, zero or a small positive voltage is applied to a side of an insulating layer to make a flat-band condition of an MIS-type capacitor as so-called a flat-band voltage. Accordingly, if the flat-band voltage is zero, the capacitor 1,800 is not put in a depression state from a start of the charge storage to its termination as mentioned above. If the flat-band voltage is a small positive voltage, the storage capacitor 1,800 can be used not in the depression state, but in an accumulation state from the start of the charge storage to its termination by inserting a power supply having a voltage equivalent to or greater than the positive flat-band voltage between a G electrode reset-TFT 1,400 and the GND in FIG. 42. In other words, there occurs no leak current which flows via a storage capacitor 1,800 in the photoelectric converter described by using FIG. 41. Accordingly, almost all the electric charges stored in the storage capacitors and other stray capacitance are charges generated by signal light incident on the photoelectric converting section 100, and it is possible to obtain information with a high signal-to-noise ratio by reading its signal voltage. A signal detecting element within a rectangular range indicated by a dashed line in
In this embodiment, as described above, it is possible to use the signal storage capacitor always in the accumulation state by storing signal charges in the electrode G in the insulating layer 70 for the signal storage capacitor, therefore, there occurs apparently almost no leak current caused by a leakage of signal charges through the signal charge storage capacitor, which makes it possible to provide a further higher signal-to-noise ratio photoelectric converter.
[19th embodiment]
The 19th embodiment of the present invention is described below by using
In
Referring to
In
Next, how to drive the photoelectric converter of the 19th embodiment is described below by using the circuit diagram.
In
Further in
In this embodiment, photoelectric converting means include TFTs R1 to R9, a shift register 1,109, and a power supply 114, and refresh means include TFTs F1 to F9, a shift register 1,108, a power supply 1,115, and a power supply 1,114. Further, a signal detecting section includes a detecting means enclosed by a dashed line in
Next, the operation of the 19th embodiment is described in time series.
If signal light is incident on the photoelectric converting elements S1 to S9 first, electric charges are stored in the storage capacitors D1 to D9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance depending on its intensity. At this point, as mentioned for the 18th embodiment, electrons and holes in each i-layer of the storage capacitors D1 to D9 do not flow out to the electrode G since the electrode G in the insulating layer side is a charge storage electrode, therefore, apparent leak current does not occur in the storage capacitors D1 to D9. Then, when a high level is output from a parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the storage capacitors D1 to D3, the capacitive components, and the stray capacitance are transferred to the common capacitors C100 to C120. Subsequently, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.
After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 to turn on the refresh-TFTs F1 to F3 and it increases potential of the electrode G for the photoelectric converting elements S1 to S3. Then, a part of holes in the photoelectric converting elements S1 to S3 are swept out to the common power supply line 1,403.
Next, a high level is output from a first parallel terminal of a shift register 1,109 and the reset-TFTs R1 to R3 are turned on, which initializes potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the storage capacitors D4 to D6, the equivalent capacitive components of the photoelectric converting elements S4 to S6, and their stray capacitance in the second block to the common capacitors C100 to C120. After that, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential readout of light signals of the second block stored in the common capacitors C100 to C120.
Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.
Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.
As explained in this embodiment by using
In addition, in the above explanation of the 18th or 19th embodiment, the configuration permits an inverse relationship between the holes and the electrons. For example, the injection blocking layer can be a p-layer. If it is so, the same operational result as for the above embodiment can be achieved by reversing the directions for applying the voltages and the electric fields and arranging other parts in the same manner in the 18th or 19th embodiment.
Although a one-dimensional line sensor is explained in the 19th embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment.
As mentioned above, since an identical layer structure is used for the photoelectric converting elements, the storage capacitors, the TFTs and the matrix signal line section, the layers can be formed in an identical process at a time in the 19th embodiment in addition to the effect of the 18th embodiment, therefore, miniaturization and a high yielding ratio can be achieved, which makes it possible to produce a high signal-to-noise ratio photoelectric converter at low cost.
[20th embodiment]
The 20th embodiment is described below by using
In
Using
In
Now, how to drive the photoelectric converter of this embodiment is described below by using the circuit diagram.
In
An individual electrode having an identical order in each block of the photoelectric converting elements S1 to S9 is connected to one of common lines 1,102 to 1,104 via the transfer-TFTs T1 to T9. More specifically, the transfer-TFTs T1, T4, and T7 which belong to a first group of each block are coupled to the common line 1,102, the transfer-TFTs T2, T5, and T8 which belong to a second group of each block are to the common line 1,103, and then the transfer-TFTs T3, T6, and T9 which belong to a third group of each block are to the common line 1,104. The common lines 1,102 to 1,104 are connected to an amplifier 1,126 via switching transistors T100 to T120, respectively.
Further in
In this embodiment, photoelectric converting means include TFTs R1 to R9, a shift register 1,109, and a power supply 114 and refresh means include the capacitors C1 to C9, a shift register 1,108, and a power supply 114. Further, a signal detecting section include detecting means enclosed by a dashed line in
Next, the operation of this embodiment is described in time series below.
First, if signal light is incident on the photoelectric converting elements S1 to S9, electric charges are stored in storage/refresh capacitors C1 to C9, equivalent capacitive components of the photoelectric converting section 100, and their stray capacitance depending on its intensity. At this point, as mentioned for the 18th embodiment, electrons and holes in each i-layer of the storage/refresh capacitors C1 to C9 do not flow out to the electrode G since the electrode G in the insulating layer side is a charge storage electrode, therefore, apparent leak current does not occur in the storage/refresh capacitors C1 to C9. Then, when a high level is output from a parallel terminal of the shift register 1,106 and the transfer-TFTs T1 to T3 are turned on, the charges stored in the storage/refresh capacitors C1 to C3, the capacitive components, and the stray capacitance are transferred to the common capacitors C100 to C120. Subsequently, a high level output from a shift register 1,107 is shifted and switching transistors T100 to T120 are sequentially turned on. This starts sequential readout of light signals of the first block transferred to the common capacitors C100 to C120 via the amplifier 1,126.
After the transfer-TFTs T1 to T3 are turned off, a high level is output from a first parallel terminal of the shift register 1,108 and it increases potential across the storage/refresh capacitors C1 to C3 or potential of the electrode G for the photoelectric converting elements S1 to S3. Then, holes in the photoelectric converting elements S1 to S3 are swept out to a common power supply line 1,403.
Next, turning on the reset-TFTs R1 to R3 for which a high level is output from a first parallel terminal of a shift register 1,109 initializes potential of the electrode G for the photoelectric converting elements S1 to S3 to GND. Then, a Pa pulse triggers initialization of potential of the common capacitors C100 to C120. When the potential of the common capacitors C100 to C120 is completely initialized, the shift register 1,106 shifts data and a high level is output from a second parallel terminal. This turns on the transfer-TFTs T4 to T6, and it starts a transfer of signal charges stored in the storage/refresh capacitors C4 to C6, the equivalent capacitive components of the photoelectric converting elements S4 to S6, and the stray capacitance in the second block to the common capacitors C100 to C120. Then, in the same manner as for the first block, the switching transistors T100 to T120 are sequentially turned on by a shift of the shift register 1,107, and it starts sequential readout of light signals of the second block stored in the common capacitors C100 to C120.
Also for the third block, the charge transfer operation and the light signal read operation are performed in the same manner.
Like this, signals for a line is completed to be read in a horizontal scanning direction on the original copy through a series of the operations from the first block to the third block, and then the read signals are output in an analog mode according to a reflectance degree of the original copy.
In this embodiment, the photoelectric converting elements, the storage/refresh capacitors, the transfer-TFTs, the reset-TFTs, and the matrix signal line section have an identical layer structure consisting of five layers including the first electrode layer, the insulating layer, the i-layer, the n-layer and the second electrode layer, but all the elements do not need to have the same layer structure necessarily. It is only required that at least the photoelectric converting elements and the storage/refresh capacitors have this (MIS) structure and that other elements each have a layer structure which allows it to serve as each element. If they have the identical layer structure, however, it is more effective to improve an yielding ratio and to lower the cost.
Although a one-dimensional line sensor is explained in this embodiment, it should be understood that a two-dimensional area sensor can be achieved by arranging a plurality of line sensors and that the above configuration permits a photoelectric converter for reading the same size of copies as for an information source such as an X-ray camera by using a block driving method described in the above embodiment, in the same manner as for the 19th embodiment.
In this embodiment, it is possible that the storage capacitors have a refresh function in addition to the effects of the 18th and 19th embodiments as mentioned above, therefore, due to miniaturization and a high yielding ratio, a lower cost photoelectric converter can be achieved.
[21st embodiment]
In
In addition, the photoelectric converter shown in
Next, the photoelectric converter according to this embodiment will be described.
Shift registers SR1 and SR2 first applies a Hi (High voltage) to control lines g1 to gm and sg1 to sgn. Thus, the transfer-TFTs T11 to Tmn and switches M1 to M3 are turned on to be in a conductive state, and then, the electrodes D of all photoelectric converting elements S11 to Smn become GND potential (because an input terminal of an integral detector Amp. is designed to be GND potential). At the same time, the refresh control circuit RF outputs the Hi to turn on the switch Swg so that the electrodes G of all the photoelectric converting elements S11 to Smn are turned by the refresh power supply Vg to negative potential whose magnitude of the absolute value is small. As a result, all the photoelectric converting elements S11 to Smn are turned to a refresh mode to be refreshed. The refresh control circuit RF next outputs a Lo (Low voltage signal) to turn on the switch SWs so that the electrodes G of all the photoelectric converting elements S11 to Smn are turned by the read power supply Vs to negative potential whose magnitude of the absolute value is large. As a result, all the photoelectric converting elements S11 to Smn are turned to a photoelectric conversion mode to initialize the capacitors C11 to Cmn simultaneously.
As described above, in the refresh mode of this embodiment, the potential of the electrodes G is set to the negative potential in comparison with the potential of the electrodes D and the potential of the electrodes G does not reach a flat-band voltage VFB. Accordingly, as described in the foregoing embodiments, electrons can not reach the interface between the insulating layer and the photoelectric converting semiconductor layer and this makes it possible to inhibit the electrons from coming in and out of the interface defects. For this reason, inrush currents can be reduced and a photoelectric converter of high signal-to-noise ratio can be realized.
In this embodiment, while each electrode D of the photoelectric converting elements is connected to the TFT and each electrode G of the photoelectric converting elements is connected commonly, the electrode G may be connected to the TFT and the electrode D may be connected commonly. In this case, the same operations can be performed by reversing the polarities of Vg and Vs.
Also in this embodiment, while the number of pixels has been defined as mxn, in actuality, it can be selected properly in accordance with system structure. For example, when pixels are arranged on one substrate of 20 cm×20 cm size, assuming that n is 2,000 and m is 2,000, the pixels of m×n numbers, i.e., the photoelectric converting elements of 4,000,000 numbers are arranged with a density of 100 μm pitches on the substrate.
In
The photoelectric converting element and the TFT are constituted in plural numbers inside an a-Si sensor substrate 6011 and connected with flexible circuit substrates 6010 on which shift registers SR1 and integrated circuits IC for detection are mounted. The opposite side of the flexible circuit substrates 6010 are connected with a PCB1 or a PCB2. A plurality of the a-Si sensor substrates 6011 are adhered onto a base 6012 so as to constitute a large-sized photoelectric converter. A lead plate 6013 is mounted under the base 6012 so as to protect memories 6014 in a processing circuit 6018 from X rays. A phosphor 6030 such as Cs1 or the like is coated on or adhered to the a-Si sensor substrate 6011. On the basis of the same principle as the X-ray detecting method described above in
X rays 6060 emitted from an X-ray tube 6050 are transmitted through the chest 6062 of a patient or an examinee 6061 to be incident to a photoelectric converter 6040 on which a phosphor has been mounted. The incident X rays include the internal information of the patient. Here, the phosphor emits light in response to the incident X rays and the emitted light is photoelectrically converted to obtain the electric information. The electric information is then converted to be digitalized and an image on the electric information is processed by an image processor 6070 to be able to observe on a display 6080 in a control room. This information can be transferred to a remote place, such as a doctor room located in other place or the like, by way of a transmission means such as a telephone line 6090 and displayed on a display 6081 or stored in a storage means such as an optical disk, and this makes it possible to be diagnosed by a doctor in a remote place. Also, this information can be recorded on a film 6110 by a film processor 6100.
[Effect]
As described above, the present invention can provide a photoelectric converter having a high signal-to-noise ratio and stable characteristics and a system having the above photoelectric converter.
Also, the present invention can provide a photoelectric converter having a high yield and high productivity.
In addition, the present invention can provide a photoelectric converter which can be composed in the same process as for the TFT, will not complicate fabrication processes, and can be fabricated at a low cost, its driving method and a system including the above photoelectric converter.
According to the present invention, the photoelectric converting section (photoelectric element) in the photoelectric converter can detect the incident amount of light only in one place of the injection blocking layer, so that the processes can be easily optimized, the yield can be improved and the manufacturing cost can be also reduced. Accordingly, a photoelectric converter of a high signal-to-noise ratio and low cost can be provided. Also, according to the present invention, any tunnel effect or Schottky barrier is not used in the interfaces between the first electrode layer, the insulating layer and the photoelectric converting semiconductor layer, so that the electrode material can be selected freely as well as the thickness of the insulating layer or other control. Furthermore, the photoelectric element matches well with the switching and capacitive elements such as thin-film field effect transistors (TFT), both being formed at the same time as the photoelectric element, and can be formed simultaneously as the common films with the TFTs due to the same film structure. The film structure important to the photoelectric element and the TFTs can be also formed in an identical vacuum at the same time. Accordingly, an excellent photoelectric converter of a further high signal-to-noise ratio and low cost can be provided.
The present invention can also provide a photoelectric converter having complex functions with a simplified structure since the photoelectric element itself has a property to store optical information as carriers, with simultaneously flowing the current at a real-time. Further, the capacitor of the above photoelectric converter includes an insulating layer in its middle layer and can be formed with a preferable properties, and this makes it possible to provide a photoelectric converter of high functions so that the integral values of the optical information obtained in the photoelectric element can be output with a simplified structure.
Furthermore, according to the present invention, the refresh operation of the photoelectric element can be performed through the capacity of the capacitor or the like and this makes it possible to generate an inrush current at the instant the applied voltage was dropped down. In comparison with the case the refresh operation is performed by using the TFT, this reduces the stored inrush currents extremely, therefore, an excellent photoelectric converter of a further high signal-to-noise ratio and low cost can be provided.
Furthermore, in the refresh operation of the photoelectric element, for example, if the semiconductor injection blocking layer of the photoelectric element has an n-type structure, i.e., if an electric charge q of carriers inhibited from their injections is positive, electrons can be inhibited from coming in and out of the interface defects generated between the insulating layer and the photoelectric converting semiconductor layer by a condition represented by {(Vrg·q)<(VD·q−VFB·q)}, where the potential of the electrode D is set higher than the potential of the electrode G. On the contrary, if the semiconductor injection blocking layer of the photoelectric element has a p-type structure, i.e., if the electric charge q of carriers inhibited from their injections is negative, electrons can be inhibited from coming in and out of the interface defects generated between the insulating layer and the photoelectric converting semiconductor layer by the condition represented by {(Vrg·q)<(VD·q−VFB·q)}, where the potential of the electrode D is set lower than the potential of the electrode G. Accordingly, an excellent photoelectric converter of a further high signal-to-noise ratio and low cost which can reduce the inrush currents can be provided.
Furthermore, a capacitive element for signal-charge storage is formed by the identical laminating structure with the photoelectric element and the electric charge is stored at the electrode of insulating side of the capacitive element, so that the capacitive element for signal-charge storage can be used in the accumulation state at any time and the apparent leak currents generated by leaking the signal charge through the capacitive element for signal-charge storage can be reduced, thereby providing a photoelectric converter of a high signal-to-noise ratio and low cost.
Furthermore, according to the present invention, a plurality of photoelectric elements are divided into blocks so that the refresh operation in a block and the signal transfer operation in other block can be driven by an identical driving line at the same time. As a result, the read operation can be performed at a high speed and the converter can be decreased in size. Accordingly, a photoelectric converter of a high yield and low cost can be provided.
By utilizing the above photoelectric converter of excellent properties, a facsimile machine or a roentgen (X-ray) scope of a low cost, wide area, high functions and high characteristics can be also provided.
The present invention, however, is not limited to the structures and the embodiments described above, it will be understood that any modification and combination can be realized properly within the scope of the present invention.
Takeda, Shinichi, Itabashi, Satoshi, Kaifu, Noriyuki, Kobayashi, Isao, Mizutani, Hidemasa
Patent | Priority | Assignee | Title |
10332280, | Oct 24 2013 | Canon Kabushiki Kaisha | Information processing apparatus, information processing method, and control apparatus |
10621758, | Oct 24 2013 | Canon Kabushiki Kaisha | Information processing apparatus, information processing method, and control apparatus |
10847568, | Feb 15 2018 | TIANMA JAPAN, LTD. | Image sensor and method of driving image sensor |
7470908, | May 24 2006 | Canon Kabushiki Kaisha | Radiation imaging apparatus and radiation imaging system |
7626156, | Sep 13 2007 | SAMSUNG DISPLAY CO , LTD | Image sensor having plural pixels adjacent to each other in a thickness direction and method for manufacturing the same |
7642517, | May 24 2006 | Canon Kabushiki Kaisha | Radiation imaging apparatus and radiation imaging system |
8138004, | May 20 2005 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device, manufacturing method thereof and semiconductor device |
8207591, | May 20 2005 | Semiconductor Energy Laboratory Co., Ltd. | Photoelectric conversion device |
8519344, | May 24 2006 | Canon Kabushiki Kaisha | Radiation imaging apparatus and radiation imaging system |
Patent | Priority | Assignee | Title |
3598997, | |||
4004148, | Feb 02 1976 | General Electric Company | Accumulation mode charge injection infrared sensor |
4575638, | May 04 1982 | NEC Corporation | Thin film photoelectric converting device |
4675739, | May 04 1984 | ENERGY CONVERSION DEVICES, INC , ECD | Integrated radiation sensing array |
4835507, | Dec 06 1985 | Canon Kabushiki Kaisha | Photosensor array for image processing apparatus |
4908718, | Jul 09 1987 | Canon Kabushiki Kaisha | Image reading apparatus having a light shielding layer arranged on the sides of the substrate and protective layers of a photo sensor |
4922117, | Jun 12 1987 | Canon Kabushiki Kaisha | Photoelectric conversion device having a constant potential wiring at the sides of the common wiring |
4939592, | Jun 12 1987 | CANON KABUSHIKI KAISHA, A CORP OF JAPAN | Contact photoelectric conversion device |
4940901, | Nov 10 1987 | Thomson-CSF | X-ray imaging device |
5043785, | Aug 20 1987 | Canon Kabushiki Kaisha | Photosensor device photodiode and switch |
5184018, | Jan 27 1990 | U.S. Philips Corporation | Sensor matrix |
5225706, | Dec 04 1987 | Thomson-CSF | Matrix of photosensitive elements associating a photodiode or a phototransistor and a storage capacitor |
5491339, | Sep 21 1993 | Kabushiki Kaisha Toshiba | Charged particle detection device and charged particle radiation apparatus |
5780872, | May 17 1988 | Seiko Epson Corporation | Liquid crystal device, projection type color display device and driving circuit |
EP296603, | |||
EP503062, | |||
JP5180945, |
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