Latch-up recovery in quantized feedback DC restorer circuits

Abstract

A method and apparatus for avoiding and or recovering from the latch-up condition in a quantized feedback dc restorer circuit for use in a digital data communication system receiver. An automatic gain control (AGC) circuit controls the level of the received data by comparing the AGC output with a quantized output signal from the dc restorer. A carrier detect circuit detects the presence of data transitions in the quantized output signal, and in the absence of such transitions continuously ramps up the gain of the AGC until such transitions are detected. The carrier detect circuit can be further used to disable, either entirely or partially, the positive feedback path of the dc restorer in the absence of transition in the quantized output signal. The present invention further provides an inherent muting function of the dc restorer output signal in the absence of valid data transitions.

Description

FIELD OF THE INVENTION

The present invention relates to the field of serial digital data communication systems. In particular, the present invention relates to latch-up avoidance and recovery in a serial digital data receiver using a quantized feedback DC restorer.

BACKGROUND OF THE INVENTION

In a digital data communication system the transmitted data is generally attenuated and distorted by the medium and the AC coupling networks through which it is transmitted. This results, among other things, in a loss of the low frequency and DC components in the received data.

To combat this problem, receivers typically include a DC (direct current) restorer to restore or regenerate the low frequency and DC components of the transmitted input, and an automatic gain control (AGC) circuit which automatically changes the gain or amplification of the received input to maintain the level of the amplified signal essentially constant despite variations in input signal strength.

DC restorer circuits are generally implemented as either a clamping DC restorer or a DC restorer based on the principle of quantized feedback (QFB). Both clamping and quantized feedback restorer circuits are described in detail in U.S. Pat. No. 5,426,389, the description of said patent being incorporated herein by this reference. A QFB DC restorer circuit generally exhibits superior noise and jitter performance, however such circuits are susceptible to latching-up if the output of the restorer is in the incorrect state at the onset of data transmission. Prior art methods of overcoming the latch-up problem involve additional start-up circuitry and/or deviations in the QFB structure, and, as a result, require supplementary circuitry and exhibit inferior circuit performance.

Further, an important criteria in designing a QFB DC restorer is the delay which occurs in the feedback loop. Since any delay in the feedback loop of the QFB restorer adversely affects the construction of the signal spectrum at the input of the slicer of the restorer, delay should be kept at a minimum level. In particular, at high data rates, elegant and efficient circuit implementation techniques are critical for keeping the QFB circuit as simple as possible.

SUMMARY OF THE INVENTION

3535′ 40 is in the lower position). In this manner, if the amplifier 41 has a gain of 1 (no control/attenuation) this effectively corresponds to the embodiment shown in FIG. 6. On the other hand, if the amplifier 41 has a gain of 0 (full control/attenuation) this effectively corresponds to the embodiment of FIG. 7.

The embodiment of FIG. 8 therefore provides superior latch-up protection for the QFB DC restorer than does the embodiment of FIG. 6, while still providing a muting function for the QFB output. Thus the embodiment of FIG. 8 represents a compromise or trade-off between latch-up protection and muting control.

As mentioned previously, simplicity of the QFB circuit is crucial in high data rate applications. Any significant delay in the QFB feedback loop deteriorates its performance due to the addition of timing jitter. FIG. 9 shows a preferable basic circuit realization for the QFB DC-restorer of the embodiment of FIG. 6. Referring to FIG. 9, transistors Q3 and Q4 form the slicer 18, while transistors Q5 and Q6 provide the positive feedback. The feedback loop is completed by buffers Q7 and Q8 and two RC low-pass filters consisting of resistor-capacitor pairs R1-C1 and R2-C2 respectively (note that two filters are used due to the differential configuration of the circuit). The same RC filters are employed to realize the feed-forward high-pass filters through their high-pass ports. This guarantees matching between the cut-off frequencies of the high-pass and low-pass filters. The high-pass ports are supplied by the differential input signal (in+, in−) which is fed to the circuit via the bases of buffers Q1 and Q2. The output is taken from the output of the slicer between terminals out+ and out−, as shown in FIG. 9. This circuit can be used directly in the block diagram of FIG. 6.

The circuits of FIGS. 10A and 10B are modified versions of the circuit of FIG. 9, which provide for the option of disabling (entirely or partially) the positive feedback around the QFB loop. This is accomplished by adding a switch to bypass (entirely or partially) the biasing current of transistors Q5 and Q6. In either case, this is achieved by adding a few transistors to the circuit of FIG. 9.

With the addition of transistors Q9 and Q10 in the circuit of FIG. 10A, the positive feedback is entirely disabled if the disable control voltage, “disable”, is more than the threshold voltage Vth. This alteration therefore makes the circuit of FIG. 10A suitable for use in the block diagram of FIG. 7.

Alternatively, a portion of the biasing current can be bypassed. This can be implemented by adding another transistor to the circuit of FIG. 10A. FIG. 10B shows the result, with transistor Q11 added to the circuit of FIG. 10A. The resulting circuit can be used to implement the block diagram of FIG. 8, in which partial disablement of the QFB restorer's positive feedback is desired, as already discussed. In FIG. 10B the partial disablement of the feedback is turned “on” when the disable control voltage, “disable”, is more than the threshold voltage Vth. The extent to which the feedback is disabled is determined by the relative emitter areas of transistors Q10 and Q11, where the amount of disablement equals the ratio of the emitter area of Q11 divided by the sum of the emitter areas of both Q10 and Q11. As will be appreciated by those skilled in the art, by making one or more of the emitter areas of these transistors programmably variable, the circuit of FIG. 8B can be used to provide variable amounts of partial disablement of the QFB DC restorer feedback, as may be required.

Thus, the present invention uses and processes signals which, typically, are already present in the receiver of a data communication system to prevent the latch-up problem in the QFB DC-restorer. This eliminates the overhead of the start-up circuitry. The present invention further provides means of preventing the latch-up problem by exploiting the inherent potentials of the stages preceding the QFB, such as the automatic gain control circuit. This approach again reduces the overhead since such stages are usually present in the system. As a result, the QFB DC restorer used in accordance with the present invention becomes very simple, and hence fast, since either no further latch-up precaution or minimal further precautions are required.

The present invention makes further use of the built-in mute operation of the above embodiments to cut off the output when there is no signal (or when there is a signal which is smaller than the minimum signal the system is designed to handle) at the input of the receiver. This built-in mute function is very valuable, as serial digital data communication systems usually require precautions to be taken in order to avoid suffering from unwanted outputs (such as oscillations or amplified noise) which typically accompany very small input signals. Moreover the present invention is very attractive for use in high data rate communication systems, since, while avoiding latch-up, it can still be designed to minimize delay, depending on the criteria of the specific application.

While preferred embodiments of the present invention have been described, the embodiments disclosed are illustrative and not restrictive, and the scope of the invention is intended to be defined only by the appended claims.

Claims

1. A circuit for receiving an input signal and providing a quantized output signal in response, said quantized output signal being at either a first level or a second level, and said input signal being substantially at either said first level or said second level, said circuit comprising:

(a) an automatic gain control (AGC) circuit for providing a gain signal which processes said input signal to output a controlled signal having a constant amplitude at either said first level or said second level, said AGC circuit being operative in a first mode to provide said gain signal in response to the difference between the level of said controlled signal and the level of said quantized output signal;

(b) a restorer circuit coupled to said AGC circuit for receiving said controlled signal and for providing said quantized output signal in response;

(c) a carrier detect circuit coupled to said AGC circuit and having an input for receiving said quantized output signal, said carrier detect circuit providing a detection signal for indicating the presence of a transition in the level of said quantized output signal, said detection signal being coupled to said AGC circuit;

2. A circuit according to claim 1 wherein when said AGC circuit is operative in said second mode, said gain signal increases in a substantially linear manner until said gain value reaches said predetermined level.

3. A circuit according to claim 2 wherein said predetermined level corresponds to a gain saturation level of said AGC circuit.

4. A circuit according to claim 1 wherein said restorer circuit comprises:

(a) a high-pass filter circuit for receiving said controlled signal and providing a high-pass filtered controlled signal in response;

(b) a low-pass filter circuit for receiving said quantized output signal and providing a low-pass filtered quantized output signal in response, said low pass filter circuit providing a feedback path for said low-pass filtered quantized output signal;

(c) a summer for adding said high-pass filtered controlled signal with said low-pass filtered quantized output signal to provide a slicer input signal; and

(d) a slicer circuit for comparing said slicer input signal to a slicer reference signal and providing said quantized output signal at a slicer output terminal in response.

5. A circuit according to claim 4 wherein the time constant of said high pass circuit and the time constant of said low pass circuit are equal.

6. A circuit according to claim 5 wherein the voltage swing of said controlled signal and the voltage swing of said quantized output signal are equal.

7. A circuit according to claim 4 wherein said low pass filter circuit includes a disabling circuit responsive to said detection signal or a version thereof, so that said disabling circuit disables said feedback path during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.

8. A circuit according to claim 7 wherein said disabling circuit comprises a feedback enable switch coupled between said slicer output terminal and said summer, said switch being operative in an open or closed position in response to said detection signal or a version thereof.

9. A circuit according to claim 4 wherein said low pass filter circuit includes a disabling circuit responsive to said detection signal or a version thereof, so that said disabling circuit partially disables said feedback path during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.

10. A circuit according to claim 9 wherein said disabling circuit comprises a feedback control amplifier coupled between said slicer output terminal and said summer, said feedback control amplifier having a feedback control gain with a value in the range of 0 to 1, said value corresponding to the extent that said feedback path may be partially disabled, said disabling circuit further comprising a feedback enable switch being operative, in response to said detection signal or a version thereof, in a first position to insert said feedback control amplifier in said feedback path and in a second position to bypass said feedback control amplifier in said feedback path.

11. A circuit according to claim 10 wherein said feedback control gain value is changeable.

12. A circuit according to claim 1, 7, or 9 wherein said carrier detect circuit comprises:

(a) a high-pass filter circuit for receiving said quantized output signal and providing a high pass filtered quantized output signal in response;

(b) a peak detector circuit for receiving said high pass filtered quantized output signal and providing a peak signal representative of the peak amplitude of said high pass filtered quantized output signal in response; and

(c) a comparator circuit for comparing said peak signal to a carrier detect threshold signal and outputting said detection signal in response.

13. A method for avoiding a latch-up condition in the output of a digital data communication receiver which receives an input signal and provides a quantized output signal in response, said quantized output signal being at either a first level or a second level, and said input signal being substantially at either said first level or said second level, said receiver comprising an automatic gain control circuit, a quantized feedback dc restorer circuit, and a carrier detect circuit, said method comprising the steps of:

(a) processing the input signal in response to a gain signal to provide a controlled signal having a constant amplitude at either said first level or said second level, said gain signal being responsive in a first manner to the difference between the level of said controlled signal and the level of said quantized output signal;

(b) restoring the dc and low frequency components of said controlled signal to provide a quantized output signal; and

(c) detecting the presence of a transition in the level of said quantized output signal;

14. A method according to claim 13 wherein when said gain signal is responsive in said second manner, said gain signal increases substantially linearly until said gain signal reaches said predetermined value.

15. A method according to claim 14 wherein step (b) further comprises the steps of:

high-pass filtering said controlled signal to provide a high-pass filtered controlled signal;

low-pass filtering said quantized output signal to provide a low-pass filtered quantized output signal;

adding said low-pass filtered quantized output signal to said high-pass filtered controlled signal to provide a slicer input signal; and

comparing said slicer input signal a slicer reference signal and providing said quantized output signal in response.

16. A method according to claim 15 wherein said step of low-pass filtering is disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.

17. A method according to claim 15 wherein said step of low-pass filtering is partially disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.

18. A circuit for receiving an input signal and providing a quantized output signal in response, said circuit comprising:

(a) an amplifier for providing a controlled signal in response to said input signal and a gain signal;

(b) a restorer circuit coupled to said amplifier, said restorer circuit including an internal feedback path;

(c) a carrier detect circuit having an input for receiving said quantized output signal, said carrier detect circuit providing a first detection signal and a second detection signal for indicating the presence of a transition in the level of said quantized output signal;

(d) an automatic gain control (AGC) circuit coupled to said amplifier, said restorer circuit and said carrier detect circuit for providing said gain signal in response to said controlled signal, said quantized output signal and said first detection signal; and

(e) a feedback disabling circuit coupled to said carrier detect circuit and said restorer circuit for controllably enabling and disabling said internal feedback path in response to said second detection signal.

19. A circuit according to claim 18, wherein said restorer circuit comprises:

(i) a high-pass filter circuit for receiving said controlled signal and providing a high-pass filtered controlled signal in response;

(ii) a low-pass filter circuit for receiving said quantized output signal and providing a low-pass filtered quantized output signal in response, said low-pass filter circuit providing said internal feedback path for said low-pass filtered quantized output signal;

(iii) a summer for adding said high-pass filtered controlled signal with said low-pass filtered quantized output signal to provide a slicer input signal; and

(iv) a slicer circuit for comparing said slicer input signal to a slicer reference signal and providing said quantized output signal at a slicer output terminal in response.

20. A circuit according to claim 19, wherein the time constant of said high-pass filter circuit and the time constant of said low-pass filter circuit are equal.

21. A circuit according to claim 20, wherein said feedback disabling circuit includes a switch coupled between said slicer circuit and said summer, said switch having a first state and a second state, wherein in said first state, said switch is fully open to disable said internal feedback path and wherein in said second state, said switch is fully closed to enable said internal feedback path.

22. A circuit according to claim 21, wherein said switch is in said first state when said second detection signal does not indicate the presence of a transition and is in said second state when said second detection signal indicates the presence of a transition.

23. A circuit according to claim 20, wherein said feedback disabling circuit includes a feedback control amplifier coupled between said slicer circuit and said summer, said feedback control amplifier having a gain between 0 and 1, wherein said gain corresponds to the extent to which said internal feedback path is enabled.

24. A circuit according to claim 23, wherein said feedback disabling circuit further includes a switch coupled between said slicer output and said summer, said switch being coupled in parallel with said feedback control amplifier, said switch having a first state and a second state, wherein in said first state, said switch inserts said feedback control amplifier into said internal feedback path and wherein in said second state, said switch bypasses said feedback control amplifier from said internal feedback path.

25. A circuit according to claim 24, wherein said switch is in said first state when said second detection signal does not indicate the presence of a transition and is in said second state when said second detection signal indicates the presence of a transition.

26. A circuit according to any one of claims 23, 24 or 25, wherein said gain of said feedback control amplifier may be varied.

27. A circuit according to claim 18, wherein said first detection signal and said second detection signal are identical.

28. A circuit according to claim 18, wherein said second detection signal is a version of said first detection signal.

29. A circuit according to claim 18, wherein said AGC may be operative in a first mode when said first detection signal indicates that there is a transition in the level of said quantized output signal or in a second mode when said first detection signal indicates that there is no transition in the level of said quantized output signal, and wherein in said first mode, said gain signal corresponds to a difference between said controlled signal and said quantized output signal and wherein in said second mode said gain signal is continually increased, at least to a predetermined level.

30. A circuit according to claim 29, wherein said quantized output signal may be at either a first level or a second level and wherein said input signal is generally at either said first level or said second level.

31. A circuit according to claim 29, wherein when said AGC circuit is in said second mode, said gain signal increases in a substantially linear manner until said gain value reaches said predetermined level.

32. A circuit according to claim 29, wherein said predetermined level corresponds to a gain saturation level of said AGC circuit.

33. A circuit according to claim 29, wherein the voltage swing of said controlled signal and the voltage swing of said quantized output signal are equal.

34. A circuit according to claim 18 or 29 wherein said carrier detect circuit comprises:

(a) a high-pass filter circuit for receiving said quantized output signal and providing a high pass filtered quantized output signal in response;

(b) a peak detector circuit for receiving said high pass filtered quantized output signal and providing a peak signal representative of the peak amplitude of said high pass filtered quantized output signal in response; and

(c) a comparator circuit for comparing said peak signal to a carrier detect threshold signal and outputting said detection signal in response.

35. A method for avoiding a latch-up condition in the output of a digital data communication receiver which receives an input signal and provides a quantized output signal in response, said quantized output signal being at either a first level or a second level, and said input signal being substantially at either said first level or said second level, said receiver comprising an automatic gain control circuit, a quantized feedback dc restorer circuit, a carrier detect circuit, and a feedback disabling circuit, said method comprising:

(a) processing the input signal in response to a gain signal to provide a controlled signal having a constant amplitude at either said first level or said second level, said gain signal being responsive in a first manner to the difference between the level of said controlled signal and the level of said quantized output signal;

(b) selectively restoring the dc and low frequency components of said controlled signal to provide said quantized output signal by isolating said dc and low frequency components in said quantized output signal and summing said isolated dc and low frequency components into said controlled signal or a version thereof through a feedback path which may be controllably enabled or disabled; and

(c) detecting the presence of a transition in the level of said quantized output signal,

36. A method according to claim 35, wherein step (b) is accomplished by:

(i) high-pass filtering said controlled signal to provide a high pass filtered controlled signal;

(ii) selectively low-pass filtering said quantized output signal through said feedback path to provide a low-pass filtered quantized output signal,

(iii) adding said low-pass filtered quantized output signal to said high-pass filtered controlled signal to provide a slicer input signal; and

(iv) comparing said slicer input signal to a slicer reference signal and providing said quantized output signal in response.

37. A method according to claim 36, wherein when said gain signal is responsive in said second manner, said gain signal increases substantially linearly until said gain signal reaches said predetermined value.

38. A method according to claim 36, wherein said feedback path is partially disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.

39. A method according to claim 36, wherein said feedback path is completely disabled during periods when said detection signal indicates that there are no transitions in the level of said quantized output signal.