A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies.
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0. 3. A method for fabricating a multiple-die, low-profile semiconductor device, comprising:
a. providing a lead frame having a lead frame paddle and a plurality of lead fingers;
b. affixing to said paddle a first die having a plurality of first die-bonding pads;
c. connecting bond wires between each of said plurality of first die-bonding pads and corresponding lead fingers of said plurality of lead fingers by way of a low-loop wire bond on each of said plurality of first die-bonding pads and a wire bond on each of said corresponding lead fingers;
d. affixing to said first die, following said connecting bond wires, a second die having a plurality of second die-bonding pads;
e. connecting bond wires between each of said plurality of second die-bonding pads and corresponding lead fingers of said plurality of lead fingers by way of a low-loop wire bond on each of said plurality of second die-bonding pads and a wire bond on each of said corresponding lead fingers; and
f. affixing two additional dies above said second die.
0. 1. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first diebonding pads, said wire bond having a wire height above the bonding pad of about 0.006 inches, and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. two additional dies affixed above the second die by additional subsequent layers of adhesive of about 0.008 inches and having additional thin wires bonded to additional bonding pads and lead fingers; and
g. an encapsulated layer surrounding all dies, adhesive layers, and thin wires wherein a total encapsulated-package height is about 0.110 inches.
0. 2. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 to 0.005 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads, said low-loop wire ball bond having a wire height above the bonding pads of about 0.006 inches and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 to 0.010 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. an encapsulated layer surrounding all die adhesive layers and thin wires wherein a total encapsulation-layer height is about 0.070 inches.
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Each of the die bonding pads 26 in double rows are electrically connected to multiple lead fingers 28A, 28B, 28C . . . 28N by thin (0.001 inch) gold or aluminum wires 30A, 30B, 30C . . . 30N; gold being the preferred metal. For clarity, only part of the 18 bonding pads, wires, and fingers are shown. The critical bonding method used at the die end pad 26 is an ultrasonic ball bond bond, as named by the shape of the bond as at 32. This first-installed bond and formed gold wire are low-loop wire bonds as seen at critical dimension 34, as will be described later.
The other end of gold wires 30 are attached to the lead fingers by a wedge bond 36, which is also an ultrasonic bond, indicating the use of ultrasonic energy to heat the wire 30 as it is compressed against the lead finger 28. The wedge bond is not used on the die because the bonding machine contacts the bonding surface and could damage this critical surface. The lead fingers may be formed upward as at 38 to permit the use of shorter wires 30.
Paddle 14 which supports the stack is attached to the lead frame typically at four corners as at 40 and also typically, in this application, would have a downset from the lead frame and lead fingers 28 as at dimension 42. The stack is finally encapsulated by a plastic or ceramic at 44.
A dimensional analysis is provided by referring to FIG. 2.
By careful control of layer thicknesses, it is possible to fabricate a four-stack die device having an overall height 46 of about 0.110 inches inch which is the same height as a current single die. Starting at the bottom, the encapsulation thickness 48 is between 0.010 and 0.012 inches inch. The paddle 74 14 thickness 50 can be between 0.005 and 0.010 inches inch and is a matter of choice. The controlled adhesive-layer thickness 52 can be from 0.001 to 0.005 inches inch. The individual dies 20, 18, 16, and 12 each have a thickness 54 of 0.012 inches inch and the critical controlled, adhesive-layer thicknesses 56 between each die are between 0.008 and 0.010 inches inch. These thin layers have to be slightly greater than the low-loop wire dimension 34, which is about 0.006 inches inch. Finally, the top encapsulation thickness 58 is between 0.010 and 0.012 inches inch so as to cover the top loop.
Thus, it can be seen by carefully controlling and minimizing the adhesive layer thicknesses 56, the top and bottom encapsulation thicknesses 48 and 58, and the paddle adhesive layer 52 that it is possible to have an overall height between 0.108 and 0.110 inches inch overall for the four-stack die.
If the looser tolerances were used for a two-stack die, the height at 60 would be between 0.058 and 0.073 inches inch and for a three-die stack it would be from 0.078 to 0.100 inches inch.
The fabrication of these two or four-stack die devices, necessarily, has to be from the bottom up, since it is not possible to form the die pad wire ball bond 32 on the lower dies 16, 18, and 30, if the four dies are already stacked. This is due to the overhead space required by the wire bond machine.
The die pads 26 of each die can be each connected to an individual lead finger 28 or the dies can be wired in parallel. The former configuration would, therefore, require (for a four die stack) something less than 4×18=72 4×18=72 leads, while parallel connections would require something on the order of 22 or more pins, depending on the type of devices and system requirements. The final packages can be in the form of a small outline J-leaded (SOJ) package, a dual in-line package (DIP), a single in-line package (SIP), a plastic leaded chip carrier (PLCC), and a zig-zag in-line package (ZIP).
While a preferred embodiment of the invention has been disclosed, various modes of carrying out the principles disclosed herein are contemplated as being within the scope of the following claims. Therefore, it is understood that the scope of the invention is not to be limited except as otherwise set forth in the claims.
Patent | Priority | Assignee | Title |
7691668, | Dec 19 2006 | Infineon Technologies LLC | Method and apparatus for multi-chip packaging |
7888185, | Aug 17 2006 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
8324716, | Dec 19 2006 | Infineon Technologies LLC | Method and apparatus for multi-chip packaging |
8384228, | Apr 29 2009 | Qorvo US, Inc | Package including wires contacting lead frame edge |
Patent | Priority | Assignee | Title |
4567643, | Oct 24 1983 | Sintra-Alcatel | Method of replacing an electronic component connected to conducting tracks on a support substrate |
4984059, | Oct 08 1982 | Fujitsu Limited | Semiconductor device and a method for fabricating the same |
4996587, | Apr 10 1989 | International Business Machines Corporation | Integrated semiconductor chip package |
5012323, | Nov 20 1989 | Micron Technology, Inc. | Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe |
5049976, | Jan 10 1989 | National Semiconductor Corporation | Stress reduction package and process |
JP128856, | |||
JP3169062, | |||
JP456262, | |||
JP5662351, | |||
JP60182731, | |||
JP62126661, | |||
JP63128736, | |||
RE36613, | Feb 29 1996 | Round Rock Research, LLC | Multi-chip stacked devices |
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Dec 23 2009 | Micron Technology, Inc | Round Rock Research, LLC | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 023786 | /0416 |
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