The program circuit according to the present invention can apply a program voltage to the only memory cells which are not programmed during a re-programming operation, thus, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a program bias voltage.
|
1. A program circuit comprising:
a comparator for comparing output data of a data input buffer with output data of a sense amplifier bit by bit, and for outputting a re-program operation signal if the data are different from each other;
a data latch circuit for latching the comparing results of the output data of said data input buffer and the output data of said sense amplifier;
a control circuit for generating a high voltage for receiving the output data of said data input buffer and the data latched at said data latch circuit, respectively, and for outputting a signal for applying a program bias voltage to a memory cell which has not been completely programmed in response to a power-up reset signal and program state signal.
0. 17. A non-volatile semiconductor device, comprising:
a plurality of memory cells;
a sense amplifier coupled to the memory cells to read information written into the memory cells;
an input data buffer coupled to the memory cells and configured to transmit n bits of information at a time into the memory cells;
a comparator having a plurality of logic gates to compare bit-by-bit first information of the input data buffer with second information of the sense amplifier and output a reprogram operation signal if the first information and the second information are different;
a data latch circuit coupled to outputs of one or more of the logic gates of the comparator; and
a controller having a plurality of logic gates and being configured to receive the first information of the input data buffer and outputs of the data latch circuit, and output a signal for applying a program bias voltage to any memory cell that has not been properly programmed.
0. 6. A semiconductor device, comprising:
a plurality of memory cells;
an input component coupled to the memory cells and configured to program the memory cells;
a comparator to determine whether first information of the input component has been properly programmed into the memory cells, the comparator having a logic gate to output a first signal to indicate whether or not a reprogramming operation is needed, wherein the first information is n bits of data;
a controller coupled to the comparator and configured to output a second signal to initiate reprogramming of M number of the memory cells, where M is less than n,
wherein the comparator compares the first information of the input component with second information read from the memory cells,
wherein n is eight and the input component is configured to transmit a byte of information at a time to the memory cells, and
wherein the comparator includes a plurality of xnor gates having first and second input ports, the first input ports being configured to receive the first information and the second input ports being configured to receive the second information, wherein outputs of the xnor gates indicate whether the first information and the second information are the same.
0. 20. A non-volatile semiconductor device, comprising:
a plurality of memory cells;
a sense amplifier coupled to the memory cells;
an input data buffer coupled to the memory cells and configured to write n bits of information at a time into the memory cells;
a comparator having n number of xnor gates corresponding to the n bits of information being written into the memory cells, the comparator being configured to compare bit-by-bit n bits of first information of the input data buffer with n bits of second information of the sense amplifier and output a rewrite operation signal if any bit of the first information and the second information is different from each other;
a data latch circuit coupled to the comparator to receive outputs of the xnor gates; and
a controller having a plurality of logic gates and being configured to receive the first information of the input data buffer and outputs of the data latch circuit, and configured to output a signal for applying a bias voltage to any memory cell that has not been properly written,
wherein the plurality of logic gates of the controller include a first set of logic gates of n numbers corresponding to the n bits of information written into the memory cells, the first set of logic gates being configured to output a high voltage signal for any bit of information that has not been properly written into the memory cells.
2. The program circuit as claimed in
3. The program circuit as claimed in
4. The program circuit as claimed in
0. 5. The program circuit as claimed in
0. 7. The device of
0. 8. The device of
a logic gate coupled to the outputs of the xnor gates, the logic gate configured to output the second signal; and
a data latch circuit for latching the compared results of the comparator.
0. 9. The device of
a sense amplifier coupled to the memory cells, wherein the sense amplifier provides the second information to the second input ports of the xnor gates.
0. 10. The device of
a latch configured to receive information relating to the first information of the input component.
0. 11. The device of
0. 12. The device of
0. 13. The device of
0. 14. The device of
0. 15. The device of
0. 16. The device of
0. 18. The non-volatile device of
0. 19. The non-volatile device of
|
from each other, the data outputted via the output terminals of the exclusive NOR gates EG1 through EG8 become “10011000”. As a result, the output of the NOR gate NG is maintained at a low level, and a re-programming operation is performed. At the same time, the data “101111011” outputted via the output terminals of the exclusive NOR gates EG1 through EG8 is latched to the flip-flops F1 through F8 respectively depending on the input of the program state signal PGM4, and the output signals Q0 through Q7 of the flip-flops F1 through F8 are inputted to the NOR gates N1 through N8, respectively. For reference only, before the data “101111011” “10111011” is inputted to the data latch circuit 2, the flip-flops F1 through F8 are maintained at the state in which the data of “0” is latched by the input of the power-up reset signal PURST. Thereafter, the data “10011000” outputted from the flip-flops F1 through F8 are inputted to the NOR gates N1 through N8 of the control circuit for generating high voltage 3 respectively, and the output data “1001100” of the data input buffer is inputted to the inverters I1 and I8, respectively.
At this time, signals at a low level are outputted from only the output terminals VCVPB1 and VCVPB5 of the NAND gates NG2 and NG6 by the power-up reset signal PURST inputted with a low level and the program state signal PGM1 inputted with a high level. Therefore, a programming bias voltage is again applied to only the memory cells which are corresponded to the second and the sixth bits, respectively.
As mentioned above, the program circuit according to the present invention can apply a program voltage to only the memory cells which are not programmed during a re-programming operation. Therefore, the present invention can be prevent a lowering of reliability of the memory cell due to a continued supply of a program bias voltage.
The foregoing description, although described in its preferred embodiments with a certain degree of particularity, is only illustrative of the principle of the present invention. It is to be understood that the present invention is not to be limited to the preferred embodiment disclosed and illustrated herein. Accordingly, all expedient variations that may be made within the scope and spirit of the present invention are to be encompassed as further embodiments of the present invention.
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4811294, | Jun 21 1985 | Mitsubishi Denki Kabushiki Kaisha | Data integrity verifying circuit for electrically erasable and programmable read only memory (EEPROM) |
5163021, | Apr 11 1990 | SanDisk Technologies LLC | Multi-state EEprom read and write circuits and techniques |
5299162, | Feb 21 1992 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device and an optimizing programming method thereof |
5521868, | Aug 11 1993 | Sony Corporation | NOR-type non-volatile memory using tunnel current and having selective re-write |
5570315, | Sep 21 1993 | Kabushiki Kaisha Toshiba | Multi-state EEPROM having write-verify control circuit |
5574684, | Jan 09 1995 | Mitsubishi Electric Semiconductor Software Co., Ltd.; Mitsubishi Denki Kabushiki Kaisha | Flash memory having data refresh function and data refresh method of flash memory |
5629890, | Sep 14 1994 | Winbond Electronics Corporation | Integrated circuit system for analog signal storing and recovery incorporating read while writing voltage program method |
5657270, | Mar 31 1990 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with threshold value controller for data programming |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Jul 25 2001 | Hynix Semiconductor Inc. | (assignment on the face of the patent) | / | |||
Mar 23 2012 | Hynix Semiconductor Inc | SK HYNIX INC | CHANGE OF NAME SEE DOCUMENT FOR DETAILS | 030085 | /0600 | |
Mar 07 2013 | SK HYNIX INC | FIDELIX CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 030086 | /0328 | |
Apr 12 2017 | FIDELIX CO , LTD | DOSILICON CO , LTD | ASSIGNMENT OF ASSIGNORS INTEREST SEE DOCUMENT FOR DETAILS | 042244 | /0073 |
Date | Maintenance Fee Events |
May 18 2010 | ASPN: Payor Number Assigned. |
Dec 02 2010 | M1553: Payment of Maintenance Fee, 12th Year, Large Entity. |
Date | Maintenance Schedule |
Feb 19 2011 | 4 years fee payment window open |
Aug 19 2011 | 6 months grace period start (w surcharge) |
Feb 19 2012 | patent expiry (for year 4) |
Feb 19 2014 | 2 years to revive unintentionally abandoned end. (for year 4) |
Feb 19 2015 | 8 years fee payment window open |
Aug 19 2015 | 6 months grace period start (w surcharge) |
Feb 19 2016 | patent expiry (for year 8) |
Feb 19 2018 | 2 years to revive unintentionally abandoned end. (for year 8) |
Feb 19 2019 | 12 years fee payment window open |
Aug 19 2019 | 6 months grace period start (w surcharge) |
Feb 19 2020 | patent expiry (for year 12) |
Feb 19 2022 | 2 years to revive unintentionally abandoned end. (for year 12) |