Probe card having groups of probe needles in a probing test apparatus for testing semiconductor integrated circuits

Abstract

A probe card which can help to enhance the productivity of semiconductor integrated circuits manufacturing and to reduce the manufacturing cost thereof, and a method of probe-testing semiconductor integrated circuits by using the probe card. The probe card is designed to test semiconductor integrated circuits formed on a semiconductor wafer and arranged in rows and columns. It has groups of probe needles provided to contact semiconductor integrated circuits arranged in two columns and at least two rows. The card receives a test signal from a test device and supplies the test signal simultaneously to these semiconductor integrated circuits arranged in two columns and at least two row, through the groups of probe needles. It receives response signals simultaneously from the semiconductor integrated circuits through the groups of probe needles and then supplies the response signals to the tester.

Description

is similar to the conventional card 5. Since the probe card 15 has a small diameter, it wraps but very little, exerting but a very little stress on the wires provided on or in the substrate 20 and scarcely altering the electrical characteristics of the wires. In addition, since the wires are short, the crosstalk among the wires is small.

In view of these advantages, the probe card 15 can serve to enhance the productivity production of semiconductor integrated circuits and also to reduce the manufacturing cost of semiconductor integrated circuits.

FIG. 5A is a graph representing the results of conventional probing test, while FIG. 5B is a graph representing the results of the probing test performed by using the probe card 15. As seen from FIG. 5A, three out of eight chips 3a to 3h were found to be flawless when tested by using the probe card 5′ shown in FIG. 2. In FIG. 5A, the true characteristics of the chips tested are indicated by broken lines. In view of the true characteristics of the chips, seven chips should have been found to be flawless. This means that four chips were 3a, 3f, 3g and 3h were regarded as defective, though they were flawless in fact.

When the probe card 15 was used, testing chips 3a to 3h arranged in four rows and two columns, six of the chips were found to be flawless, as can be seen from FIG. 5B. Only one of the chips was found to be defective, though it was actually flawless, as can be understood from FIG. 5B. It should be noted that the eight chips tested by using the probe card 15 were respectively identical in characteristics to those eight chips tested by using the conventional probe card 5′.

Namely, some of the flawless chips which were regarded as defective when tested by using the conventional probe card 5′ were correctly found to flawless when tested by using the probe card 15 according to the invention. In other words, the probe card 15 serves to test chips with high accuracy, thus saving flawless chips which would have been discarded as defective if the conventional probe card 5′ had been used. As a result, the probe card 15 serves to decrease the manufacturing cost of semiconductor integrated circuits.

A probe card 15 according to the second embodiment will be described, with reference to FIG. 6 which is a plan view. The second embodiment is characterized in that groups of wires are arranged on or in the substrate 20 such that all wires are as short as possible.

As shown in FIG. 6, the probe card 15 has a substrate. The substrate has a rectangular through hole 17 extending along a diameter 30 of the substrate 30. The substrate has a right half 33R and a left half 33L on the right and left sides of the diameter 30, respectively. Provided in the right half 33R are four wiring regions 35a to 35d. Provided in the left half 33L are four wiring regions 35e to 35h. In the wiring region 35a, a group 37a of wires is provided, connecting the probe contacts of a group 21a to the probe needles of the group 19a (not shown) which are to contact the pads of a chip 3a. Similarly, in the wiring region 35b, a group 37b of wires is provided, connecting the probe contacts of a group 21b to the probe needles of the group 19b (not shown) which are to contact the pads of a chip 3b. In the other wiring regions 35c to 35h, groups 37c to 37h of wires are provided, respectively, each connecting a probe pad to a probe needle. For example, the wires of the group 37h provided in the wiring region 35h connect the probe pads of the group 21h to the probe needles of the group 19h which are to contact the pads of a chip 3h.

Thus, the four groups 19a to 19d of probe needles to contact the chips 3a to 3d, groups 21a to 21d of probe contacts, and groups 37a to 37d of wires are arranged in the right half 33R of the substrate. The remaining four groups 19e to 19h of probe needles to contact the chips 3e to 3h, groups 21e to 21h of probe contacts, and groups 37e to 37h of wires are arranged in the right left half 33L of the substrate.

Arranged as shown in FIG. 6, the wires of the groups 37a to 37h are shorter than otherwise, and the difference in length between the longest and shortest wires provided is relatively small. Hence, the differences in resistance and capacitance among the wires is proportionally small. In addition, since the wires are short, the crosstalk among the wires is small. The probe card 15 according to the second embodiment can therefore help accomplish high-accuracy probing test, in which eight chips are tested at the same time.

Another probe card 15 according to the third embodiment of this invention will be described, with reference to FIG. 7 which is an exploded view. The third embodiment is similar to the first embodiment. It is characterized in that the substrate 20 is designed so as to reduce the crosstalk among the wires.

As illustrated in FIG. 7, the substrate 20 is composed of seven layers 20-1 to 20-7. Probe contacts 21 are mounted on the first layer 20-1. This probe card 15 is designed for use in testing semiconductor memories and has six types of wires 27, which are: address signal wires; data signal wires; ground (VSS) wires; control wires for supplying control signals such as row-address strobe signals and column-address strobe signals; power-supply wires; and other wires for a monitor or the like. The address signal wires are provided on the second layer 20-2, the data signal wires on the third layer 20-3, the ground wires on the fourth layer 20-4, the control wires on the fifth layer 20-5, the power-supply wires on the sixth layer 20-6, and the other wires on the seventh layer 20-7. The wires 37 provided on the second to seventh layers 20-2 to 20-7 extend through holes 39 made in these layers 20-2 to 20-7 and are connected to the probe contacts 21 which are provided on the first layer 20-1.

Since the wires 37 of each type are provided on one layer, not together with the wires of any other type, the crosstalk among the wires 37 is far less than in the case all wires are arranged densely on one and the same layer. The probe card 15 according to the third embodiment can, therefore, help to achieve high-accuracy probing test. It has eight groups of probe needles and can serve to test eight chips at the same time.

The third embodiment can be used in combination with the probe card according to the second embodiment.

Methods of probe-testing semiconductor integrated circuits by using the probe card according to the invention will be described as the fourth, fifth and sixth embodiments.

FIG. 8 is a diagram explaining the probe-testing method according to the fourth embodiment. This method can test more chips at the same time than is possible by using the probe card 15 according to the first embodiment.

As shown in FIG. 8, four test stations 43-1 to 43-4 are provided for one tester 41. Each test station is equipped with one probe card. More precisely, the test stations 43-1 to 43-4 have probe cards 15-1 to 15-4, respectively. Four semiconductor wafers 1-1 to 1-4 are located at the test stations 43-1 to 43-4, respectively. Using the probe cards 15-1 to 15-4, the tester 41 tests four wafers 1-1 to 1-4 simultaneously.

With this method, the more test stations are installed, the more chips can be tested at the same time with high accuracy. Namely, L×M chips can be tested at a time, where L is the number of chips that can be simultaneously tested by using one probe card, and M is the number of test stations installed.

In the instance shown in FIG. 8, L=8 and M=4. Hence, the tester 41 can test 32 chips at a time. The probe cards 15-1 to 15-4 may be those of the first embodiment, the second embodiment, the third embodiment or a combination of the second and third embodiments. Since the probe card 15 of any embodiment serves to test chips with high accuracy, the tester 41 can test as many as 32 chips simultaneously with sufficiently high accuracy.

FIG. 9 is a diagram explaining the probe-testing method which is the fifth embodiment of this invention. The fifth embodiment requires but little cost per chip, and is better in cost performance than the method according to the fourth embodiment.

As illustrated in FIG. 9, the method uses one tester 41 and one test station 43. The test station 43 is equipped with two probe cards 15-1 and 15-2. The probe cards 15-1 and 15-2 are used at the same time to test chips provided on one semiconductor substrate 1. In this method, the tester 41 can test L×N chips simultaneously, where N is the number of probe cards provided at the test station 42 and L is the number of chips that can be simultaneously tested by using one probe card. Hence, one test station can test more chips at the same time than is possible with the fourth embodiment, with the same accuracy as is possible with the fourth embodiment. In the case shown in FIG. 9, wherein L=8 and N=2, the test station 42 can test 16 chips at a time, whereas each test station can test only 8 chips at a time in the fourth embodiment (FIG. 8). Furthermore, the accuracy of probing test remains high, because both probe cards 15-1 and 15-2 attached to the station 43.

Still further, the number of chips tested simultaneously at one test station increases since two or more probe cards 15 are attached to one test station. Therefore, the facility cost for testing one chip is low. Having only one test station, the prober probing system shown in FIG. 9 occupies a smaller floor area than the prober probing system shown in FIG. 8 which needs two test stations to test the same number of chips at the same time. The smaller the floor area required, the lower the air-conditioning cost required, or the hither higher the air purity in the probing room. In view of this, the probe-testing method according to the fifth embodiment helps to decrease the possibility that chips are contaminated with harmful substance such as sodium and the possibility that the wires of each chip are short-circuited by electrically conductive particles such as silicon dust.

As may be understood from FIG. 9, the method according to the fifth embodiment is advantageous when used to test a large semiconductor wafer which has an increased number of chips.

FIG. 10 is a diagram explaining a probe-testing method according to the sixth embodiment of the present invention. As may be seen from FIG. 10, the sixth embodiment is a combination of the methods according to the fourth and fifth embodiments.

In the sixth embodiment, two test stations 43-1 and 43-2 are provided for one tester 41, and two probe cards are attached to each test station. To be more specific, probe cards 15-1 and 15-2 are attached to the first test station 43-1, and probe cards 15-3 and 15-4 to the second test station 43-2. Two semiconductor wafers 1-1 and 1-2 are simultaneously tested at the test stations 43-1 and 43-2, respectively, by using the four probe cards 15-1 to 15-4.

The probe-testing method according to the sixth embodiment can test L×M×N chips at the same time, where L is the number of chips one probe card can test at a time, M is the number of test station provided, and N is the number of probe cards attached to one test station. The sixth embodiment can serve to test many chips simultaneously with high accuracy as does the fourth embodiment, and can achieve good cost performance as does the fifth embodiment.

A semiconductor IC chips chip which can be easily tested by using a probe card which is according to the seventh embodiment of the invention will now be described.

Like the first to third embodiments, this probe card is designed to test IC chips arranged in two columns and at least two rows, at the same time, to determine whether the chips are flawless or defective. The probe card comprises a substrate having a rectangular through hole. It is desirable that some of the probe needles be arranged along one long side of the hole to contact the pads of chips provided on a semiconductor wafer and forming one column and that the other probe needles be arranged along the other long side of the hole to contact the pads of chips provided on the wafer and forming a next column. If the probe needles are thus arranged, the wires provided on or in the substrate can be made shortest as has been explained in conjunction with the second embodiment.

A semiconductor IC chip should have pads arranged in a column to be tested by using the a probe card according to the invention, which has groups of probe needles arranged in the specific manner described above.

FIG. 11 is a diagram representing the positional relationship between the probe needles of the probe card, on the one hand, and the pads of the IC chip 3, on the other. As shown in FIG. 11, the chip 3 is rectangular and has a column of pads 31 arranged along the longitudinal axis. This type of a chip is known as “center-pad type” and is used in, for example, semiconductor memories of large storage capacity.

It is easy to bring the probe needles of one group 19 provided on the probe card into contact with the pads 31 because the pads 31 are arranged in a column. Even if identical chips on the semiconductor wafer are arranged in two columns as shown in FIG. 4, there will be formed only two columns of pads 31 which are to contact the probe needles of one group 19 provided on the probe card. Arranged in two columns, the pads 31 can easily contact the needles of the group 19 provided on the probe card, some of which are arranged along one long side of the rectangular hole of the substrate and the others of which are arranged along the other long side of the rectangular hole.

Alternatively, the pads 31 may be arranged in staggered fashion as is illustrated in FIG. 12.

A probe card 15 according to the eighth embodiment of this invention will be described, with reference to FIG. 13 which is a perspective view.

As shown in FIG. 13, this probe card 15 serves to test 16 chips simultaneously, which are arranged in eight rows and two columns, whereas the first embodiment (FIG. 3) serves to test eight chips at the same time, which are arranged in four rows and two columns.

Designed to test chips arranged in eight rows, the probe card 15 inevitably have has a larger diameter D than the first embodiment (FIG. 3). Hence, it may have the same problems as does the conventional probe card 5′ (FIG. 2). Nevertheless, the eighth embodiment will be practically useful since the probe card technology is well expected to advance to simultaneously test 16 chips arranged in eight rows and two columns, with accuracy as high as in the case eight chips arranged in four rows and two columns are tested at the same time. Needless to say, the eighth embodiment has a smaller diameter than a conventional probe card which is designed to test 16 chips arranged in single column. The eighth embodiment (FIG. 13) can therefore help not only to increase the productivity production of semiconductor integrated circuits, but also to reduce the manufacturing cost of semiconductor integrated circuits.

As can be understood from the eighth embodiment, the present invention is not limited to probe cards which are designed to test eight chips arranged in four rows and two columns. Rather, the invention can provide probe cards which serve to test more chips at a time, arranged in more rows and two columns.

A probe card according to the ninth embodiment of the present invention will be described, with reference to FIGS. 14 and 15. The ninth embodiment is designed to test semiconductor memories each having a large storage capacity and, hence, a relatively large number of pads.

As shown in FIG. 14, a semiconductor memory to be tested has 24 pads arranged in eight rows and three columns. The probe card has group 19 of probe needles, each group consisting of 24 needles which are arranged in eight rows and three columns. FIG. 15 is a plan view showing how the probe needles of groups 19a to 19h are positioned with respect to the pads 31 of semiconductor memories 3a to 3h. (Shown in FIG. 15 are only groups 19a, 19b, 19g and 19h and only memories 3a, 3b, 3g and 3h.) As the probe card technology advances as expected, each group 19 may consists consist of more probe needles arranged in m rows and n column, where m>8 and n>3, whereby the probe card can test semiconductor integrated circuits each having more pads.

A probe card according to the tenth embodiment of the invention will be described, with reference to FIGS. 16 and 17. As seen from FIGS. 16 and 17, this probe card is designed to test semiconductor integrated circuits each having many pads 31 which are arranged in m rows and n columns in staggered fashion.

In the probe cards 15 according to the invention, which are shown in FIGS. 3, 6, 7 and 13, the probe contacts 21 are arranged in a circle, along the circumference of the substrate 20. The probe card may need to have so many probe contacts 21 that it is no longer possible to arrange the contacts 21 in one circle. If so, the probe contacts 21 may well be arranged in two or more concentric circles.

As has been described, the present invention can provide a probe card which can help to enhance the productivity of semiconductor integrated circuits and to reduce the manufacturing cost thereof, and can also provide a method of probe-testing semiconductor integrated circuits by using the probe card.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the intention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims

1. A probed card for use in probing test of semiconductor integrated circuits arranged on a semiconductor wafer in rows and columns, comprising:

a card substrate;

groups of probe needles, said groups arranged on said card substrate in two columns and at least two rows, to contact connection terminals of semiconductor integrated circuits which are arranged in two columns and at least two rows, and

groups of signal lines, each group of signal lines provided for one group of probe needles, each signal line provided for supplying a test signal from a tester to one probe needle and a response signal from the probe needle to the tester,

wherein a test signal supplied from said tester is supplied from said probe needles to the semiconductor integrated circuits arranged in two columns and at least two rows at the same time through said groups of probe needles, and response signals generated by the semiconductor integrated circuits arranged in two columns and at least two rows are simultaneously supplied to the tester through said groups of probe needles.

2. The probe card according to claim 1, wherein said card substrate has a rectangular through hole having first and second long sides, the probe needles of the groups extend through the rectangular through hole, the probe needles of some groups are arranged along the first long side of the rectangular hole to contact the connection terminals of the semiconductor integrated circuits arranged in the first column, and the probe needles of the other groups are arranged along the second long side of the rectangular through hole to contact the connection terminals of the semiconductor integrated circuits arranged in the first column.

3. The probe card according to claim 1, wherein connection terminals of the semiconductor integrated circuits comprise a plurality of pads which are arranged in at least two columns.

4. The probe card according to claim 2, which further comprises groups of contacts exposed on a surface of said card substrate, to be connected to the tester, and groups of wires connecting the groups of probe contacts to the groups of probe needles; and in which said probe substrate consists of first and second halves divided along a longitudinal axis of said rectangular hole, the wires connected to the probe needles to contact the connection terminals of the semiconductor integrated circuits arranged in the first column and the probe contacts connected to these wires are provided on the first half of said probe substrate, and the wires connected to the probe needles to contact the connection terminals of the semiconductor integrated circuits arranged in the second column and the probe contacts connected to these wires are provided on the second half of said probe substrate.

5. The probe card according to claim 4, wherein said probe substrate comprises a plurality of layers, said wires are divided into groups in accordance with types of signals and types of powers, and the groups of wires, thus formed, are provided on the layers, respectively.

6. A method for testing semiconductor integrated circuits, the method comprising:

providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in two columns and at least two rows, each of said plurality of semiconductor integrated chips having a plurality of external terminals;

coupling a probe card to the semiconductor wafer through a plurality of probe needles on said probe card corresponding to said plurality of external terminals of each of said integrated circuit chips, said probe card receiving a plurality of independent test signals and a power supply from a tester, wherein said probe card includes structure defining a rectangular through hole having first and second long sides, and wherein the probe needles extend through the rectangular through hole;

supplying the independent test signals and the power supply from the tester through the probe needles to said plurality of external terminals of said plurality of integrated circuits; and

measuring electric characteristics of said semiconductor integrated circuit chips in an independent manner.

7. The method of claim 6, wherein said external terminals are centrally disposed within said integrated circuit chips, with integrated circuits on either side of said external terminals.

8. The method of claim 7, wherein said external terminals are arranged in a plurality of columns and rows.

9. The method of claim 8, wherein the step of providing a semiconductor wafer includes forming memory arrays for each of said integrated circuit chips.

10. The method of claim 6, wherein the test signal and the power supply are supplied from said tester to said probe needles by way of a plurality of wiring lines on internal layers of said probe card.

11. The method of claim 6, wherein the test signal and the power supply are supplied from said tester to said probe needles by way of a plurality of wiring lines on different internal layers of said probe card, said wiring lines positioned on different ones of said different internal layers according to a type of signal carried by said wiring lines.

12. A probing test method of semiconductor integrated circuits, comprising:

preparing at least one semiconductor wafer, said semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in rows and columns, said semiconductor integrated circuit chips having a plurality of external pads;

preparing at least one probe card, said probe card having a plurality of connection terminals for receiving from a tester a test signal and a power supply, said at least one probe card having a plurality of probe needles corresponding to said plurality of external pads, respectively, wherein said probe card includes structure defining a rectangular through hole having first and second long sides, and wherein the probe needles extend through the rectangular through hole;

supplying said test signal and said power supply from said tester to said probe needles by way of said connection terminals in a completely independent manner;

supplying said test signal and said power supply from said probe needles to said semiconductor integrated circuit chips, by way of said external pads, in a completely independent manner; and

measuring electric characteristics of the semiconductor integrated circuit chips in a completely independent manner.

13. The probing test method according to claim 12, wherein said test signal and said power supply are supplied from said connection terminals to said probe needles in a completely independent manner, by way of a plurality of completely independent wiring lines which are provided inside said probe card and to which said test signal and said power supply are transmitted.

14. The probing test method according to claim 12, wherein said test signal and said power supply are supplied from said connection terminals to said probe needles in a completely independent manner, by way of a plurality of wiring lines which are provided inside said probe card in accordance with kinds of signals and types of power supplies.

15. The probing test method according to claim 12, further comprising:

preparing at least one test station; and

attaching said probe card to said at least one test station.

16. The probing method according to claim 12, further comprising:

preparing at least one test station; and

attaching a plurality of probe cards to said at least one test station.