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0. 24. A method of fabricating a metal oxide semiconductor field effect transistor, (MOSFET) device on a semiconductor substrate, comprising the steps of:
forming a gate structure overlying a gate insulator layer on said semiconductor substrate;
forming a silicon oxide layer on said gate structure and on the top surface of said semiconductor substrate not covered by said gate structure;
performing a first ion implantation procedure to form an implanted region, in an area of said semiconductor substrate not covered by said gate structure; and
performing a second ion implantation procedure to create a nitrogen region at the interface between the silicon oxide layer and the implanted region.
1. A method of fabricating a metal oxide semiconductor field effect transistor, (MOSFET), device, on a semiconductor substrate, comprising the steps of:
forming a gate structure, overlying a gate insulator layer, on said semiconductor substrate;
growing a first silicon oxide layer on said gate structure, and on the top surface of regions of said semiconductor substrate not covered by said gate structure;
performing a first ion implantation procedure to form a lightly doped source/drain, (ldd), region, in an area of said semiconductor substrate not covered by said gate structure;
depositing a second silicon oxide layer;
performing a second ion implantation procedure to create a nitrogen region at the first silicon oxide-ldd interface;
forming composite insulator spacers on the sides of said gate structure;
performing a third ion implantation procedure to form a heavily doped source/drain region in an area of said semiconductor substrate not covered by said gate structure, or by said composite insulator spacers; and
performing an anneal procedure.
14. A method of fabricating an input/output n channel, (I/O NMOS), device, on a semiconductor substrate, featuring an implanted nitrogen region, located at an interface of an overlying insulator layer and an underlying, lightly doped source/drain, ( ldd), region, comprising the steps of:
growing a silicon dioxide gate insulator layer on said semiconductor substrate;
forming a polysilicon gate structure on said silicon dioxide gate insulator layer;
growing a silicon oxide layer on the surface of said polysilicon gate structure, and on the surface of portions of said semiconductor substrate not covered by said polysilicon gate structure;
using tetraethylorthosilicate as a source to deposit a teos silicon oxide liner layer;
performing a first ion implantation procedure to form an n type ldd region in an area of said semiconductor substrate not covered by said polysilicon gate structure;
performing a second ion implantation procedure in situ, to form said nitrogen region at said silicon oxide-n type ULDD interface;
forming composite insulator spacers on sides of said polysilicon gate structure, comprised of an overlying silicon oxide shape, and an underlying silicon nitride shape;
performing a third ion implantation procedure to form an n type, heavily doped source/drain region, in an area of said semiconductor substrate not covered by said polysilicon gate structure, or by said composite insulator spacers; and
performing a rapid thermal anneal, (RTA), procedure.
2. The method of claim 1, wherein said MOSFET device is an input/output n channel, (I/O NMOS), device.
3. The method of claim 1, wherein said gate insulator layer is a silicon dioxide layer, thermally grown to a thickness between about 40 to 80 Angstroms, at a temperature between about 650 to 900° C., in an oxygen-steam ambient.
4. The method of claim 1, wherein said gate structure is a polysilicon gate structure, comprised from a polysilicon layer which is obtained via LPCVD procedures, at a thickness between about 1500 to 2500 Angstroms, and either doped in situ, during deposition, via the addition of arsine, or phosphine, to a silane ambient, or deposited intrinsically then doped via implantation of arsenic, or phosphorous ions.
5. The method of claim 1, wherein said gate structure is defined via an anisotropic RIE procedure, applied to a polysilicon layer, using Cl 2 or SF 6 as an etchant.
6. The method of claim 1, wherein said first silicon oxide layer is thermally grown to a thickness between about 15 to 80 Angstroms, at a temperature between about 800 to 1015° C., in an oxygen-steam ambient.
7. The method of claim 1, wherein said first ion implantation procedure, used to form said ldd region, is performed using arsenic or phosphorous ions, at an energy between about 20 to 50 KeV, at a dose between about 2E13 to 5E13 atoms/cm 2.
8. The method of claim 1, wherein said second silicon oxide layer, is obtained via LPCVD or PECVD procedures, at a thickness between about 80 to 250 Angstroms, using tetraethylorthosilicate, ( teos), as a source.
9. The method of claim 1, wherein said second ion implantation procedure, used to create said nitrogen region, is performed using either nitrogen, n2+), or nitrogen ions, ( n+), as a source, at an energy between about 5 to 25 KeV, at a dose between about 1E14 to 1E15 atoms/cm 2.
10. The method of claim 1, wherein said composite insulator spacers are comprised of an underlying silicon nitride layer, obtained via LPCVD or PECVD procedures, at a thickness between about 200 to 400 Angstroms, and comprised of an overlying silicon oxide layer, obtained via LPCVD or PECVD procedures, at a thickness between about 850 to 1100 Angstroms, using teos as a source.
11. The method of claim 1, wherein said composite insulator spacers are defined via an anisotropic RIE procedure using CHF 3 as an etchant for silicon oxide, and using Cl 2 as an etchant for silicon nitride.
12. The method of claim 1, wherein said third ion implantation procedure, used to create said heavily doped source/drain region, is performed using arsenic or phosphorous ions, at an energy between about 40 to 60 KeV, at a dose between about 3E15 to 6.5E15 atoms/cm 2.
13. The method of claim 1, wherein said anneal procedure is a rapid thermal anneal, (RTA), procedure, performed at a temperature between about 1000 to 1050° C., for a time between about 5 to 15 sec, in a nitrogen or argon ambient.
15. The method of claim 14, wherein said silicon dioxide gate insulator layer is obtained via thermal oxidation procedures, at a temperature between about 650 to 900° C., in an oxygen-steam ambient, to a thickness between about 40 to 80 Angstroms.
16. The method of claim 14 wherein said polysilicon gate structure is comprised from a polysilicon layer, which is obtained via LPCVD procedures, at a thickness between about 1500 to 2500 Angstroms, and either doped in situ, during deposition via the addition of arsine, or phosphine, to a silane ambient, or deposited intrinsically the doped via implantation of arsenic, or phosphorous ions, then defined via an anisotropic RIE procedure, applied to a polysilicon layer, using Cl 2 or SF 6 as an etchant.
17. The method of claim 14, wherein said silicon oxide layer is obtained via thermal oxidation procedures, at a temperature between about 800 to 1015° C., in an oxygen-steam ambient, to a thickness between about 15 to 80 Angstroms.
18. The method of claim 14, wherein said teos silicon oxide liner layer is deposited to a thickness between about 80 to 250 Angstroms, via LPCVD or PECVD procedures, using tetraethylorthosilicate, ( teos), as a source.
19. The method of claim 14, wherein said first ion implantation procedure, used to form said n type ldd region, is performed using arsenic or phosphorous ions, at an energy between about 20 to 50 KeV, at a dose between about 2E13 to 5E13 atoms/cm 2.
20. The method of claim 14, wherein said second ion implantation procedure, used to create said nitrogen region, is performed using either nitrogen, ( n2+), or nitrogen ions, ( n+), as a source, at an energy between about 5 to 25 KeV, at a dose between about 1E14 to 1E15 atoms/cm 2.
21. The method of claim 14, wherein said composite insulator spacers are comprised of an underlying silicon nitride layer, obtained via LPCVD or PECVD procedures, at a thickness between about 200 to 400 Angstroms, and comprised of an overlying silicon oxide layer, obtained via LPCVD or PECVD procedures, at a thickness between about 850 to 1100 Angstroms, using teos as a source.
22. The method of claim 14, wherein said third ion implantation procedure, used to create said n type, heavily doped source/drain region, is performed using arsenic or phosphorous ions, at an energy between about 40 to 60 KeV, at a dose between about 3E15 to 6.5E15 atoms/cm 2.
23. The method of claim 14, wherein said rapid thermal anneal procedure is performed at a temperature between about 1000 to 1050° C., for a time between about 5 to 15 sec, in a nitrogen or argon ambient.
0. 25. The method of claim 24, wherein said MOSFET device is an input/output n channel (I/O NMOS) device.
0. 26. The method of claim 24 wherein said gate insulator layer is formed to a thickness of between about 40 to 80 Angstroms, at a temperature of between about 650 to 900° C., in an oxygen-steam ambient.
0. 27. The method of claim 24, wherein said step of forming a gate structure includes LPCVD depositing a polysilicon layer at a thickness of between about 1500 to 2500 Angstroms, the polysilicon layer being doped by a method selected from the group consisting of in situ doping during deposition via the addition of arsine or phosphine to a silane ambient, and deposited intrinsically then doped via implantation of arsenic or phosphorous ions.
0. 28. The method of claim 24, wherein said step of forming a gate structure includes defining said gate structure via an anisotropic RIE procedure, applied to a polysilicon layer, using Cl2 or SF6 as an etchant.
0. 29. The method of claim 24, wherein said silicon oxide layer is thermally grown to a thickness of between about 15 to 80 Angstroms, at a temperature of between about 800 to 1015° C., in an oxygen-steam ambient.
0. 30. The method of claim 24, wherein said first ion implantation procedure used to form said implanted region is performed using arsenic or phosphorous ions at an energy of between about 20 to 50 KeV at a dose of between about 2E13 to 5E13 atoms/cm2.
0. 31. The method of claim 24, wherein said second ion implantation procedure used to create said nitrogen region is performed using either nitrogen (n2+), or nitrogen ions (n+) as a source, at an energy between about 5 to 25 KeV, at a dose between about 1E14 to 1E15 atoms/cm2.
0. 32. The method of claim 30, wherein said MOSFET device is an input/output n channel (I/O NMOS) device.
0. 33. The method of claim 30, wherein said gate insulator layer is formed to a thickness of between about 40 to 80 Angstroms, at a temperature between about 650 to 900° C., in an oxygen-steam ambient.
0. 34. The method of claim 30, wherein said gate structure is a polysilicon gate structure, comprised from a polysilicon layer which is obtained via LPCVD procedures, at a thickness between about 1500 to 2500 Angstroms, and either doped in situ during deposition via the addition of arsine or phosphine, to a silane ambient, or deposited intrinsically then doped via implantation of arsenic or phosphorous ions.
0. 35. The method of claim 30, wherein said gate structure is defined via an anisotropic RIE procedure, applied to a polysilicon layer, using Cl2 or SF6 as an etchant.
0. 36. The method of claim 30, wherein said first ion implantation procedure used to form said implanted region is performed using arsenic or phosphorous ions at an energy of between about 20 to 50 KeV, at a dose of between about 2E13 to 5E13 atoms/cm2.
0. 37. The method of claim 30, wherein said second ion implantation procedure used to create said nitrogen region is performed using either nitrogen (n2+), or nitrogen ions (n+) as a source, at an energy of between about 5 to 25 KeV, at a dose of between about 1E14 to 1E15 atoms/cm2.
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(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to an ion implantation procedure, used to improve the reliability of metal oxide semiconductor field effect transistor, (MOSFET), devices, in regards to a hot electron carrier phenomena.
(2) Description of Prior Art
Micro-miniaturization has allowed the semiconductor industry to fabricate MOSFET devices with sub-quarter micron features. Specific MOSFET devices, such as input/output, N channel, (I/O NMOS), devices, used for logic applications, can however be prone to a hot electron carrier, (HCE), carefuil careful wet cleans, with the wet clean cycle removing the exposed regions of gate insulator 2, not covered by polysilicon gate structure 3. An oxidation procedure is next performed to form silicon oxide layer 4, on the surface of polysilicon gate structure 3, as well as on the exposed surface of semiconductor substrate 1. Silicon oxide layer 4, at a thickness between about 15 to 80 Angstroms, is obtained via thermal oxidation procedures, at a temperature between about 800 to 1015° C., in an oxygen-steam ambient.
A first iteration of this invention is next described, and shown schematically in FIGS. 2-5. In addition to the fabrication of the I/O NMOS devices, the fabrication of core devices are also integrated on the same semiconductor chip. The core devices, not shown in the drawings, are designed with performance and reliability parameters, different than the performance and reliability requirements of the I/O NMOS devices. Therefore specific regions of the core devices, such as a previously formed lightly doped source/drain region, (LDD), have to be protected from subsequent I/O NMOS process steps, such as formation of the I/O NMOS LDD regions, and the critical nitrogen implantation procedure. Therefore prior to the formation of the I/O NMOS, LDD region 5, a photoresist block out shape, not shown in the drawings, is use to protect the core devices. LDD region 5, shown schematically in FIG. 2, is formed via ion implantation of arsenic or phosphorous ions, at an energy between about 20 to 50 KeV, at a dose between about 2E13 to 5E13 atoms/cm2. This ion implantation procedure can be performed at an angle between about 0 to 45 degrees. After removal of the photoresist shape used to protect the core devices from implantation procedures used to form LDD region 5, via plasma oxygen ashing and careful wet cleans, TEOS liner 6, is deposited via LPCVD, or via plasma enhanced chemical vapor deposition, (PECVD), procedures, at a temperature between about 700 to 800° C., at a thickness between about 80 to 250 Angstroms, using tetraethylorthosilicate, (TEOS), as a source. This is schematically shown in FIG. 2.
Another photoresist shape is used to protect the core devices from a critical implantation of nitrogen, (N2+), or nitrogen ions, (N+), performed at an energy between about 5 to 25 KeV, at a dose between about 1E14 to 1E15 atoms/cm2, resulting in a concentration of nitrogen ions 7, located at the top surface of LDD region 5. This is schematically shown in FIG. 3. This plantation implantation procedure results in a pile-up of nitrogen at the LDD—oxide interface, reducing hot carrier electron, (HCE), injection, during operation of the completed I/O NMOS device. In addition the nitrogen pile-up, at this interface increase increases the transient enhanced diffusion, (TED), phenomena, allowing a more graded IL)D LDD region to be achieved, when compared to counterparts fabricated without the nitrogen implantation procedure. Graded LDD region 5, in combination with the nitrogen pile-up at the interface, also reduces HCE injection. The photoresist shape, used to protect the core devices from the nitrogen implantation procedure, is again removed via plasma oxygen ashing and careful wet cleans.
Composite insulator spacers are next formed, and schematically described using FIGS. 4-5. Silicon nitride layer 8, is first obtained, via LPCVD or PECVD procedures, at a temperature between about 700 to 780° C., at a thickness between about 200 to 400 Angstroms. This is followed by the deposition of silicon oxide layer 9, again via LPCVD or PECVD procedures, at a temperature between about 700 to 800° C., to a thickness between about 850 to 1100 Angstroms, using TEOS as a source. Anisotropic RIE procedures, using CHF3 as an etchant for silicon oxide layer 9, and using Cl2 as an etchant for silicon nitride layer 8, are employed to form the composite insulator spacers, shown schematically in FIG. 5. An overetch cycle, for the definition of the composite insulator spacers result in removal the exposed regions of TEOS finer liner 6, and of silicon oxide layer 4. Heavily doped source/drain region 20, is next formed in regions of the semiconductor substrate not covered by polysilicon gate structure 3, or by the composite spacers, on the sides of the polysilicon gate structure. Heavily dopes doped source/drain region 20, shown schematically in FIG. 5, is formed via implantation of arsenic, or phosphorous ions, at an energy between about 40 to 60 KeV, at a dose between about 3E15 to 6.5E15 atoms/cm2. A rapid thermal anneal, (RTA), procedure, performed at a temperature between about 1000 to 1050° C., for a time between about 5 to 15 sec, in a nitrogen or argon ambient, is used to activate the dopants in heavily doped source/drain region 20, as well as grading the profile of LDD region 5.
A second iteration of this invention also features the desired nitrogen pile-up, at the LDD-oxide interface, reducing HCE injection, however this iteration features the implantation of the I/O NMOS LDD regions, followed by an in situ implantation of nitrogen, using only one photoresist mask, thus reducing cost. After definition of polysilicon gate structure 3, followed by the re-oxidation procedure, resulting in the formation of silicon oxide layer 4, a TEOS liner layer 10, is deposited, via PECVD or LPCVD procedures, at a thickness between about 80 to 250 Angstroms. This is schematically shown in FIG. 6. A photoresist shape is then formed to protect the core devices from an ion implantation procedure used to form LDD region 11a, and from an in situ ion implantation procedure, used to form nitrogen region 11b. This is schematically shown in FIG. 7. LDD region 11a, and nitrogen region 11b, are formed using identical ion implantation species and conditions used to form LDD region 5, and nitrogen region 7, respectively, in the first iteration. Composite insulator spacers, and a heavily doped source/drain region, not shown in the drawings, are again formed using materials, and conditions, identical to those used in the first iteration to form heavily doped source/drain region 20, and the composite insulator spacers, comprised of TEOS oxide—silicon nitride. The I/O NMOS device, described in the second iteration, fabricated using one less masking step, then step than experienced in the first iteration, again results in the desired HCE injection reduction, as a result of the nitrogen implantation procedure. If desired the implantation procedures used for creation of LDD region 11a, and for creation of nitrogen region 11b, can be accomplished prior to deposition of TEOS liner layer 10.
FIG. 8, graphically represents the dopant profile for LDD region 13, obtained using the nitrogen implantation procedure, featured in the two iterations of this invention. The more graded profile of LDD region 13, compared to counterpart LDD region 12, formed without the nitrogen implantation procedure, resulting from enhanced TED phenomena, will reduce HCE injection. This is shown in FIG. 9, where time to fail, (TTF), influenced by HCE injection, is shown against unwanted substrate current, (Isub), which is in turn generated by HCE injection. The TTF is increased for samples 15, formed using the nitrogen implantation procedure, when compared to samples 14, formed without the nitrogen implantation procedure, featured in this invention. Less substrate current, or less HCE injection is encountered as a result of the nitrogen pile-up, and graded LDD profile, accomplished via the procedures described in this invention.
While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention.
Shih, Jiaw-Ren, Chiang, Mu-Chi, Lin, Hsien-Chin
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