control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals. control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
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3. A clock signal generating circuit comprising:
a clock forming circuit including,
a first delay circuit which receives a first clock having a first cycle and thereby outputs a second clock obtained by delaying the first clock;
a second delay circuit which outputs a second signal obtaining by delaying a first signal in response to the second signal; and
a control circuit which determines the state of the second signal at the time that a third clock having a second cycle has changed from a first level to a second level, in response to the third clock and the second signal, and outputs a control signal based on the result of determination to said first delay circuit; and
wherein said second delay circuit is set to an initial state in response to a fourth clock having the second cycle and formed on one semiconductor substrate.
0. 8. A semiconductor memory, comprising:
a clock forming circuit including,
a first variable delay circuit which receives a first clock and outputs a second clock obtained by delaying said first clock;
a second variable delay circuit which receives a first signal and outputs a second signal obtained by delaying said first signal;
a first delay circuit which receives said second signal and outputs a third signal;
a control circuit which compares said third signal and a fourth signal and controls said first variable delay circuits in accordance with the compared result; and
a signal generator which outputs said first and fourth signals, wherein said first delay circuit is able to be reset so that the remaining signal in said first delay circuit is erased after said control circuit compares said third signal and said fourth signal.
1. A clock signal generating circuit comprising:
a first delay circuit which receives a first clock signal and outputs a second clock signal, said second clock being a delayed signal to said first clock signal;
a first circuit which outputs a third clock signal, said third clock signal being a frequency-divided signal to said first clock signal;
a second circuit which outputs a fourth clock signal, said fourth clock signal being a frequency-divided signal to said second clock signal;
a second delay circuit which receives a fourth clock signal and outputs a fifth clock signal, said fifth clock signal being a delayed signal to said fourth clock signal; and
a control circuit which compares said third clock signal and said fifth clock signal and controls said first delay circuit so that an output timing of said second clock signal is changed.
0. 11. A semiconductor memory, comprising:
a clock forming circuit including, a first variable delay circuit which receives a first clock and outputs a second clock obtained by delaying said first clock;
a first delay circuit which receives a first signal and outputs a second signal obtained by delaying said first signal, said first delay circuit having a second variable delay circuit and second delay circuit which are connected in series;
a control circuit which compares said second signal and a third signal and controls said first variable delay circuits in accordance with the compared result; and
a signal generator which outputs said first and third signals, wherein said second variable delay circuit is able to be reset thereby the remaining signal in said second variable delay circuit is erased after the comparing operation of said control circuit.
0. 5. A semiconductor memory, comprising:
a clock forming circuit including a first variable delay circuit which receives a first clock signal and outputs a second clock signal obtained by delaying said first clock signal;
a second variable delay circuit which receives a first signal and outputs a second signal obtained by delaying said first signal;
a first delay circuit which receives said second signal and outputs a third signal;
a control circuit which compares said third signal and a fourth signal and controls said first variable delay circuit in accordance with the compared result; and
a signal generator which outputs said first and fourth signals, wherein said second variable delay circuit is able to be reset so that the remaining signal in said second variable delay circuit is erased after said control circuit compares said third signal and said fourth signal.
2. A clock signal generating circuit according to
4. A clock signal generating circuit according to
0. 6. A semiconductor memory according to
0. 7. A semiconductor memory according to
0. 9. A semiconductor memory according to
0. 10. A semiconductor memory according to
0. 12. A semiconductor memory according to
0. 13. A semiconductor memory according to
0. 14. A semiconductor memory according to
0. 15. A semiconductor memory according to
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This application
In a synchronous memory, for example, a delay time corresponding to the sum td1+td2 of a delay time td1 developed in an input clock buffer and a delay time td2 developed in a long wire is developed until a clock signal reaches an output data buffer from an external clock terminal. With the speeding up of a clock for a CPU (Central Processing Unit) employed in a computer system, there has recently been a demand for achievement of the speeding up of an interface portion with other various electronic circuits. Even a clock employed in the synchronous memory needs a high frequency domain like 100 to 200 MHz or higher. As described above, the function of the DLL circuit is to output an internal clock signal delayed m×tck−(td1+td2+td3) with respect to an external clock signal. The variable delay circuit in the DLL circuit needs to create a delay time of m×tckmax−(td1+td2+td3). Here, tckmax indicates the maximum clock cycle time. Further, m is an integer greater than 1 and is determined so as to satisfy m×tck−(td1×td2+td3)>0. When the frequency of the clock becomes high and tck<td1+td2+td3, m results in an integer greater than or equal to 2. When the clock frequency ranges from 100 MHz to 200 MHz, tck results in 10 to 5 nanoseconds. If m=2 in the DLL circuit activated in such a clock frequency range, then the maximum tdmax of a delay time to be created by the variable delay circuit reaches m×tck, i.e., 20 nanoseconds at the time that tck=10 nanoseconds. If tdrep=td1+td2+td3=5 nanoseconds, then the condition that the phase comparison is not misjudged at a clock frequency of 200 MHz, results in 5 (nanoseconds)+20 (nanoseconds)−2×5 (nanoseconds) <n×5 (nanoseconds)/2 from the above description (equation 1). Thus, the required number of frequency divisions n results in n>6. The number of the frequency divisions needs to a large one as the clock frequency increases.
It has been revealed by the present inventors that as is apparent from this point of view, a problem arises in that since it is necessary to perform the phase comparison according to a signal larger in the number of frequency divisions when the clock frequency in high, for the purpose of avoiding a misjudgment even if the phase comparison is done using the divided clock signal in the DLL circuit, a timing interval for controlling the delay time of the variable delay circuit becomes long and a lock-in cycle of the DLL circuit increases, thus causing a reduction in follow-up performance of the internal clock incident to a change in chip-in environment. If such a problem is left as it is, then the synchronous LSI using the DLL circuit brings about a situation in which as the lock-in cycle of the DLL circuit increases, the number of clock cycles necessary for its recovery from a standby state thereof increases, thus causing an impediment to an improvement in performance of a system with an improvement in clock frequency.
An object of the present invention is to provide a timing control circuit capable of effecting low power consumption on a circuit (including a dummy delay circuit) on a delay loop while a small area is being held as it is without increasing a variable delay circuit in number, and a semiconductor device having such a timing control circuit.
Another object of the present invention is to provide a timing control circuit capable of implementing low power consumption while a small area is being held as it is without increasing a variable delay circuit in number, and shortening a lock-in cycle, and a semiconductor device having such a timing control circuit.
A further object of the present invention is to provide a timing control circuit capable of performing clock phase control with high accuracy without a misjudgment on phase, and a semiconductor device having such a timing control circuit.
A still further object of the present invention is to provide a timing control circuit capable of reducing an interval for phase comparing timing without a fear of a misjudgment and shortening a time interval necessary for lock-in, and a semiconductor device having such a timing control circuit.
The above, other objects and novel features of the present invention will become apparent form the description of the present application and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] A semiconductor device according to the invention of the present application, in which attention has been focused on low power consumption and a reduction in area, performs control on an operating speed of a delay loop from the output of a variable delay circuit to a delay control input thereof. For example, frequency-dividing circuits are placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals.
Described more specifically, a semiconductor integrated device comprises a semiconductor chip including a clock input circuit which inputs an external clock signal, a timing control circuit which inputs a first internal clock signal outputted from the clock input circuit to thereby output a second internal clock signal, and an internal circuit which inputs the second internal clock signal outputted from the timing control circuit. The timing control circuit includes a variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal, a dummy delay circuit which reproduces an operation delay time of a predetermined circuit on the semiconductor chip and gives it to the second internal clock signal, a phase comparator which compares the phase of the first internal clock signal outputted from the clock input circuit and the phase of a signal outputted from the dummy delay circuit, a delay control circuit which controls a delay time of the variable delay circuit based on the result of comparison by the phase comparator, and speed control means which allows the dummy delay circuit, the phase comparator and the delay control circuit to operate at a frequency lower than that of the first internal clock signal.
According to the semiconductor integrated circuit, since the phase comparator, the delay control circuit and the dummy delay circuit are activated based on the frequency of the divided clock, power consumption is reduced. The variable delay circuits, which have been provided two in the prior art, can be set to one. It is also possible to reduce power consumption while an increase in circuit area is being controlled.
[2] A semiconductor integrated circuit according to the invention of the present application, in which attention has been focused on step signalization of a phase comparison signal in terms of the prevention of both a phase comparison determination malfunction and an increase in lock-in cycle, adopts a timing signal generator which generates a phase comparing timing signal having a step waveform. Further, the semiconductor integrated circuit adopts means which erases or resets a phase comparing timing signal transmitted to a delay loop after a phase comparing operation.
Described more specifically, a semiconductor device comprises a semiconductor chip including a clock input circuit which inputs an external clock signal, a timing control circuit which inputs a first internal clock signal outputted from the clock input circuit to thereby output a second internal clock signal, and an internal circuit which inputs the second internal clock signal outputted from the timing control circuit. The timing control circuit includes a variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal, a delay circuit which delays an input signal with a signal propagation delay time equivalent to the variable delay circuit, a dummy delay circuit which reproduces an operation delay time of a predetermined circuit on the semiconductor chip and adds the operation delay time to a signal outputted from the delay circuit, a phase determining circuit which determines the phase of a signal outputted from the dummy delay circuit, based on phase determining timing, a delay control circuit which controls a delay time of the variable delay circuit, based on the result of determination by the phase determining circuit, and a timing signal generator which, for every plural cycles of the first internal clock signal outputted from the clock input circuit, supplies a phase determining level signal to the delay circuit and supplies phase determining timing for the phase determining level signal, which is fed back to the phase determining circuit, to the phase determining circuit.
A reset control circuit is further provided which sets the outputs of the delay circuit and the dummy delay circuit to an initial level respectively after the phase determining timing.
The delay circuit may be comprised of another variable delay circuit which has the same circuit as the variable delay circuit and is subjected to the same control as the control on the variable delay circuit by the delay control circuit. That is, the variable delay circuits are placed side by side.
In order to reduce a circuit scale of the delay circuit, the delay circuit may comprise a shift register in which shift control terminals are successively coupled to a delay signal path of the variable delay circuit.
The timing signal generator generates a phase determining level signal (first phase comparing timing signal) and a phase determining timing signal (second phase comparing timing signal) as phase comparing timing signals every plural cycles of a first clock signal supplied to a variable delay circuit. The second phase comparing timing signal is delayed m clock cycles with respect to the first phase comparing timing signal. The first phase comparing timing signal is transmitted to the variable delay circuit which constitutes a delay loop, whereas the second phase comparing timing signal is transmitted to a phase comparator. When a phase comparing operation is completed, a phase comparison control circuit next outputs a timing signal request signal for making a request to the timing signal generator for the generation of an additional phase comparing timing signal, for example. The variable delay circuit and dummy delay circuit constituting the delay loop, and the timing signal generator erase the phase comparing timing signal which remains within the delay loop. The timing signal generator additionally generates first and second phase comparing timing signals.
Thus, the timing control circuit according to the present invention utilizes the timing signal having the step waveform, which is different from the divided clock signal upon phase comparison, erases the phase comparing timing signal remaining within the delay loop along with the completion of the phase comparing operation, and immediately starts the next phase comparison. It is therefore possible to shorten the interval for timing provided to perform phase comparison to the minimum without any misjudgment. Accordingly, the timing control circuit can shorten the intervals for the timing provided to perform phase comparison and the timing provided to control the delay time of the variable delay circuit and is capable of reducing a lock-in cycle.
[3] The divided clock signal may be introduced in the delay loop in the configuration of the step signalization in the delay loop.
That is, a semiconductor device comprises a semiconductor chip including a clock input circuit which inputs an external clock signal, a timing control circuit which inputs a first internal clock signal outputted from the clock input circuit to thereby output a second internal clock signal, and an internal circuit which inputs the second internal clock signal outputted from the timing control circuit. The timing control circuit has a first variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal, a second variable delay circuit having the same circuit configuration as the first variable delay circuit, a dummy delay circuit which reproduces an operation delay time of a predetermined circuit on the semiconductor chip and gives it to a signal outputted from the second variable delay circuit, a phase determining circuit which determines the phase of a signal outputted from the dummy delay circuit, based on phase determining timing, a delay control circuit which controls delay times of the first and second variable delay circuits to the same, based on the result of determination by the phase determining circuit, a frequency-dividing circuit which outputs the first internal clock signal outputted from the clock input circuit as it is or divides it and outputs the same therefrom, and a timing signal generator which, for every plural cycles of the clock signal outputted from the frequency-dividing circuit, supplies a phase determining level signal to the second variable delay circuit and supplies phase determining timing for the phase determining level signal, which is fed back to the phase determining circuit, to the phase determining circuit. Dividing the clock signal by the frequency-dividing circuit after lock-in makes it possible to promptly complete a lock-in operation and contribute to low power consumption after the lock-in.
When the frequency-divided signal is used, the timing control circuit may adopt a follow-up circuit like a shift register as a delay circuit. The timing control circuit considered from this point of view comprises a variable delay circuit which inputs the first internal clock signal to thereby output the second internal clock signal, a delay circuit having a shift register configuration in which shift control terminals are successively coupled to a delay signal path of the variable delay circuit and an input signal is delayed with a signal propagation delay time equivalent to the variable delay circuit, a dummy delay circuit which reproduces an operation delay time of a predetermined circuit on the semiconductor chip and adds the operation delay time to a signal outputted from the delay circuit, a phase determining circuit which determines the phase of a signal outputted from the dummy delay circuit, based on phase determining timing, a delay control circuit which feedback-controls a delay time of the variable delay circuit, based on the result of determination by the phase determining circuit, a frequency-dividing circuit which outputs the first internal clock signal outputted from the clock input circuit as it is or divides the first internal clock signal and outputs the same therefrom, and a timing signal generator which, for every plural cycles of the clock signal outputted from the frequency-dividing circuit, supplies a phase determining level signal to the delay circuit and supplies the phase determining timing for the phase determining level signal, which is fed back to the phase determining circuit, to the phase determining circuit. The frequency-dividing circuit performs frequency division after lock-in. Thus, this makes it possible to immediately complete a lock-in operation and contribute to low power consumption after the lock-in.
After the phase determining timing, the outputs of the delay circuits and the dummy delay circuit may be reset to an initial level respectively.
[4] In a semiconductor integrated circuit to which the configuration of step signalization in the delay loop is applied, when the internal circuit is an output circuit which performs an external output operation in synchronism with a change in the second internal clock signal, the dummy delay circuit is a delay circuit which reproduces a time interval corresponding to the sum of an operation delay time of the clock input circuit, an operation delay time of the output circuit, a delay time developed in a wire extending from the clock input circuit to the timing control circuit, and a delay time developed in a wire extending from the timing control circuit to the output circuit.
Such a semiconductor device implements, for example, a clock synchronous memory. For example, the clock synchronous memory further includes a processing circuit which is connected to the output circuit and processes data to be outputted from the output circuit. The processing circuit has a memory cell array and a selection circuit which selects a memory cell from the memory cell array. The output circuit corresponds to an output data latch circuit which latches information stored in the memory cell selected from the memory cell array, and a data output buffer connected to the output data latch circuit. The output timing signal is a latch control signal for the output data latch circuit.
Typical ones of various inventions of the present inventions have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the invention, it is believed that the invention, the objects and features of the invention and further objects, features and advantages thereof will be better understood from the following description taken in connection with the accompanying drawings in which:
<<Semiconductor Device>>
One example of a semiconductor device according to the present invention is shown in
<<Delay Loop Frequency-division Type Timing Control Circuit>>
One example of a feedback loop dividing type DDL circuit 114 is illustrated in
The timing control circuit shown in
In the circuit shown in
A further detailed example of the DLL circuit 114 shown in
One example of the variable delay circuit is shown in
The operation of the variable delay circuit 103 will be described. Differential signals INP and INN are first inputted. The signals INP and INN pass through the differential delay stages 801 over the plural stages and are outputted as signals OUTP and OUTN from the clock signal output terminal 102 with given delay times. The delay times of the respective differential delay stages 801 respectively result in time constants based on resistances of the load MOS transistors and parasitic capacitance of an output unit. Since each differential delay stage 801 changes in output resistance when the voltage of the delay control signal CNTLP is now changed, the time constant, i.e., delay time based on the output resistance of each differential delay stage 801 and the parasitic capacitance of the output unit can be controlled by changing the voltage of the delay control signal CNTLP. Incidentally, as will be described in the subsequent section of bias circuit, the signal CNTLN is used to change a current flowing through the NMOS current source transistor Q7n, based on its voltage, and control or restrain a variation in output voltage amplitude of each differential delay stage with respect to a variation in process and a variation in source voltage.
One example of the delay control circuit is illustrated in
One example of the pulse generator 905 is illustrated in
One example of the charge pump circuit 906 is illustrated in
One example of the bias circuit 908 is shown in FIG. 11. The bias circuit 908 generates a signal CNTLN for controlling the MOS transistor Q7n of each differential delay stage 801 in the variable delay circuit 103 and a signal CNTLP for controlling the MOS transistors Q4p and Q5p from the voltage applied to the VB signal terminal 914. Delay times of the respective differential delay stages constituting the variable delay circuit 103 respectively result in time constants based on on resistances of the MOS transistors Q4p and Q5p and parasitic capacitance of an output unit. Since each differential delay stage changes in output resistance when the voltage of the phase comparison signal input terminal CNTLP is changed, the time constant, i.e., delay time based on the output resistance of each differential delay stage and the parasitic capacitance of the output unit can be controlled by changing the voltage of the signal CNTLP at the delay control signal terminal. That is, when the voltage of the signal CNTLP is reduced, the mutual conductance (gm) of each P channel MOS transistor increases and the output resistance (l/gd) is lowered. Since the time constant corresponds to the product of the output resistance and the parasitic capacitance of the output unit, it is reduced at this time and the delay time becomes short. On the other hand, when the voltage of the signal CNTLP is increased, the mutual conductance of the P channel MOS transistor Q decreases and the output resistance increases. At this time the time constant increases and the delay time becomes long.
Thus, when the phase of the internal clock signal lag, the voltage applied to the VB signal terminal 914 is lowered and the voltage of the signal CNTLP at the bias signal terminal 903 of each differential delay stage 801 in the variable delay circuit 103 is controlled so that the time constant based on the product of the output resistance of each differential delay stage 801 in the variable delay circuit 103 and the parasitic capacitance of the output unit is reduced to shorten the delay time. When the phase of the internal clock signal leads, the voltage of the signal CNTLP at the bias signal terminal 903 of each differential delay stage 801 in the variable delay circuit 103 is increased, and the time constant based on the product of the output resistance of each differential delay stage 801 in the variable delay circuit 103 and the parasitic capacitance of the output unit is made great, thereby controlling the delay time so as to become long. The bias circuit 908 has the same differential delay stage 920 as the differential delay stage 801. One input terminal of the differential delay stage 920 is connected to a source VDD high in voltage. Thus, a node 917 in the differential delay stage 920 corresponds to the output node of the differential delay node 801, and the voltage applied to the node 917 becomes equal to a low limit voltage of an output signal voltage. Owing to the operation of an op amplifier 916, such a current as to equalize the voltage at the node 917 and the voltage at the VB signal terminal 914 to each other flows through a MOS transistor 918 of the differential delay stage 920. A voltage outputted from the op amplifier 916 is outputted from the output terminal 904 as the signal CNTLN. Further, the voltage at the node 917, i.e., the same voltage as that for the VB signal inputted to the terminal 914 is outputted from the output terminal 903 as the signal CNTLP of the differential delay stage 920. In other words, the bias circuit 908 provides the voltage at the output terminal 904 corresponding to the signal CNTLN of the differential delay stage 801 in the variable delay circuit 103 so that the voltage of the signal VB at the terminal 914 reaches the low limit of the output voltage of the differential delay stage 801 in the variable delay circuit 103.
As described above, the circuit shown in
One example of the divide-by-eight frequency circuit 107 is shown in FIG. 12. The divide-by-eight frequency circuit 107 comprises an input terminal 1001 for a clock signal, an input terminal 1003 for a reset signal RESET, a terminal 1002 for an output signal, three divide-by-two frequency circuits 1004, 1005 and 1006 connected in series, and two flip-flops 1007 and 1008 connected in series.
The operation of the divide-by-eight frequency circuit 107 will be described. The reset signal RESET is inputted to the input terminal 1003 for initialization. Thus, the first flip-flop 1007, the second flip-flop 1008 and the first through third divide-by-two frequency circuits 1004 through 1006 are initialized so that the output signal is brought to an “L” level. Now consider where the reset signal RESET is a positive pulse signal. Next, the clock signal is supplied to the clock signal input terminal 1001. The clock signal is inputted to the first divide-by-two frequency circuit 1004. The first divide-by-two frequency circuit 1004 divides the clock signal by two to thereby obtain a divided-by-two clock signal. Further, the second divide-by-two frequency circuit 1005 divides the clock signal by two to thereby obtain a divided-by-four clock signal. Furthermore, the third divide-by-two frequency circuit divides the clock signal by two to thereby produce a divided-by-eight clock signal. Thereafter, the divide-by-eight clock signal passes through the first flip-flop 1007 and the second flip-flop 1008 over two clock cycles and is outputted as an output signal from the output signal terminal 1002. The circuit shown in
One example of the divide-by-two frequency circuit 1004 is shown in
One example of the flip-flop 1023 shown in
One example of the divide-by-eight frequency circuit 108 is illustrated in FIG. 15. The divide-by-eight frequency circuit 108 comprises an input terminal 1009 for a clock signal IN8b, an input terminal 1012 for a reset signal RESET, a terminal 1010 for an output signal, three divide-by-two frequency circuits 1013, 1014 and 1015 arranged in series, and a dummy delay circuit 1016. The dummy delay circuit 1016 is a circuit for reproducing a delay time of the flip-flop 1008. The first through third divide-by-two frequency circuits 1013, 1014 and 1015 respectively have the same circuit configuration as the divide-by-two frequency circuit 1004 shown in FIG. 13.
One example of the dummy delay circuit 1016 for reproducing the delay time of the flip-flop 1008 is shown in FIG. 16. The circuit shown in the same drawing is one obtained by extracting a path extending from a clock signal input terminal 1301 of the flip-flop 1023 to an output signal terminal 1304 thereof while a load is being held as it is. The circuit reproduces the delay time of the flip-flop 1008.
The operation of the divide-by-eight frequency circuit 108 shown in
One example of the dummy delay circuit 106 is illustrated in FIG. 17. The function of the dummy delay circuit 106 aims to reproduce the delay time tdrep developed in the input clock buffer, long wire and output data buffer. According to
The first through seventh delay circuits 1101 through 1107 are used to correct variations in delay time due to a variation in chip's process. A signal path employed in the present circuit passes from the input signal terminal 1110 to the eighth delay circuit 1108 and reaches the output signal terminal 1120 through the buffer 109. However, each of the first through seventh delay circuits 1101 through 1107 can be selected as a path formed between the eighth delay circuit 1108 and the buffer 1109. While the first through seventh delay circuits 1101 through 1107 are respectively comprised of series-stages of inverters. However, they are different from one another in constants of MOS circuits constituting the respective circuits (MOS transistor size) and different in delay time from one another. However, even if any of the first through seventh delay circuits 1101 through 1107 is selected, the delay time of the present circuit is designed to approach the delay time tdrep developed in the input clock buffer, long wire and output data buffer. Further, the difference in delay time between the respective adjacent first through seventh delay circuits 1101 through 1107 is kept small sufficiently. Therefore, such first through seventh delay circuits 1101 through 1107 that the delay time of the present circuit most approximates the delay time tdrep developed in the input clock buffer, long wire and output data buffer after the fabrication of a chip, are selected through the use of the first through seventh fuse circuits 111 through 1117 respectively. For example, the selection of the seventh delay circuit 1107 will be explained. Now consider where any fuses lying within the first through seventh fuse circuits 1111 through 1117 are not cut off or blown. Since, at this time, the inputs of inverters of the first through seventh fuse circuits 1111 through 1117 are an “H” level respectively, the outputs thereof are “L” in level. Thus, NAND circuits (NAND gates) 1122 in the first through seventh fuse circuits 1111 through 1117 and clocked inverters 1123 located in final stages of the first through seventh delay circuits 1101 through 1107 are respectively kept in a high output impedance state (off state). Thus, the input of the buffer 1109 is undefined. Next, the fuse 1118 lying within the seventh fuse circuit 1117 is cut off or blown. In doing so, the voltage inputted to the inverter 1119 provided within the seventh fuse circuit 1117 is reduced by leakage current flowing through a MOS transistor 1121 provided within the seventh fuse circuit 1117 so that the output voltage of the inverter 1119 is inverted to thereby reach an “H” level. Thus, the NAND circuit 1122 provided within the seventh fuse circuit 1117 and the final-stage clocked inverter 1123 provided within the seventh delay circuit 1107 are capable of output operation, so that the seventh delay circuit 1107 becomes effective as a signal path. Since the delay time of the circuit shown in
One example of the phase comparator 104 is illustrated in FIG. 18. The function of the phase comparator 104 is to compare input two timing signals, output an “H” level if rise timing of the second timing signal leads that of the first timing signal, and output an “L” level if the rise timing thereof lags that of the first timing signal. According to
The reset signal RESET is inputted to the phase comparator 104 shown in
According to the timing control circuit 114 constructed as described above, since the frequency-dividing circuit 108 is provided midway between the variable delay circuit and the dummy delay circuit, and the dummy delay circuit 106 is activated by each divided clock without increasing the variable delay circuit in number, low power can be implemented in a small area.
The above-described area reducing effect will be verified in further details. When a delay increment or step is defined as 100 ps and the maximum delay time is defined as 20 ns in each variable delay circuit of a timing control circuit using such two variable delay circuits as illustrated in
<<Phase Comparison Signal Step-signalizing Timing Control Circuit>>
One example of a timing control circuit for bringing a phase comparison signal into step signal form is shown in
The timing control circuit shown in
The clock signal EXTCLK is inputted from the clock terminal 101. Further, the clock signal is sent to the first variable delay circuit 201 and additionally transmitted even to the timing signal generator 205. The timing signal generator 205 generates the first phase comparing timing signal 211 and the second phase comparing timing signal 212. Let's now consider where the first phase comparing timing signal 211 and the second phase comparing timing signal 212 are respectively signals having step waveforms, each of which indicates timing on one rising or falling edge, and the second phase comparing timing signal 212 is delayed m clock cycles with respect to the first phase comparing timing signal 211. Next, the first phase comparing timing signal 211 is sent to the second variable delay signal 202 and the second phase comparing timing signal 212 is sent to the phase comparator 203. The delay time of the first phase comparing timing signal 211 sent to the second variable delay circuit 202 is controlled based on a delay control signal 210 outputted from the delay control circuit 204 in a manner similar to the delay time developed in the first variable delay circuit 201. The first phase comparing timing signal 211 passes through the second variable delay circuit 202 and thereafter passes through the dummy delay circuit 207 so as to enter the phase comparator 203. Next, the phase comparator 203 compares timing for the second phase comparing timing signal 212 and that for a phase comparing timing signal 213 (second signal) obtained by allowing the first phase comparing timing signal 211 to pass through the second variable delay circuit 202 and the dummy delay circuit 207. The result of comparison by the phase comparator 203 is outputted to the delay control circuit 204 as a phase comparison signal 214. The delay control circuit 204 outputs a delay control signal 210 in such a manner that when the phase comparing timing signal 213 obtained by allowing the first phase comparing timing signal 211 to pass through the second variable delay circuit 202 and the dummy delay circuit 207 lags the second phase comparing timing signal 212, it shortens the delay times developed in the first and second variable delay circuits 201 and 202 and when the phase comparing timing signal 213 leads the second phase comparing timing signal 212 in reverse, it lengthens the delay times developed therein, thereby controlling the delay times of the first and second variable delay circuits 201 and 202.
In response to the second phase comparing timing signal 212, the phase comparison control circuit 216 outputs a timing signal request signal 219 for making a request to the timing signal generator 205 for the generation of new first and second phase comparing timing signals 211 and 212. Next, when the variable delay circuit 202 and the dummy delay circuit 207, which form a delay loop, obtain the timing signal request signals 219 respectively, they reset their outputs to an “L” level and thereby erase the internally-remaining phase comparing timing signals. When the timing signal generator 205 obtains the timing signal request signal 219, it generates new first and second phase comparing timing signals 211 and 212 in synchronism with the rising edge of the next external clock.
Owing to the repetition of the above phase comparison control over m+1 clock cycles, the timing for the phase comparing timing signal 213 obtained by allowing the first phase comparing timing signal to pass through the second variable delay circuit 202 and the dummy delay circuit 207 can be matched with that for the second phase comparing timing signal 212, whereby the internal clock signal INTCLK delayed m×tck−tdrep with respect to the clock signal EXTCLK inputted to the terminal 101 can be obtained at the terminal 102. Incidentally, the timing signal request signal 219 will be defined as a signal having a positive pulse waveform.
Phase lock operating timings provided by the timing control circuit shown in
The circuit described in
One example of a variable delay circuit 202 with a reset function is illustrated in FIG. 23. The function of the variable delay circuit 202 is to output an input signal with a delay of a predetermined time according to delay control signals 210 and erase the internally-remaining phase comparing timing signal in response to a timing signal request signal 219.
The variable delay circuit 202 is comprised of a variable delay stage 703 to which a reset circuit 1604 is added. The variable delay stage 703 comprises delay stages connected in series in multistage form, each of which is comprised of two two-input NAND gates 710 and 711 and an inverter 712. One of the signals (S1 through S4) represented in a plurality of bits is set to “H” so as to allow a clock signal CLKIN to pass through with the delay stage receiving the corresponding signal of “H” as a base point. Thus, the control of the delay stages for allowing the signal CLKIN to pass through makes it possible to change the delay of the signal, i.e., the phase thereof.
The reset circuit 1604 is a circuit for resetting an output CLKOUT to an “L” level and thereby erasing the internally-remaining phase comparing timing signal. The reset circuit 1604 has p channel switch MOS transistors 720 between the outputs of the NAND gates 710 of the respective delay stages and source terminals VDD and are configured such that the gates of the MOS transistors 720 are controlled based on an inverted signal of a reset signal RESET. When all the MOS transistors 720 are turned on, the inputs of the inverters 712 in all the delay stages are respectively brought to “H” of the source voltage VDD. Thus, when a timing signal request signal 219 having a positive pulse waveform is inputted to the reset terminal 1602 as the reset signal, the gates of the MOS transistors 720 are brought to “L” through the inverter 721 and hence the outputs of all the delay stages are reset to “L”.
One identical to the variable delay circuit 202 may be used as the variable delay circuit 201. However, since no resetting is required, the reset signal input terminal 1602 may be pulled down to a ground voltage VSS so as to be fixed to the “L” level.
Although not shown in the drawing in particular, the delay control circuit 204 shown in
One example of the dummy delay circuit 207 is shown in FIG. 24. The dummy delay circuit 207 provides the function of reproducing a delay time tdrep developed in an input clock buffer, a long wire and an output data buffer and erasing the internally-remaining phase comparing timing signal in response to a timing signal request signal 219. The dummy delay circuit 207 shown in
That is, a reset switch circuit comprised of MOS transistors 1720 is formed within the delay circuit 1704 of the dummy delay circuit 207 of
A detailed example of the timing signal generator 205 is shown in FIG. 27. The timing signal generator 205 generates a first phase comparing timing signal 211 and a second phase comparing timing signal 212 in response to a timing signal request signal 219. Here, the first and second phase comparing timing signals 211 and 212 are respectively signals represented in the form of step waveforms, each of which is indicative of timing on one rising edge or falling edge. The second phase comparing timing signal 212 needs to be delayed m clock cycles with respect to the first phase comparing timing signal 211. Here, m indicates an integer greater than 1.
Referring to
Operating timings of the timing signal generator 205 are illustrated in
Prior to the operation of the timing signal generator 205, a reset signal having a positive pulse waveform is supplied to the reset signal input terminal 1503. Thus, the D flip-flop 1507 is initialized. Next, a timing signal request signal 219 having a positive pulse waveform is supplied to the terminal 1501. In doing so, the second RS latch 1511 and m-stage D flip-flops 1513 and 1514 are initialized so that the outputs of the respective stages are brought to an “L” level respectively. At this time, the first RS latch 1506 is set so that a signal 1515 outputted therefrom is brought to an “H” level. On the other hand, a clock signal is supplied to the terminal 1502. The D flip-flop 1507 outputs the output data of the first RS latch 1506 with the fall timing of the clock. The present signal 1515 is a timing signal generation enable signal for permitting the generation of a timing signal. The signal 1515 is inputted to the AND circuit 1508. Next, the AND gate 1509 outputs an “H” level on the rise timing of the clock when the timing signal generation enable signal 1515 is “H” in level, and outputs an “L” level on the rise timing thereof when the timing signal generation enable signal 1515 is “L” in level. In doing so, an “H” level appears at the output of the second RS latch 1511 when the timing signal generation enable signal 1515 is “H” in level and hence a rise step waveform is outputted from the second RS latch 1511. This step waveform appears at the terminal 1504, which is used as a first phase comparing timing signal. At this time, the first phase comparing timing signal is inputted even to the pulse generator 1509, which generates a pulse signal having a pulse width determined according to a delay time developed in a delay circuit 1510 provided within the pulse generator 1509. This pulse signal is inputted to a reset terminal R of the first RS latch 1506 to thereby bring the timing signal generation enable signal to an “L” level on the fall timing of the next clock.
Incidentally, the first phase comparing timing signal 211 having the step waveform, which has been outputted from the second RS latch 1511, passes through the delay circuit 1512, followed by inputting to the m-stage D flip-flops 1513 and 1514, which in turn appears at the terminal 1505 after the elapse of m clock cycles. This results in the second phase comparing timing signal 212. Incidentally, the delay of the delay circuit 1512 is done to prevent a hazard from occurring in the output of the D flip-flop 1513 when a signal change timing at the input unit of the D flip-flop 1513 and the rise timing of the clock signal approach each other. This aims to separate the signal change timing at the input unit of the D flip-flop 1513 from the rise timing of the clock signal.
One example of the phase comparison control circuit 216 is shown in FIG. 29. The phase comparison control circuit 216 generates a timing signal request signal 219, based on the second phase comparing timing signal 212.
Referring to
The operation of the phase comparison control circuit 216 will next be described. When a second phase comparing timing signal 212 having a rise step waveform is first inputted to the terminal 1801, the signal enters the pulse generator 1806 from which a signal having a positive pulse waveform is outputted. Incidentally, the pulse generator 1806 outputs a signal having a positive pulse waveform even when a fall step waveform is outputted to the terminal 1801. Next, the positive pulse signal outputted from the pulse generator 1806 is inputted to one input terminal of the AND gate 1805. At this time, the other input terminal of the AND gate 1805 is supplied with the second phase comparing timing signal 212. Thus, the signal having the positive pulse waveform is outputted to the terminal 1803 only when the second phase comparing timing signal 212 is represented as the rise step waveform. Further, the pulse signal outputted from the pulse generator 1806, which appears when the second phase comparing timing signal 212 is of the fall step waveform, is cut off by the AND gate 1805 and thereby not outputted therefrom. That is, when the second phase comparing timing signal 212 having the rise step waveform is inputted, the signal having the positive pulse waveform is outputted from the terminal 1803. This results in a timing signal request signal 219.
While the timing control circuit shown in
The effect of shortening a lock-in time by the timing control circuit shown in
<<Speed Control on Delay Loop and Step Signalization of Phase Comparison Signal>>
One example of a timing control circuit, which brings a phase comparison signal into step signalization and permits speed control on a delay loop, is illustrated in
The timing control circuit shown in
The variable delay circuit 302 receives or inputs a signal outputted from the dummy delay circuit 301 and outputs a clock signal to the terminal 102. The follow-up circuit 2218 is a delay circuit having a shift register configuration in which shift control terminals are successively coupled to a delay signal path of the variable delay circuit 302 and the input signal is delayed with a signal propagation delay time equivalent to that of the variable delay circuit 302. The dummy delay circuit 307 gives a predetermined delay time to a signal outputted from the timing signal generator 306 so that it is reproduced. The phase of a signal outputted from the dummy delay circuit 307 is compared with that of a signal 313 with a phase determining timing given by the signal 313 by the phase comparator 308. The delay control circuit 309 feedback-controls the delay time of the variable delay circuit 302 based on the result of determination by the phase comparator 308. The divide-by-eight frequency circuit 303 outputs the clock signal supplied from the terminal 101 as it is or frequency-divides it and outputs it therefrom. Every plural cycles of the clock signal outputted from the divide-by-eight frequency circuit 303, the timing control circuit 304 supplies a comparison pulse follow-up request signal 320 defined as a phase determining level signal to the delay circuit 2218 and supplies phase determining timing with respect to the phase determining level signal fed back to the phase comparator 308 to the phase comparator 308 through the signal 313. The phase comparison control circuit 312 functions as a reset control circuit for bringing the outputs of the follow-up circuit 2218 and the dummy delay circuit 307 or the like to an initial level respectively after the phase determining timing.
The divide-by-eight frequency circuit 303 outputs the clock signal supplied from the terminal 101 as it is before a lock-in state is detected from the result of phase determination by the phase comparator 308. After the attainment to the lock-in state has been detected from the result of phase comparison, the divide-by-eight frequency circuit 303 selects and outputs the divided signal. Correspondingly, the timing signal generator 306 selects the output signal of the variable delay circuit 302 before the lock-in state is detected from the result of phase determination by the phase comparator 308, and selects the output of the follow-up circuit 2218 after the lock-in state has been detected from the result of phase comparison.
Operating timings of the timing control circuit shown in
The operation of the timing control circuit shown in
During the first operation up to the lock-in, the divide-by-eight frequency circuit 303 causes an external clock signal EXTCLK (first clock) supplied from the terminal 101 to pass therethrough as it is. During the second operation subsequent to the lock, the divide-by-eight frequency circuit 303 divides the external clock signal by eight. Switching between these is done based on a frequency-division switching signal 322 outputted from the on-lock frequency-division switching circuit 310.
Prior to the operation, a reset signal is first inputted to bring the outputs of each flip-flop and a latch in the circuit to an “L” level. This is a positive pulse signal. Next, the external clock signal is inputted to the external circuit input terminal 101 during the first operation. The clock signal is sent to the dummy delay circuit 301 and the divide-by-eight frequency circuit 303. During the first operation, the divide-by-eight frequency circuit 303 outputs the input clock signal as it is.
Next, the signal outputted from the divide-by-eight frequency circuit 303 is inputted to the timing signal generator 304. If the timing signal generator 304 receives a timing signal request signal 319 in advance at this time, then the timing signal generator 304 outputs a comparison pulse follow-up request signal 320 for making a request to the follow-up circuit 2218 for the follow-up of a clock pulse corresponding to timing used for phase comparison, to the follow-up circuit 2218, and outputs a first phase comparing timing signal 313 to the phase comparator 308.
Now consider where the first phase comparing timing signal 313 is a signal given in a step waveform, which is indicative of timing by one rise waveform and which is delayed m clock cycles with respect to the output signal of the divide-by-eight frequency circuit 303. Further, the timing signal request signal 319 is a positive pulse signal. Now, one sent to the dummy delay circuit 301, of the external clock signal is outputted to the variable delay circuit 302 and the follow-up circuit 2218 after the delay thereof by the dummy delay circuit 301. The dummy delay circuit 301 and the variable delay circuit 302 constitutes a first delay circuit. This is intended to input the clock signal to the variable delay circuit 302 after the comparison pulse follow-up request signal 320 has reached the follow-up circuit 2218. Next, the delayed clock signal is inputted to the variable delay circuit 302 and outputted after the elapse of a delay time controlled by a delay control signal 323, which in turn is outputted from the internal clock output signal terminal 102 as an internal clock signal INTCLK (second clock).
At this time, the timing signal generator 306 is supplied with the output of the variable delay circuit 302 and a comparison pulse attainment prediction signal 321 outputted from the follow-up circuit 2218. The comparison pulse attainment prediction signal 321 is a positive step signal, which is inputted prior to within one clock cycle in which a clock pulse corresponding to timing used for phase comparison reaches the timing signal generator 306. That is, a clock pulse, which is to first arrive since the reception of the comparison pulse attainment prediction signal 321, results in a clock pulse corresponding to the timing used for phase comparison. Incidentally, the comparison pulse attainment prediction signal 321 is reset by the timing signal request signal 319. Next, the internal clock signal enters the timing signal generator 306. If the comparison pulse attainment prediction signal 321 is already inputted to the timing signal generator 306, then the timing signal generator 306 outputs a second phase comparing timing signal 316.
Here, the second phase comparing timing signal (first signal) 316 is a signal having a positive step waveform, which indicates timing by one rise waveform. The second phase comparing timing signal 316 passes through the dummy delay circuit (second delay circuit) 307 so as to enter the phase comparator 308. Next, the phase comparator 308 compares the timing for the first phase comparing timing signal 313 and that for a timing signal (second signal) 314 obtained by allowing the second phase comparing timing signal 316 to pass through a dummy delay circuit 1307. The result of comparison by the phase comparator 308 is outputted to the delay control circuit 309 as a phase comparison signal 315. The delay control circuit 309 outputs a delay control signal 323 in such a manner that when the timing signal 314 lags the first phase comparing timing signal (third clock) 313, the delay control circuit 309 shortens the delay time developed in the variable delay circuit 302, and when the timing signal 314 leads the first phase comparing timing signal 313 in reverse, it lengthens the delay time developed in the variable delay circuit 302, thereby controlling the delay time developed in the variable delay circuit 302.
Next, the phase comparison control circuit 312 outputs a timing signal request signal (fourth clock) 319 for making a request to the timing signal generator 304 for the generation of a new first phase comparing timing signal 313. Next, the timing signal generator 304 generates a new first phase comparing timing signal 313 when its obtains the timing signal request signal 319.
Owing to the implementation of the above control for a sufficient time, the timing for the timing signal 314 obtained by allowing the second phase comparing timing signal 316 to pass through a dummy delay circuit 1307 can be matched with that for the first phase comparing timing signal 313. Thus, an internal clock signal delayed m×tck−tdrep with respect to the external clock signal inputted to the terminal 101 can be obtained at the terminal 102. Incidentally, each of the phase comparison completion signal 317 and a delay signal attainment signal 318 is defined as a signal having a rise step waveform. Further, the timing signal request signal 319 is defined as a signal having a positive pulse waveform.
The second operation subsequent to the lock-in will next be explained. Prior to the second operation, the on-lock frequency-division switching circuit 310 first determines based on a time-sequential change in the phase comparison signal 315 whether the timing control circuit has locked in. If it is determined that it has locked in, then the on-lock frequency-division switching circuit 310 outputs a frequency-division switching signal 322. When the divide-by-eight frequency circuit 303 receives the frequency-division switching signal 322 therein, it changes the output thereof to a divided-by-eight clock signal. This results in a shift to the second operation. During the second operation, the divide-by-eight frequency circuit 303 is rendered effective, so that the parts other than the dummy delay circuit 301 and variable delay circuit 302 through which the clock signal passes, are activated according to the divided-by-eight clock.
Incidentally, the parts other than the variable delay circuit 201 can be activated based on the divided-by-eight clock subsequently to the lock-in in a manner similar to the above even in the case of the timing control circuit described with reference to
One example of the divide-by-eight frequency circuit 303 is shown in FIG. 32. The divide-by-eight frequency circuit 303 is capable of perform switching between the output of a divided-by-eight clock signal and the output of an input signal as it is, based on a frequency-division switching signal. The divide-by-eight frequency circuit 303 comprises an input signal terminal 1902, a frequency-division switching signal input terminal 1903, a reset signal input terminal 1904, an output signal terminal 1905, three divide-by-two frequency circuits 1004, and a selector 1906. A specific example of the selector 1906 is shown in FIG. 33. In
In the divide-by-eight frequency circuit 303, a positive pulse signal is first inputted to the reset signal input terminal 1904, and the outputs of the three divide-by-two frequency circuits 1004 are respectively initialized to an “L” level. Next, a clock signal is inputted to the input signal terminal 1902. On the one hand, the input clock signal passes through the three divide-by-two frequency circuits 1004 to thereby produce a divided-by-eight signal, followed by inputting to a first input terminal IN1 of the selector 1906. On the other hand, the input clock signal enters a second input terminal IN0 of the selector 1906 as it is. If a signal supplied to a selection signal terminal SEL is of an “H” level, then the selector 1906 outputs the signal inputted to the input signal terminal IN1. If the signal supplied to the selection signal terminal SEL is of an “H” level, then the selector 1906 outputs the signal inputted to the input signal terminal IN0. That is, if the signal supplied to the selection signal terminal SEL is of the “H” level, then the divide-by-eight frequency circuit 303 outputs a divided-by-eight clock signal. If the signal supplied to the selection signal terminal SEL is of the “L” level, then the divide-by-eight frequency circuit 303 outputs the input clock signal as it is.
One example of the timing signal generator 304 is shown in FIG. 34. The timing signal generator 304 generates a first phase comparing timing signal 313 and a comparison pulse follow-up request signal 320 in response to a timing signal request signal 319. Here, the first phase comparing timing signal 313 and comparison pulse follow-up request signal 320 are respectively signals represented in the form of step waveforms, each of which is indicative of timing on one rise waveform. The first phase comparing timing signal 313 needs to be delayed m clock cycles as viewed from the rising edge of the next output signal of the divide-by-eight frequency circuit 303 in response to the timing signal request signal 319. Here, m indicates an integer greater than 1. Further, the comparison pulse follow-up request signal 320 needs to be synchronized with the rising edge of the next output signal of the divide-by-eight frequency circuit 303 in response to the timing signal request signal 319.
In
The operation of the timing signal generator 304 will next be explained. Prior to its operation, a reset signal having a positive pulse waveform is first supplied to the reset signal input terminal 2003. Thus, the D flip-flop 2007 is initialized. Next, a timing signal request signal having a positive pulse waveform is supplied to the terminal 2001. In doing so, the second RS latch 2011 and the m-stage D flip-flops 2013 and 2014 are initialized so that the outputs of the respective stages are respectively brought to an “L” level. At this time, the first RS latch 2006 is set so that a signal 2015 outputted therefrom is brought to an “H” level.
The terminal 2002 is supplied with a clock signal outputted from the divide-by-eight frequency circuit 303. The D flip-flop 2007 outputs data outputted from the first RS latch 2006 on the fall timing of the clock. The signal 2015 is a timing generation enable signal for permitting the generation of a timing signal. The signal 2015 is inputted to the AND gate 2008.
Next, when the timing generation enable signal 2015 is of an “H” level on the rise timing of the clock outputted from the divide-by-eight frequency circuit 303, the “H” level is outputted from the AND gate 2008. On the other hand, when the timing generation enable signal 2015 is of an “L” level on the rise timing thereof, the “L” level is outputted from the AND gate 2008. Thus, when the timing generation enable signal 2015 is of the “H” level, the “H” level appears at the output of the second RS latch 2011, so that a rise step waveform is outputted from the second RS latch 2011. The step waveform appears at the terminal 2004 and is used as a comparative pulse follow-up request signal 320. At this time, the comparison pulse follow-up request signal 320 is inputted even to the pulse generator 2009 from which a pulse signal 2016 having a pulse width determined according to a delay time developed in a delay circuit 2010 provided within the pulse generator 2009 is generated. The pulse signal 2016 is fed back so as to be inputted to a reset terminal R of the first RS latch 2006, thereby bringing a timing generation enable signal to an “L” level on the fall timing of the next clock. Incidentally, the timing signal having the step waveform, which is outputted from the second RS latch 2011, passes through the delay circuit 2012, followed by inputting to the m-stage D flip-flops 2013 and 2014. Since clock input terminals of these D flip-flops 2013 and 2014 are supplied with the external clock signal, the timing signal having the step waveform appears at the terminal 2005 after the elapse of m clock cycles from the rise timing of the clock outputted from the divide-by-eight frequency circuit 303. This results in the first phase comparing timing signal 313.
Incidentally, the delay of the delay circuit 2012 is taken to prevent a hazard from occurring in the output of the D flip-flop 2013 when a signal change timing at the input unit of the D flip-flop 2013 and the rise timing of the clock signal approach each other. This aims to separate the signal change timing at the input unit of the D flip-flop 2013 from the rise timing of the clock signal.
Thus, the circuit shown in
One example of the timing signal generator 306 is shown in FIG. 35. The timing signal generator 306 receives a comparison pulse attainment prediction signal 321 outputted from the variable delay circuit 302 and thereafter generates a second phase comparing timing signal having a positive step waveform, which is synchronized with the first or initial rising edge of the output of the variable delay circuit 302.
The timing signal generator 306 comprises a comparison pulse attainment prediction signal input terminal 2101 for inputting or receiving the comparison pulse attainment prediction signal 321, a clock input terminal 2102 for inputting or receiving a clock outputted from the variable delay circuit 302, a reset signal input terminal 2103 for inputting or receiving a reset signal, a phase comparing timing signal output terminal 2104 for outputting a second phase comparing timing signal, an AND gate 2106, and a RS latch 2105.
The operation of the timing signal generator 306 will be explained. Prior to its operation, a reset signal having a positive pulse waveform is first inputted to the terminal 2103 for receiving the reset signal. Thus, the output of the RS latch 2105 is initialized so as to take an “L” level. A timing signal request signal 319 is used as the reset signal. Next, a comparison pulse attainment prediction signal 321 is inputted to the comparison pulse attainment prediction signal input terminal 2101 from the follow-up circuit 2218. Thereafter, when the initial rising edge of a signal outputted from the variable delay circuit 302 appears at the terminal 2102, the RS latch 2105 is set so as to output an “H” level, whereby a second phase comparing timing signal 316 is outputted from the phase comparing timing signal output terminal 2104. This state is held until the next reset signal, i.e., timing signal request signal 319 is given.
When no comparison pulse attainment prediction signal 321 is inputted, the output signal of the variable delay circuit 302 cannot pass through the AND gate 2106, and hence the RS latch 2105 is not set, thereby continuing to output an “L” level.
Thus, the timing signal generator 306 shown in
One examples of the variable delay circuit 302 and the comparison pulse follow-up circuit 2218 are shown in FIG. 36.
The variable delay circuit 302 outputs an input signal with a delay of a predetermined time according to a delay control signal 323. The comparison pulse follow-up circuit 2218 outputs a comparison pulse attainment prediction signal 321 for notifying the attainment of a clock pulse to the timing signal generator 306 in advance upon outputting the clock pulse corresponding to timing used for phase comparison. Incidentally, the interval between timing provided to output the comparison pulse attainment prediction signal 321 and timing provided to output the clock pulse, which is associated with the timing used for phase comparison, will be set within one clock cycle time.
In
Incidentally, the variable delay circuit 302 is the same as the variable delay circuit 103 shown in
The comparison pulse follow-up circuit 2218 is a circuit for outputting the comparison pulse attainment prediction signal 321 for notifying the attainment of the clock pulse to the timing signal generator 306 beforehand upon outputting the clock pulse corresponding to the phase comparing timing. The comparison pulse follow-up circuit 2218 comprises four AND gates 2219 through 2222 and four RS latches 2223 through 2226.
Prior to the operation of the comparison pulse follow-up circuit 2218, a comparator reset signal having a positive pulse waveform is first inputted to the comparison pulse follow-up circuit reset signal input terminal 2204. This aims to reset the four RS latches 2223 through 2226 in the comparison pulse follow-up circuit 2218. A timing signal request signal 319 may be used for the comparator reset signal. When the timing signal request signal 319 is inputted, a first input signal for the AND gate 2219, which is supplied from the terminal 2203, is next brought to an “H” level. Next, a clock pulse corresponding to timing used for phase comparison is inputted to the first clock signal input terminal 2202 of the variable delay circuit 302. This is supplied as for a second input signal for the AND gate 2219 as a positive pulse. In doing so, the positive pulse appears in an output signal of the AND gate 2219 so that the RS latch 2223 is brought to a set state, thereby outputting a signal of an “H” level. At this time, a first input signal of the AND gate 2220 is brought to an “H” level. Next, when the clock pulse corresponding to the timing used for phase comparison, which is inputted to the variable delay circuit 302, passes through the first delay circuit stage 2210 and the second delay circuit stage 2211, a positive pulse appears at a first output terminal of the second delay circuit stage 2211. This is applied even to a second input of the AND gate 2220. Thus, the positive pulse appear in an output signal of the AND gate 2220, so that the RS latch 2224 is set so as to output a signal of an “H” level. At this time, a first input signal of the AND gate 2221 is brought to the “H” level. When the clock pulse corresponding to the timing used for phase comparison, which is inputted to the variable delay circuit 302, passes through the third delay circuit stage 2212 through the sixth delay circuit stage 2215 continuously, the second RS latch 2224 through the fourth RS latch 2226 are respectively brought to a set state in the same manner as described above, so that a signal of an “H” level appears at the comparison pulse attainment prediction signal output terminal 2209, whereby a positive step signal, i.e., a comparison pulse attainment prediction signal 321 is outputted.
Thereafter, the clock pulse corresponding to the timing used for phase comparison passes through the seventh and eighth delay circuit stages 2216 and 2217, followed by being outputted from the variable delay circuit 302. That is, the interval between the comparison pulse attainment prediction signal 321 and the timing provided to output the clock pulse corresponding to the timing used for phase comparison is equivalent to a time interval reduced by delay times developed in the AND circuit 2222 and RS latch 2226 as counted from a delay time corresponding to the delay circuit stages equal to two stages. Since the delay circuit stage equivalent to one stage delays the rising edge or falling edge of the signal, a delay time greater than or equal to a half clock cycle cannot be created. Accordingly, a delay time greater than or equal to one clock cycle cannot be created in the case of the delay circuit stages equivalent to two stages. It can be thus said that the time interval reduced by the delay times developed in the AND circuit 2222 and RS latch 2226 as counted from the delay time corresponding to the delay circuit stages equal to the two stages, i.e., the interval between the comparison pulse attainment prediction signal 2209 outputted from the terminal 2209 and the timing provided to output the clock pulse corresponding to the timing used for phase comparison is shorter than one clock cycle time.
As is apparent from the above, the variable delay circuit 302 shown in
One example of the on-lock frequency-division switching circuit 310 is shown in FIG. 37. The on-lock frequency-division switching circuit 310 determines using a phase comparison signal 315 outputted from the phase comparator 308 whether the timing control circuit has locked in. If the timing control circuit is found not to be locked in, then the on-lock frequency-division switching circuit 310 outputs a signal of an “L” level. If it is determined that the timing control circuit has not been locked in, then the on-lock frequency-division switching circuit 310 outputs a signal of an “H” level
According to
The operation of the on-lock frequency-division switching circuit 310 will be explained. Prior to its operation, a positive pulse signal is first inputted to the reset signal input terminal 2303. This needs to initialize the outputs of the first through fourth flip-flops 2305 through 2308 and RS latch 2314 to an “L” level respectively and is carried out at power-on or upon DLL start-up. Next, a phase comparison signal corresponding to a first phase comparing timing signal 313 is inputted to the phase comparison signal input terminal 2301. Further, the first phase comparing timing signal 313 is inputted to the phase comparing timing signal input terminal 2302. If an internal clock leads an external clock in the phase comparator 308, then the phase comparison signal is given as an “H” level. If the internal clock lags the external clock, then the phase comparison signal is given as an “L” level. These signals are inputted to the first flip-flop 2305 and successively supplied to the second through fourth flip-flops 2306 through 2308 with the rise timing of the phase comparing timing signal 313.
Next, after the timing control circuit has been locked in, the level of the phase comparison signal is set such that “H” and “L” levels appear alternatively as in the case of “H”, “L”, “H”, “L”, . . . In doing so, patterns represented in the form of “H”, “L”, “H” and “L” appear at outputs 2310 through 2313 of the first through fourth flip-flops. The decoder circuit 2309 outputs an “H” level only when the outputs 2310 through 2313 of the first through fourth flip-flops are respectively brought to the patterns represented in the form of “H”, “L”, “H” and “L”. The decoder circuit 2309 outputs an “L” level except for the above. Thus, the decoder circuit 2309 outputs a pulse signal brought to an “H” level only when the outputs 2310 through 2313 of the first through fourth flip-flops are respectively given as the patterns represented in the form of “H”, “L”, “H” and “L”.
Next, the pulse signal is inputted to a set terminal S of the RS latch 2314. The RS latch 2314 is brought to a set state so that the output thereof is brought to an “H” level. Thus, the output state of the RS latch 2314 is maintained until it is reset.
Thus, the on-lock frequency-division switching circuit 310 is capable of making a decision as to lock-in of DLL, inverting the output from “L” to “H” levels after its lock-in and maintaining that level.
One example of the dummy delay circuit 301 is shown in FIG. 38. The dummy delay circuit 301 is a circuit for generating a delay time longer than that developed in the divide-by-eight frequency circuit 303. The dummy delay circuit 301 comprises delay signal input terminals 2401 and 2402 for differentially inputting or receiving signals to be delayed, a frequency-division switching signal input terminal 2403 for receiving or inputting a frequency-division switching signal, delay signal output terminals 2404 and 2405 for differentially-outputting the delayed signals, and two divide-by-eight frequency circuit-equivalent delay circuits 2406 each having a single-end type input/output.
As illustrated in
The selector 2410 may be the same circuit as the selector 106 shown in FIG. 33. Further, the two-stage type inverter 2411 is electrically connected between the selector 2410 and a delay signal output terminal 2409.
The operation of the dummy delay circuit 301 will next be described. When the frequency-division switching signal is “L”, the divide-by-eight frequency circuit 303 outputs the input signal through the selector 1906, but the circuit shown in each of
According to the configuration of the timing control circuit shown in
<<SDRAM>>
An SDRAM is shown in
An SDRAM1 has a memory array 10A which constitutes a bank A and a memory array 10B which constitutes a bank B. The respective memory arrays 10A and 10B are respectively provided with dynamic memory cells MC arranged in matrix form. According to the drawing, selection terminals of the memory cells MC arranged in the same column are electrically connected to their corresponding word lines WL provided every columns. Further, data input/output terminals of the memory cells arranged in the same row are electrically coupled to their corresponding complementary data lines BL and BLb every rows. While only parts of the word lines and complementary data lines are typically illustrated in the same drawing, they are arranged in large numbers in the form of a matrix.
One of the word lines WL of the memory array 10A, which has been selected according to the result of decoding of a row address signal by a row decoder 11A, is driven so as to take a selection level by a word driver 23A.
The complementary data lines of the memory array 10A are respectively coupled to a sense amplifier and column selection circuit 12A. A sense amplifier in the sense amplifier and column selection circuit 12A is an amplifier circuit for detecting a small voltage difference developed between the respective adjacent complementary data lines according to the reading of data from each memory cell MC. The column switch circuit therein is a switch circuit for separately selecting the complementary data lines and making continuity between the selected one and a complementary common data line 14. The column switch circuit is selectively activated according to the result of decoding of a column address signal by a column decoder 13A. A row decoder 11B, a word driver 23B, a sense amplifier and column selection circuit 12B, and a column decoder 13B are provided in the same manner as above even on the memory array 10B side. The complementary common data line 14 is electrically connected to an output terminal of a data input buffer 20 and an input terminal of a data output buffer 21. An input terminal of the data input buffer 20 and an output terminal of the data output buffer 21 are respectively electrically connected to data input/output terminals I/O0 through I/O15 represented in 16 bits.
Row and column address signals supplied from address input terminals A0 through A9 are respectively captured by a column address buffer 15 and a row address buffer 16 in address multiplex form. The supplied address signals are held by their corresponding buffers. The row address buffer 16 captures a refresh address signal outputted from a refresh counter 18 as row address signals in a refresh operation mode. The output of the column address buffer 15 is supplied as preset data for a column address counter 17. The column address counter 17 outputs the column address signals defined as the preset data or the values obtained by successively incrementing the column address signals to the column decoders 13A and 13B according to operation modes specified by commands or the like to be described later.
Although not restricted in particular, a controller 22 is supplied with external control signals such as a clock signal CLK, a clock enable signal CKE, a chip select signal CSb (whose suffix b means that a signal marked with it indicates a row enable signal or a level inversion signal), a column address strobe signal CASb, a row address strobe signal RASb and a write enable signal Web, etc., and control data inputted from the address input terminals A0 through A9 to thereby form internal timing signals for controlling operation modes of the SDRAM and the operations of the above-described circuit blocks, based on the levels of these signals, timings for changes in the signals, etc. Thus, the controller is provided with control logic used therefor.
The clock signal CLK is defined as a master clock for the SDRAM, and other external input signals are rendered significant in synchronism with the rising edge of the clock signal.
The chip select signal CSb provides instructions for the commencement of a command input cycle according to its low level. When the chip select signal is high in level (held in a chip non-selected state), other inputs do not make sense. However, the state of selection of each memory bank to be described later, and internal operations such as a burst operation, etc. are not affected by a change to the chip non-selected state.
The respective signals such as RASb, CASb and WEb are different in function from the corresponding signals employed in the normal DRAM and are defined as signals significant when command cycles to be described later are defined.
The clock enable signal CKE is a signal for specifying the validity of the next clock signal. When the signal CKE is high in level, the rising edge of the next clock signal CLK is rendered effective or valid. On the other hand, when the signal CKE is low in level, the rising edge thereof is made invalid. When a power-down mode (corresponding even to a data retention mode in the SDRAM) is selected, the clock enable signal CKE is brought to a low level.
Further, although not shown in the drawing, the external control signal for effecting output enable control on the data output buffer 21 in a read mode is also supplied to the controller 22. When the signal is high in level, for example, the data output buffer 21 is brought to a high output impedance state.
The row address signals are defined according to the levels of A0 through A8 in a row address strobe/bank active command cycle to be described later synchronized with the rising edge of the clock signal CLK.
The input supplied from A9 is regarded as a bank select signal in the row address strobe/bank active command cycle. That is, when the input supplied from A9 is low in level, the memory bank A is selected. When the input is high in level, the memory bank B is selected. Although the selection and control of each memory bank are not restricted in particular, they can be carried out by processes such as the activation of the row decoder alone on the selection memory bank side, the entire non-selection of the column switch circuits on the non-selection memory bank side, the connection to the data input buffer 20 and data output buffer 21 on the selection memory bank side alone, etc.
The column address signals are defined according to the levels of A0 through A7 in a read or write command (corresponding to a column address/read command or column address/write command to be described later) synchronized with the rising edge of the clock signal CLK. Each column address defined in this way is defined as a start address for a burst access.
The operation modes of the SDRAM, which are specified according to the commands, may include a mode register set command, a row address strobe/bank active command, a column address/read command, etc.
The mode register set command is a command for setting the mode register 220. The command is specified according to CSb, RASb, CASb and WEb=low level. Data (register set data) to be set are supplied through A0 through A9. Although not restricted in particular, the register set data may include a burst length, CAS latency, a write mode, etc. Although not restricted in particular, 1, 2, 4, 8 and a full page (256) may be mentioned as a settable burst length. Settable CAS latency may include 1, 2 and 3. Further, burst write and signal write may be mentioned as a settable write mode.
The CAS latency is used to specify what cycles of the clock signal CLK should be spent from the falling edge of CASb to the output operation of the data output buffer 21 upon a read operation specified by a column address/read command to be described later. An internal operation time required to perform data reading is required till the determination of data to be read. The CAS latency is used to set the internal operation time according to the used frequency of the clock signal CLK. In other words, when a clock signal CLK high in frequency is used, the CAS latency is set to a relatively large value, whereas when a clock signal CLK low in frequency is used, the CAS latency is set to a relatively small value.
The row address strobe/bank active command is a command for validating the designation of row address strobe and the selection of the corresponding memory bank by A9. This is specified according to CSb and RASb=low level and CASb and WEb=high level. At this time, addresses supplied to A0 through A8 are captured as row address signals, and a signal supplied to A9 is captured as a signal for selecting each memory bank. The operation of capturing such each signal is performed in synchronism with the rising edge of the clock signal CLK as described above. When the corresponding command is specified, for example, a word line for the corresponding memory bank specified by the command is selected and each individual memory cells connected to the corresponding word line are caused to conduct over their corresponding complementary data lines.
The column address/read command is a command required to start a burst read operation. Further, this command is a command for providing instructions for column address strobe. The present command is specified according to CSb and CASb=low level and RASb and WEb=high level. At this time, addresses supplied to A0 through A7 are captured as column address signals. Thus, each captured column address signal is supplied to the column address counter 17 as a burst start address. Upon the burst read operation specified by it, the selection of the corresponding memory bank and its corresponding word line is performed in a row address strobe/bank active command cycle prior to the burst read operation. Memory cells connected to the corresponding word line are successively selected and continuously read according to address signals outputted from the column address counter 17 in synchronism with the clock signal CLK. The number of continuously-read data is set to the number specified by the above burst length. The commencement of reading of data from the output buffer 21 is done while awaiting the number of cycles of the clock signal CLK, which is specified by the CAS latency.
Here, the input clock buffer 402 and timing control circuit 501 like DLL described in
While the invention achieved above by the present inventors has been described specifically by the embodiments, the present invention is not necessarily limited to them. It is needless to say that various changes can be made thereto within the scope not departing from the substance thereof.
For example, the number of frequency divisions by a frequency-dividing circuit is not limited to 8. Four or sixteen or the like may be used as the number thereof. Further, the present invention is not limited to the SDRAM and can be widely applied to clock synchronous semiconductor devices such as an SSRAM, a memory mixed-type system LSI, etc.
Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be described in brief as follows:
It is not necessary to provide two variable delay circuits as in the prior art. At least one frequency divider is provided midway between a variable delay circuit and a dummy delay circuit. Further, the dummy delay circuit is activated by a frequency-divided clock without increasing the variable delay circuit in number. Therefore, a timing control circuit small in area and low in power can be provided.
Further, since intervals for timing used for phase comparison and timing provided to control a delay time of a variable delay circuit are short as compared with the conventional DLL type timing control circuit, it is possible to implement the shortening of a lock-in time and an improvement in follow-up performance of an internal clock.
Furthermore, since a timing control circuit according to the present invention is short in lock-in time, a synchronous LSI short in recovery time as counted from its standby state can be provided if the timing control circuit is applied thereto.
Okuda, Yuichi, Nakagome, Yoshinobu, Nishio, Yoji, Funaba, Seiji
Patent | Priority | Assignee | Title |
7619454, | Dec 28 2005 | Hynix Semiconductor Inc. | Clock generator for semiconductor memory apparatus |
7701272, | May 31 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for output data synchronization with system clock |
8026749, | Nov 19 2008 | Samsung Electronics Co., Ltd.; SAMSUNG ELECTRONICS CO , LTD | Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit |
8115528, | May 31 2007 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Method and apparatus for output data synchronization with system clock |
8947966, | Jun 11 2012 | AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LIMITED | Power gated memory device with power state indication |
Patent | Priority | Assignee | Title |
5430394, | Mar 11 1994 | Advanced Micro Devices, Inc.; Advanced Micro Devices, INC | Configuration and method for testing a delay chain within a microprocessor clock generator |
5939913, | Sep 09 1997 | SOCIONEXT INC | DLL circuit and semiconductor memory device using same |
5987619, | May 07 1997 | Mitsubishi Denki Kabushiki Kaisha | Input signal phase compensation circuit capable of reliably obtaining external data |
5990714, | Dec 26 1996 | United Microelectronics Corporation | Clock signal generating circuit using variable delay circuit |
6128248, | Nov 11 1996 | LONGITUDE SEMICONDUCTOR S A R L | Semiconductor memory device including a clocking circuit for controlling the read circuit operation |
6134182, | Oct 19 1999 | International Business Machines Corporation | Cycle independent data to echo clock tracking circuit |
6269051, | Jun 18 1999 | Elpida Memory, Inc | Semiconductor device and timing control circuit |
6333875, | Nov 01 1999 | SOCIONEXT INC | Semiconductor circuit with adjustment of double data rate data latch timings |
6351166, | Jan 27 1998 | SOCIONEXT INC | Semiconductor device with stable and appropriate data output timing |
6366507, | Sep 30 1999 | VACHELLIA, LLC | High speed semiconductor memory device with short word line switching time |
6525585, | Nov 21 2000 | Renesas Electronics Corporation | Fixed-length delay generation circuit |
JP10112182, | |||
JP10283060, | |||
JP11127062, | |||
JP11127063, |
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