A spread spectrum radio transceiver includes a high data rate baseband processor and a radio circuit connected thereto. The baseband processor preferably includes a modulator for spread spectrum phase shift keying (psk) modulating information for transmission via the radio circuit. The modulator may include at least one modified walsh code function encoder for encoding information according to a modified walsh code for substantially reducing an average dc signal component to thereby enhance overall system performance when AC-coupling the received signal through at least one analog-to-digital converter to the demodulator. The demodulator is for spread spectrum psk demodulating information received from the radio circuit. The modulator and demodulator are each preferably operable in one of a bi-phase psk (BPSK) mode at a first data rate and a quadrature psk (QPSK) mode at a second data rate. These formats may also be switched on-the-fly in the demodulator. Method aspects are also disclosed.
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0. 97. A modulator for a spread spectrum radio transceiver, said modulator configured to modulate information for transmission by spread spectrum phase shift keying (psk), said modulator comprising at least one orthogonal code function encoder for encoding information according to an orthogonal code, wherein the orthogonal code is modified to have a reduced dc component for reducing an average dc signal component of the information encoded by the orthogonal code relative to that information being encoded by the orthogonal code in its unmodified state.
0. 105. A demodulator for a spread spectrum radio transceiver, said demodulator configured to demodulate information by spread spectrum phase shift keying (psk) demodulating information received from a radio circuit, said demodulator comprising at least one orthogonal code function correlator for decoding information according to an orthogonal code, wherein the orthogonal code is modified to have a reduced dc component for reducing an average dc signal component of the information decoded by the orthogonal code relative to that information being decoded by the orthogonal code in its unmodified state.
0. 116. A method for spread spectrum radio communication, the method comprising:
spread spectrum phase shift keying (psk) modulating information for transmission while encoding the information according to an orthogonal code, wherein the orthogonal code is modified to have a reduced dc component for reducing an average dc signal component of the information encoded by the orthogonal code relative to that information being encoded by the orthogonal code in its unmodified state; and
spread spectrum psk demodulating received information by decoding the received information according to the orthogonal code.
36. A modulator for a spread spectrum radio transceiver, said modulator comprising:
modulator means for spread spectrum phase shift keying (psk) modulating information for transmission, said modulator means comprising at least one predetermined orthogonal code function encoder for encoding information according to a predetermined orthogonal code, wherein the predetermined orthogonal code is modified to have a reduced dc component for reducing an average dc signal component of the information encoded by the predetermined orthogonal code relative to that information being encoded by the predetermined orthogonal code in its unmodified state.
44. A demodulator for a spread spectrum radio transceiver, said demodulator comprising:
demodulator means for spread spectrum phase shift keying (psk) demodulating information received from said a radio circuit, said demodulator means comprising at least one predetermined orthogonal code function correlator for decoding information according to a predetermined orthogonal code, wherein the predetermined orthogonal code is modified to have a reduced dc signal component for reducing an average dc signal component of the information decoded by the predetermined orthogonal code relative to that information being decoded by the predetermined orthogonal code in its unmodified state.
55. A method for baseband processor for spread spectrum radio communication, the method comprising the steps of:
spread spectrum phase shift keying (psk) modulating information for transmission while encoding the information according to a predetermined orthogonal code, wherein the predetermined orthogonal code is modified to have a reduced dc component for reducing an average dc signal component of the information encoded by the predetermined orthogonal code relative to that information being encoded by the predetermined orthogonal code in its unmodified state; and
spread spectrum psk demodulating received information by decoding the received information according to the predetermined orthogonal code.
0. 132. A method of encoding binary data for transmission in packet format along with information encoded at a predetermined spread spectrum chip rate, said method comprising the steps of:
grouping said binary data into N-bit symbols;
applying a K-bit segment of each N-bit symbol to a chip sequence generator to select one of 2K chip sequences, wherein each chip sequence is M chips in length and is a composite of an M-bit basic sequence and an M-bit modification sequence and chosen from a set that is substantially orthogonal with low dc components;
rotating the phase of the selected chip sequence in accordance with an N-K bit segment of the same N-bit symbol that selected said chip sequence; and
transmitting each phase-rotated, selected chip sequence at said predetermined chip rate.
0. 133. A method of encoding binary data for transmission in packet format along with information encoded at a predetermined spread spectrum chip rate, said method comprising the steps of:
grouping said binary data into N-bit symbols;
applying a K-bit segment of each N-bit symbol to a chip sequence generator to select one of 2K chip sequences chosen from a set that is substantially orthogonal with low dc components, wherein each chip sequence is M chips in length;
combining the selected basic chip sequence with a fixed, M-chip modification sequence to produce a selected M-chip composite chip sequence;
rotating the phase of the selected M-chip composite chip sequence in accordance with an N-K bit segment of the same N-bit symbol that selected said basic chip sequence; and
transmitting each phase rotated, selected composite chip sequence at said predetermined chip rate.
0. 123. A method of generating an rf signal for transmitting binary information in a packet format including a header field followed by a data field, comprising the steps of:
spread spectrum encoding a sequence of first data symbols from said binary information within said header field by combining said first data symbols with a spreading sequence generated at a predetermined chip rate;
encoding a sequence of N-bit second data symbols, where N is greater than 1, from said binary information within said data field by generating for each of said N-bit second data symbols one of a set of 2N chip sequences generated at the same chip rate as said spreading sequence and chosen from a set that is substantially orthogonal with low dc components; and
applying the spread-spectrum encoded symbols of said header field and selected chip sequences of said data field to the I and Q inputs of a phase shift modulator to produce said rf signal.
0. 127. A method of generating an rf signal in a transmitter having a phase shift modulator with I and Q inputs comprising the steps of:
supplying a stream of binary information containing header data and payload data, said header data specifying at least a first payload data rate or a second payload data rate;
encoding said payload data when said header data specifies said first payload data rate by grouping said payload data into N-bit symbols, where N is greater than 1, and applying each N-bit symbol to select one of 2N possible chip sequences and chosen from a set that is substantially orthogonal with low dc components;
encoding said payload data when said header data specifies said second payload data rate by grouping said payload data into 2N-bit symbols and applying each 2N-bit symbol to select one of 22N possible chip sequences; and
applying each selected chip sequence to the I and Q inputs of said phase shift modulator.
0. 78. A baseband processor for a spread spectrum radio transceiver, said baseband processor comprising:
a demodulator for spread spectrum phase shift keying (psk) demodulating;
at least one analog-to-digital (A/D) converter having an output coupled to said demodulator and an input AC-coupled to receive information;
said demodulator comprising at least one orthogonal code function correlator for decoding information according to an orthogonal code, wherein the orthogonal code is modified to have a reduced dc component for reducing an average dc signal component of the information decoded by the orthogonal code relative to that information being decoded by the orthogonal code in its unmodified state to thereby promote AC-coupling to said at least one A/D converter; and
a modulator for spread spectrum psk modulating information for transmission, said modulator comprising at least one orthogonal code function encoder for encoding information according to the orthogonal code.
0. 62. A spread spectrum radio transceiver comprising:
a baseband processor and a radio circuit coupled thereto, said baseband processor comprising a demodulator for spread spectrum phase shift keying (psk) demodulating information received from said radio circuit, at least one analog-to-digital (A/D) converter having an output coupled to said demodulator and an input AC-coupled to said radio circuit, said demodulator comprising at least one modified walsh code function correlator for decoding information according to a modified walsh code having a reduced dc component relative to an unmodified walsh code for reducing an average dc signal component of the information decoded by the modified walsh code relative to that information being decoded by the walsh code in its unmodified state, and a modulator for spread spectrum psk modulating information for transmission via the radio circuit, said modulator comprising at least one modified walsh code function encoder for encoding information according to the modified walsh code.
0. 125. A method of generating an rf signal for transmitting binary information in a packet format including a header field followed by a data field, comprising the steps of:
spread spectrum encoding a sequence of first data symbols from said binary information within said header field by combining said first data symbols with a spreading sequence;
encoding a sequence of N-bit second data symbols, where N is greater than 1, from said binary information within said data field by generating for each of said N-bit second data symbols one of a set of 2N chip sequences chosen from a set that is substantially orthogonal with low dc components, each of said chip sequences being differentially phase encoded;
applying a reference phase based on encoding of the last of said first data symbols to the differential encoding of the first selected chip sequence; and
inputting said encoded symbols of said header field and said differentially encoded chip sequences of said data field to the I and Q inputs of a phase shift modulator to produce said rf signal.
17. A baseband processor for a spread spectrum radio transceiver, said baseband processor comprising:
a demodulator for spread spectrum phase shift keying (psk) demodulating;
at least one analog-to-digital (A/D) converter having an output connected to said demodulator and an input AC-coupled to receive information;
said demodulator comprising at least one predetermined orthogonal code function correlator for decoding information according to a predetermined orthogonal code, wherein the predetermined orthogonal code is modified to have a reduced dc component for reducing an average dc signal component to thereby increase of the information decoded by the predetermined orthogonal code relative to that information being decoded by the predetermined orthogonal code in its unmodified state to thereby promote AC-coupling to said at least one A/D converter; and
a modulator for spread spectrum psk modulating information for transmission, said modulator comprising at least one predetermined orthogonal code function encoder for encoding information according to the predetermined orthogonal code.
1. A spread spectrum radio transceiver comprising:
a baseband processor and a radio circuit connected thereto, said baseband processor comprising
a demodulator for spread spectrum phase shift keying (psk) demodulating information received from said radio circuit,
at least one analog-to-digital (A/D) converter having an output connected to said demodulator and an input AC-coupled to said radio circuit,
said demodulator comprising at least one modified walsh code function correlator for decoding information according to a modified walsh code having a reduced dc component for reducing an average dc signal component which of the information decoded by the modified walsh code relative to that information being decoded by an unmodified walsh code which, in combination with the AC-coupling to said at least one A/D converter enhances overall performance, and
a modulator for spread spectrum psk modulating information for transmission via the radio circuit, said modulator comprising at least one modified walsh code function encoder for encoding information according to the modified walsh code.
30. A baseband processor for a spread spectrum radio transceiver, said baseband processor comprising:
a modulator for spread spectrum phase shift keying (psk) modulating information for transmission, said modulator comprising
at least one encoder for encoding information for transmission,
means for operating in one of a first format defined by bi-phase psk (BPSK) modulation at a first data rate and a second format defined by quadrature psk (QPSK) modulation at a second data rate,
header modulator means for modulating data packets to include a header at a third format defined by a predetermined modulation at a third data rate and variable data in one of the first and second formats; and
a demodulator for spread spectrum psk demodulating received information, said demodulator comprising
at least one correlator for decoding received information,
means for operating in one of the first and second formats,
header demodulator means for demodulating data packets by demodulating the header at the third format and for switching to the respective one of the first and second formats of the variable data after the header,
a first carrier tracking loop for the third format, and
a second carrier tracking loop for the first and second formats.
0. 91. A baseband processor for a spread spectrum radio transceiver, said baseband processor comprising:
a modulator for spread spectrum phase shift keying (psk) modulating information for transmission, said modulator comprising
at least one encoder for encoding information for transmission,
wherein said modulator is configured to operate in one of a first format defined by bi-phase psk (BPSK) modulation at a first data rate and a second format defined by quadrature psk (QPSK) modulation at a second data rate, and
wherein said modulator is configured to modulate data packets to include a header at a third format defined by a modulation at a third data rate and variable data in one of the first and second formats; and
a demodulator for spread spectrum psk demodulating received information, said demodulator comprising at least one correlator for decoding received information, wherein said demodulator is configured to operate in one of the first and second formats, wherein said demodulator is configured to demodulate data packets by demodulating the header at the third format and for switching to the respective one of the first and second formats of the variable data after the header, a first carrier tracking loop for the third format, and a second carrier tracking loop for the first and second formats.
2. A spread spectrum radio transceiver according to
3. A spread spectrum radio transceiver according to
4. A spread spectrum radio transceiver according to
5. A spread spectrum radio transceiver according to
a first carrier tracking loop for the third format; and
a second carrier tracking loop for the first and second formats.
6. A spread spectrum radio transceiver according to
a carrier numerically controlled oscillator (NCO); and
carrier NCO control means for selectively operating said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
7. A spread spectrum radio transceiver according to
a carrier loop filter; and
carrier loop filter control means for selectively operating said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
8. A spread spectrum radio transceiver according to
9. A spread spectrum radio transceiver according to
10. A spread spectrum radio transceiver according to
a modified walsh function generator; and
a plurality of parallel connected correlators connected to said modified walsh function generator.
11. A spread spectrum radio transceiver according to
12. A spread spectrum radio transceiver according to
13. A spread spectrum radio transceiver according to
14. A spread spectrum radio transceiver according to
a quadrature intermediate frequency modulator/demodulator connected to said baseband processor; and
an up/down frequency converter connected to said quadrature intermediate frequency modulator/demodulator.
15. A spread spectrum radio transceiver according to
a low noise amplifier having an output connected to an input of said up/down converter; and
a radio frequency power amplifier having an input connected to an output of said up/down converter.
16. A spread spectrum radio transceiver according to
an antenna; and
an antenna switch for switching said antenna between the output of said radio frequency power amplifier and the input of said low noise amplifier.
18. A baseband processor according to
19. A baseband processor according to
20. A baseband processor according to
21. A baseband processor according to
a first carrier tracking loop for the third format; and
a second carrier tracking loop for the first and second formats.
22. A baseband processor according to
a carrier numerically controlled oscillator (NCO); and
carrier NCO control means for selectively operating said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
23. A baseband processor according to
a carrier loop filter; and
carrier loop filter control means for selectively operating said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
24. A baseband processor according to
25. A baseband processor according to
26. A baseband processor according to
27. A baseband processor according to
a predetermined orthogonal code function generator; and
a plurality of parallel connected correlators connected to said predetermined orthogonal code function generator.
28. A baseband processor according to
29. A baseband processor according to
31. A baseband processor according to
32. A baseband processor according to
a carrier numerically controlled oscillator (NCO); and
carrier NCO control means for selectively operating said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
33. A baseband processor according to
a carrier loop filter; and
carrier loop filter control means for selectively operating said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
34. A baseband processor according to
35. A baseband processor according to
37. A modulator according to
38. A modulator according to
39. A modulator according to
40. A modulator according to
41. A modulator according to
a predetermined orthogonal code function generator; and
a plurality of parallel connected correlators connected to said predetermined orthogonal code function generator.
42. A modulator according to
43. A modulator according to
45. A demodulator according to
46. A demodulator according to
47. A demodulator according to
48. A demodulator according to
a first carrier tracking loop for the third format; and
a second carrier tracking loop for the first and second formats.
49. A demodulator according to
a carrier numerically controlled oscillator (NCO); and
carrier NCO control means for selectively operating said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
50. A demodulator according to
a carrier loop filter; and
carrier loop filter control means for selectively operating said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
51. A demodulator according to
52. A demodulator according to
53. A demodulator according to
54. A demodulator according to
a predetermined orthogonal code function generator; and
a plurality of parallel connected correlators connected to said predetermined orthogonal code function generator.
56. A method according to
57. A method according to
58. A method according to
modulating data packets to include a header at a third format defined by a predetermined modulation at a third data rate and variable data in one of the first and second formats; and
demodulating data packets by demodulating the header at the third format and for switching to the respective one of the first and second formats of the variable data after the header.
59. A method according to
60. A method according to
61. A method according to
0. 63. A spread spectrum radio transceiver according to
0. 64. A spread spectrum radio transceiver according to
0. 65. A spread spectrum radio transceiver according to
0. 66. A spread spectrum radio transceiver according to
a first carrier tracking loop for the third format; and
a second carrier tracking loop for the first and second formats.
0. 67. A spread spectrum radio transceiver according to
a carrier numerically controlled oscillator (NCO); and
a controller to selectively operate said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 68. A spread spectrum radio transceiver according to
a carrier loop filter; and
a controller to selectively operate said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 69. A spread spectrum radio transceiver according to
0. 70. A spread spectrum radio transceiver according to
0. 71. A spread spectrum radio transceiver according to
a modified walsh function generator; and
a plurality of parallel coupled correlators coupled to said modified walsh function generator.
0. 72. A spread spectrum radio transceiver according to
0. 73. A spread spectrum radio transceiver according to
0. 74. A spread spectrum radio transceiver according to
0. 75. A spread spectrum radio transceiver according to
a quadrature intermediate frequency modulator/demodulator coupled to said baseband processor; and
an up/down frequency converter coupled to said quadrature intermediate frequency modulator/demodulator.
0. 76. A spread spectrum radio transceiver according to
a low noise amplifier having an output coupled to an input of said up/down converter; and
a radio frequency power amplifier having an input coupled to an output of said up/down converter.
0. 77. A spread spectrum radio transceiver according to
an antenna; and
an antenna switch for switching said antenna between the output of said radio frequency power amplifier and the input of said low noise amplifier.
0. 79. A baseband processor according to
0. 80. A baseband processor according to
0. 81. A baseband processor according to
0. 82. A baseband processor according to
a first carrier tracking loop for the third format; and
a second carrier tracking loop for the first and second formats.
0. 83. A baseband processor according to
a carrier numerically controlled oscillator (NCO); and
a controller to selectively operate said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 84. A baseband processor according to
a carrier loop filter; and
a controller to selectively operating said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 85. A baseband processor according to
0. 86. A baseband processor according to
0. 87. A baseband processor according to
0. 88. A baseband processor according to
a predetermined orthogonal code function generator; and
a plurality of parallel coupled correlators coupled to said orthogonal code function generator.
0. 89. A baseband processor according to
0. 90. A baseband processor according to
0. 92. A baseband processor according to
0. 93. A baseband processor according to
a carrier numerically controlled oscillator (NCO); and
a controller for selectively operating said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 94. A baseband processor according to
a carrier loop filter; and
a controller to selectively operate said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 95. A baseband processor according to
0. 96. A baseband processor according to
0. 98. A modulator according to
0. 99. A modulator according to
0. 100. A modulator according to
0. 101. A modulator according to
0. 102. A modulator according to
an orthogonal code function generator; and
a plurality of parallel coupled correlators coupled to said orthogonal code function generator.
0. 103. A modulator according to
0. 104. A modulator according to
0. 106. A demodulator according to
0. 107. A demodulator according to
0. 108. A demodulator according to
0. 109. A demodulator according to
a first carrier tracking loop for the third format; and
a second carrier tracking loop for the first and second formats.
0. 110. A demodulator according to
a carrier numerically controlled oscillator (NCO); and
a controller to selectively operate said carrier NCO based upon a carrier phase of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 111. A demodulator according to
a carrier loop filter; and
a controller to selectively operate said carrier loop filter based upon a frequency of said first carrier tracking loop to thereby facilitate switching to the format of the variable data.
0. 112. A demodulator according to
0. 113. A demodulator according to
0. 114. A demodulator according to
0. 115. A demodulator according to
an orthogonal code function generator; and
a plurality of parallel coupled correlators coupled to said orthogonal code function generator.
0. 117. A method according to
0. 118. A method according to
0. 119. A method according to
modulating data packets to include a header at a third format defined by a modulation at a third data rate and variable data in one of the first and second formats; and
demodulating data packets by demodulating the header at the third format and for switching to the respective one of the first and second formats of the variable data after the header.
0. 120. A method according to
0. 121. A method according to
0. 122. A method according to
0. 124. The method of
0. 126. The method of
0. 128. The method of
0. 129. The method of
0. 130. The method of
0. 131. The method of
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The invention relates to the field of communication electronics, and, more particularly, to a spread spectrum transceiver and associated methods.
Wireless or radio communication between separated electronic devices is widely used. For example, a wireless local area network (WLAN) is a flexible data communication system that may be an extension to, or an alternative for, a wired LAN within a building or campus. A WLAN uses radio technology to transmit and receive data over the air, thereby reducing or minimizing the need for wired connections. Accordingly, a WLAN combines data connectivity with user mobility, and, through simplified configurations, also permits a movable LAN.
Over the past several years, WLANs have gained acceptance among a number users including, for example, healthcare, retail, manufacturing, warehousing, and academic areas. These groups have benefited from the productivity gains of using hand-held terminals and notebook computers, for example, to transmit real-time information to centralized hosts for processing. Today WLANs are becoming more widely recognized and used as a general purpose connectivity alternative for an even broader range of users. In addition, a WLAN provides installation flexibility and permits a computer network to be used in situations where wireline technology is not practical.
In a typical WLAN, an access point provided by a transceiver, that is, a combination transmitter and receiver, connects to the wired network from a fixed location. Accordingly, the access transceiver receives, buffers, and transmits data between the WLAN and the wired network. A single access transceiver can support a small group of collocated users within a range of less than about one hundred to several hundred feet. The end users connect to the WLAN through transceivers which are typically implemented as PC cards in a notebook computer, or ISA or PCI cards for desktop computers. Of course the transceiver may be integrated with any device, such as a hand-held computer.
The assignee of the present invention has developed and manufactured a set of integrated circuits for a WLAN under the mark PRISM 1 which is compatible with the proposed IEEE 802.11 standard. The PRISM 1 chip set is further described in Harris Corporation Application Note entitled “Harris PRISM Chip Set”, No. AN9614, March 1996; and also in a publication entitled “PRISM 2.4 GHz Chip Set”, file no. 4063.4, October 1996.
The PRISM 1 chip set provides all the functions necessary for full or half duplex, direct sequence spread spectrum, packet communications at the 2.4 to 2.5 GHz ISM radio band. In particular, the HSP3824 baseband processor manufactured by Harris Corporation employs quadrature or bi-phase phase shift keying (QPSK or BPSK) modulation schemes. While the PRISM 1 chip set is operable at 2 Mbit/s for BPSK and 4 Mbit/s for QPSK, these data rates may not be sufficient for higher data rate applications.
Spread spectrum communications have been used for various applications, such as cellular telephone communications, to provide robustness to jamming, good interference and multi-path rejection, and inherently secure communications from eavesdroppers, as described, for example, in U.S. Pat. No. 5,515,396 to Dalekotzin. The patent discloses a code division multiple access (CDMA) cellular communication system using four Walsh spreading codes to allow transmission of a higher information rate without a substantial duplication of transmitter hardware. U.S. Pat. No. 5,535,239 to Padovani et al., U.S. Pat. No. 5,416,797 to Gilhousen et al., U.S. Pat. No. 5,309,474 to Gilhousen et al., and U.S. Pat. No. 5,103,459 to Gilhousen et al. also disclose a CDMA spread spectrum cellular telephone communications system using Walsh function spreading codes.
Unfortunately, the conventional Walsh function spreading codes may create undesirable signal components for some applications. Moreover, a WLAN application, for example, may require a change between BPSK and QPSK during operation, that is, on-the-fly. Spreading codes may be difficult to use in such an application where an on-the-fly change is required.
In view of the foregoing background, it is therefore an object of the present invention to provide a spread spectrum transceiver and associated method permitting operation at higher data rates than conventional transceivers.
It is another object of the invention to provide a spread spectrum transceiver and associated method to permit operation at higher data rates and which may switch on-the-fly between different data rates and/or formats.
These and other objects, features and advantages in accordance with the invention are provided by a spread spectrum radio transceiver comprising a high data rate baseband processor and a radio circuit connected thereto. The baseband processor preferably includes a modulator for spread spectrum phase shift keying (PSK) modulating information for transmission via the radio circuit, and wherein the modulator, in one embodiment, comprises at least one modified Walsh code function encoder for encoding information according to a modified Walsh code. The baseband processor also preferably further comprises a demodulator for spread spectrum PSK demodulating information received from the radio circuit. The demodulator is preferably connected to the output of at least one analog-to-digital (A/D) converter, which, in turn, is AC-coupled to the associated receive portions of the radio circuit. Accordingly, the demodulator preferably comprises at least one modified Walsh code function correlator for decoding information according to the modified Walsh code. The modified Walsh code substantially reduces an average DC component which in combination with the AC-coupling to the at least one A/D converter thereby increases overall system performance. Other orthogonal and bi-orthogonal coding schemes may also be used, wherein the average DC component is preferably substantially reduced or avoided.
The modulator preferably comprises means for operating in one of a bi-phase PSK (BPSK) modulation mode at a first data rate defining a first format, and a quadrature PSK (QPSK) mode at a second data rate defining a second format. In addition, the demodulator preferably comprises means for operating in one of the first and second formats. The modulator may also preferably include header modulator means for modulating data packets to include a header at a predetermined modulation and a third data rate defining a third format, and for modulating variable data at one of the first and second formats. Accordingly, the demodulator thus preferably includes header demodulator means for demodulating data packets by demodulating the header at the third format and for switching to either the first and second formats of the variable data after the header. The third format is preferably differential BPSK, and the third data rate is preferably lower than the first and second data rates.
The demodulator may preferably comprise first and second carrier tracking loops—the first carrier tracking loop for the third format, and the second carrier tracking loop for the first and second formats. The second carrier tracking loop, in turn, may comprise a carrier numerically controlled oscillator (NCO), and NCO control means for selectively operating the carrier NCO based upon a carrier phase of the first carrier tracking loop to thereby facilitate switching to the format of the variable data. The second carrier tracking loop may also comprise a carrier loop filter, and carrier loop filter control means for selectively operating the carrier loop filter based upon a frequency of the first carrier tracking loop to facilitate switching to the format of the variable data. The carrier tracking loops permit switching to the desired format after the header and on-the-fly.
The at least one modified Walsh code function correlator of the demodulator preferably comprises a modified Walsh function generator, and a plurality of parallel connected correlators connected to the modified Walsh function generator. The modified Walsh code may be a Walsh code modified by a modulo two addition of a fixed hexadecimal code thereto. In addition, the modulator in one embodiment preferably further comprises means for partitioning data into four bit nibbles of sign (one bit) and magnitude (three bits) to the modified Walsh code function encoder.
The modulator may also include spreading means for spreading each data bit using a pseudorandom (PN) sequence at a predetermined chip rate. Accordingly, the modulator may also comprise preamble modulating means for generating a preamble, and wherein the demodulator includes preamble demodulator means for demodulating the preamble for achieving initial PN sequence synchronization.
The modulator for the spread spectrum transceiver may include a scrambler, and the demodulator accordingly preferably includes a descrambler. The demodulator may also include clear channel assessing means for generating a clear channel assessment signal to facilitate communications only when the channel is clear.
The baseband processor is desirably coupled to a radio circuit for the complete spread spectrum transceiver. Accordingly, the transceiver preferably includes a quadrature intermediate frequency modulator/demodulator connected to the baseband processor, and an up/down frequency converter connected to the quadrature intermediate frequency modulator/demodulator. In addition, the radio circuit preferably further comprises a low noise amplifier having an output connected to an input of the up/down converter, and a radio frequency power amplifier having an input connected to an output of the up/down converter. The spread spectrum radio transceiver preferably also includes an antenna, and an antenna switch for switching the antenna between the output of the radio frequency power amplifier and the input of the low noise amplifier.
A method aspect of the invention is for baseband processing for spread spectrum radio communication. The method preferably comprises the steps of: spread spectrum phase shift keying (PSK) modulating information for transmission by encoding information according to a predetermined bi-orthogonal code for reducing an average DC signal component; and spread spectrum PSK demodulating received information by decoding information according to the predetermined bi-orthogonal code. The predetermined bi-orthogonal code is preferably a modified Walsh function code.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
Referring to
A low noise amplifier 38, as may be provided by Harris part number HFA3424, is also operatively connected to the antennas. The illustrated up/down converter 33 is connected to both the low noise amplifier 38 and the RF power amplifier and TX/RX switch 32 as would be readily understood by those skilled in the art. The up/down converter 33 may be provided by a Harris part number HFA3624, for example. The up/down converter 33, in turn, is connected to the illustrated dual frequency synthesizer 34 and the quad IF modulator/demodulator 35. The dual synthesizer 34 may be a Harris part number HFA3524 and the quad IF modulator 35 may be a Harris part number HFA3724. All the components described so far are included in a 2.4 GHz direct sequence spread spectrum wireless transceiver chip set manufactured by Harris Corporation under the designation PRISM 1. Various filters 36, and the illustrated voltage controlled oscillators 37 may also be provided as would be readily understood by those skilled in the art and as further described in the Harris PRISM 1 chip set literature, such as the application note No. AN9614, March 1996, the entire disclosure of which is incorporated herein by reference.
Turning now more particularly to the right hand side of
Like the HSP3824 baseband processor, the high data rate baseband processor 40 of the invention contains all of the functions necessary for a full or half duplex packet baseband transceiver. The processor 40 has on-board dual 3-bit A/D converters 41 for receiving the receive I and Q signals from the quad IF modulator 35. Also like the HSP3824, the high data rate processor 40 includes a receive signal strength indicator (RSSI) monitoring function with the on-board 6-bit A/D converter and CCA circuit block 44 provides a clear channel assessment (CCA) to avoid data collisions and optimize network throughput as would be readily understood by those skilled in the art.
The present invention provides an extension of the PRISM 1 product from 1 Mbit/s BPSK and 2 Mbit/s QPSK to 5.5 Mbit/s BPSK and 11 Mbit/s QPSK. This is accomplished by keeping the chip rate constant at 11 Mchip/s. This allows the same RF circuits to be used for higher data rates. The symbol rate of the high rate mode is 11 MHz/8=1.375 Msymbol/s.
For the 5.5 Mbit/s mode of the present invention, the bits are scrambled and then encoded from 4 bit nibbles to 8 chip modified Walsh functions. This mapping results in bi-orthogonal codes which have a better bit error rate (BER) performance than BPSK alone. The resulting 11 Mchip/s data stream is BPSK modulated. The demodulator comprises a modified Walsh correlator and associated chip tracking, carrier tracking, and reformatting devices as described in greater detail below.
For the 11 Mbit/s mode, the bits are scrambled and then encoded from 4 bit nibbles to 8 chip modified Walsh functions independently on each I and Q rail. There are 8 information bits per symbol mapped to 2 modified Walsh functions. This mapping results in bi-orthogonal codes which have better BER performance than QPSK alone. The resulting two 11 Mchip/s data streams are QPSK modulated.
The theoretical BER performance of this type of modulation is approximately 10−5 at an Eb/No of 8 dB versus 9.6 dB for plain BPSK or QPSK. This coding gain is due to the bi-orthogonal coding. There is bandwidth expansion for all of the modulations to help combat multi-path and reduce the effects of interference.
Referring additionally to
The Magnitude part of the SIPO output points to one of the Modified Walsh Sequences shown in the table below, along with the basic Walsh sequences for comparison.
MAG
BASIC WALSH
MODIFIED WALSH
0
00
03
1
0F
0C
2
33
30
3
3C
3F
4
55
56
5
5A
59
6
66
65
7
69
6A.
The Sel Walsh A,, and Sel Walsh B bits from the clock enable logic circuit 54 multiplex the selected Walsh sequence to the output, and wherein the LSBs are output first. The A Sign and B Sign bits bypass the respective Modified Walsh Generators 53a, 53b and are XOR'd to the sequence.
As would be readily understood by those skilled in the art, there are other possible mappings of bits to Walsh symbols that are contemplated by the present invention. In addition, the Modified Walsh code may be generated by modulo two adding a fixed hexadecimal code to the basic or standard Walsh codes to thereby reduce the average DC signal component and thereby enhance overall performance as will be explained in greater detail below.
The output of the Diff encoders of the last symbol of the header CRC is the reference for the high rate data. The header may always be BPSK. This reference is XOR'd to I and Q signals before the output. This allows the demodulator 60, as described in greater detail below, to compensate for phase ambiguity without Diff decoding the high rate data. Data flip flops 55a, 55b are connected to the multiplexer, although in other embodiments the flip flops may be positioned further downstream as would be readily understood by those skilled in the art. The output chip rate is 11 Mchip/s. For BPSK, the same chip sequence is output on each I and Q rail via the multiplexer 57. The output multiplexer 58 provides the selection of the appropriate data rate and format.
Referring now additionally to
0Ah
1
Mbit/s BPSK,
14h
2
Mbit/S QPSK,
37h
5.5
Mbit/s BPSK, and
6Eh
11
Mbit/s QPSK.
The SERVICE is OOh, the LENGTH is XXXXh wherein the length is in μs, and the CRC is XXXXh calculated based on SIGNAL, SERVICE and LENGTH. MPDU is variable with a number of octets (bytes).
The PLCP preamble and PLCP header are always at 1 Mbit/s, Diff encoded, scrambled and spread with an 11 chip barker. SYNC and SFD are internally generated. SIGNAL, SERVICE and LENGTH fields are provided by the interface 80 via a control port. SIGNAL is indicated by 2 control bits and then formatted as described. The interface 80 provides the LENGTH in μs. CRC in PLCP header is performed on SIGNAL, SERVICE and LENGTH fields.
MPDU is serially provided by Interface 80 and is the variable data scrambled for normal operation. The reference phase for the first symbol of the MPDU is the output phase of the last symbol of the header for Diff Encoding. The last symbol of the header into the scrambler 51 must be followed by the first bit of the MPDU. The variable data may be modulated and demodulated in different formats than the header portion to thereby increase the data rate, and while a switchover as indicated by the switchover point in
Turning now additionally to
Referring now to
The signal is phase and frequency tracked via the Complex Multiplier 64, Carrier NCO 61 and Carrier Loop Filter 62. The output of the Complex Multiplier 64 also feeds the Carrier Phase Error Detector 76. A decision directed Chip Phase Error Detector 72 feeds the illustrated Timing Loop Filter 75 which, in turn, is connected to the Clock Enable Logic 77. A decision from the Chip Phase Error Detector 72 is used instead of early-late correlations for chip tracking since the SNR is high. This greatly reduces the additional circuitry required for high rate operation. The 44 MHz master clock input to the Clock Control 74 will allow tracking high rate mode chips with ±⅛ chip steps. Only the stepper is required to run at 44 MHz, while most of the remaining circuits run at 11 MHz. The circuit is only required to operate with a long header and sync.
Turning now additionally to
With additional reference to
Referring now additionally to
The sign of the accumulator is used to advance or retard the chip timing by ⅛ chip. This circuit must be enabled by the PRISM 1 circuits at the proper time via the HI_START signal. The errors are summed and accumulated for 32 symbols (256 chips). The Chip Track Acc signal them dumps the accumulator for the next measurement. The chip phase error is generated if the End Sign bits bracketing the Mid sample are different. This is accomplished using the transition detectors. The sign of the chip phase error is determined by the sign of the End sample after the Mid sample. A multiplier 114 is shown for multiplying by +1 if the End Sign is 0 or by −1 if the End Sign is 1. If the End sign bits are identical, the chip phase error for that rail is 0. The AND function is only enabled by transitions.
Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.
Andren, Carl F., Snell, James Leroy, Lucas, Leonard Victor
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