A transmitting method of digital data whereby information data can be reproduced at a high precision. In order to retain digital data in sectors comprising a plurality of sync frames and sequentially transmit, the sync frame is comprised of the sync signal and the run length limited code which satisfies the limitations of the minimum run length and the maximum run length, and the sync signal includes the sync pattern constituted by a bit pattern of a run length that is longer than the maximum run length by only 3T and addition bit patterns which are arranged before and after the bit pattern and each of which has a urn length that is longer than the minimum run length. The sync signal includes a specific code which indicates a position in the sector and which enables the DC control to be performed.
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4. A transmitting method of digital data for retaining the digital data in sectors each comprising a plurality of sync frames and sequentially transmitting the data, wherein said sync frame comprises a sync signal and a run length limited code which corresponds to said digital data and satisfies limitations of a minimum run length and a maximum run length, and
said sync signal includes a specific code indicative of a position in said sector.
13. A transmitting method of digital data for retaining digital data in sectors each comprising a plurality of sync frames and sequentially transmitting, wherein
said sync frame comprises a sync signal of 32 bits and a run length limited code obtained by 8-16 modulating said digital data every eight bits so as to satisfy run length limitations of a minimum run length is 2 and a maximum run length is 10, and
said sync signal comprises: a connection bit of three bits arranged so as to satisfy the limitations of said minimum run length is 2 and said maximum run length is 10 in a connection with said run length limited code existing just before said sync signal; a specific code of seven bits which satisfies the limitations of said minimum run length =2 and said maximum run length =10 and which has 32 kinds of bit patterns; and sync patterns of run lengths of (4T or more-14T-4T).
0. 1. A transmitting method of digital data for retaining digital data in sectors each comprising a plurality of sync frames and sequentially transmitting the data, wherein
said sync frame comprises a sync signal and a run length limited code which corresponds to said digital data and satisfies limitations of a minimum run length and a maximum run length, and
said sync signal includes a sync pattern comprised of a bit pattern of a run length which is longer than said maximum run length by 3T and addition bit patterns which are arranged before and after said pattern and each of which has a run length that is longer than said minimum run length.
0. 2. A method according to
0. 3. A method according to
said run length limited code is a code obtained by 8-16 modulating said digital data every eight bits so as to satisfy run length limitations of the minimum run length is 2 and the maximum run length is 10, and
said sync pattern is comprised of bit patterns of run lengths of (4T or more -14T-4T).
5. A method according to
said sector comprises s plurality of lines each of which is constituted by said two sync frames, and
a position in said sector is identified by said specific code included in each of said two sync signals included every said line.
6. A method according to
7. A method according to
8. A method according to claim 3 4, wherein a DC control can be performed by the bit patterns of said specific code.
9. A method according to
10. A method according to
said sector comprises 13 lines each of which is constituted by said two sync frames, and
said sync signal has 32 kinds of bit patterns in order to satisfy the limitations of said minimum run length and said maximum run length, specify the head of said sector and each line, and perform said DC control in a connection with said run length limited code existing just before said sync signal.
11. A method according to
said sector comprises 13 lines each of which is constituted by said two sync frames, and
said sync signal has 32 kinds of bit patterns in order to satisfy the limitations of said minimum run length and said maximum run length, specify the head of said sector and each line, and perform said DC control in a connection with said run length limited code existing just before said sync signal.
12. A method according to
said sector comprises 13 lines each of which is constituted by said two sync frames, and
said sync signal has 32 kinds of bit patterns in order to satisfy the limitations of said minimum run length and said maximum run length, specify the head of said sector and each line, and perform said DC control in a connection with said run length limited code existing just before said sync signal.
14. A method according to
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This application is a reissue of application Ser. No. 08/759,956, filed on Dec. 3, 1996, now U.S. Pat. No. 5,987,066, which claims priority under 35 U.S.C. § 119 from Japanese Patent Application JP 7-316420 filed Dec. 5, 1995. More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,987,066. The reissue applications are application Ser. No. 10/785,864(the present application) and continuation application Ser. Nos. 11/638,659, 11/638,660 and 11/638,661.
1. Field of the Invention
The invention relates to a method of transmitting digital data in which digital data is retained in sectors each comprising a plurality of sync frames and sequentially transmitting it (including recording of the digital data).
2. Description of Background Information
As an RLL (Run Length Limited) encoding method which is performed in order to transmit digital data indicative of information or record the digital data to a recording medium, an EFM (Eight to Fourteen Modulation) which is used for a CD (compact disc) or the like is known.
In the EFM, digital data of eight bits (one byte) is converted to a run length limed code of 14 bits which satisfies run length limitations of:
In the CD, a signal obtained by adding a sync signal to the EFM modulation signal has been recorded. The sequence by the EFM modulation signals is constructed in a manner such that a repetitive pattern of maximum interval which corresponds to the maximum run length k, namely, repetitive pattern such as 11T-11T doesn't exist in the sequence and the repetitive pattern of 11T is used as a sync signal.
In a CD player, the sync signal is extracted by detecting the repetitive pattern of 11T from a signal read out from the CD.
In a DVD (digital video disc) in which recording information has been recorded at a high density or a high-density data transmission, however, when reading the information, it is largely influenced by an inter-symbol interference. The repetitive pattern of 11T as a sync signal is, therefore, changed to a pattern such as 11T-10T or 10T-11 and is read out. On the contrary, a case where the data pattern such as 10T-11T or 11T-10T as an EFM modulation signal is changed to the repetitive pattern of 11T and is erroneously detected as a sync signal occurs.
As mentioned above, in the high-density recording or high-density data transmission, a frequency of errors which occur in the detection of the sync signal increases and a burst error due to out-of-synchronism easily occurs.
The invention is made to solve the problems mentioned above and it is an object of the invention to provide a transmitting method of digital data whereby the digital data can be reproduced at a high precision even at the time of a high-density recording or a high-density data transmission.
According to the invention, there is provided a transmitting method of digital data for retaining digital data in sectors each comprising a plurality of sync frames and sequentially transmitting, wherein the sync frame comprises a sync signal and a run length limited code which corresponds to the digital data and satisfies limitations of a minimum run length and a maximum run length, and the sync signal includes a sync pattern comprising a bit pattern having a run length which is longer than the maximum run length by 3T and addition bit patterns which are arranged before and after the bit pattern and each of which has a run length that is longer than the minimum run length.
According to the invention, there is also provided a transmitting method of digital data for storing the digital data into sectors each comprising a plurality of sync frames and sequentially transmitting, wherein the sync frame comprises a sync signal and a run length limited code which corresponds to the digital data and satisfies limitations regarding a minimum run length and a maximum run length, and the sync signal includes a specific code which indicates a position in the sector and which enables a DC control to be performed.
In order to retain the digital data into the sectors each comprising a plurality of sync frames and sequentially transmit, the sync frame is comprised of the sync signal and the run length limited code which satisfies the limitations of the minimum run length and the maximum run length, and the sync signal includes the sync pattern comprising the bit pattern of the run length that is longer than the maximum run length by 3T and the addition bit patterns which are arranged before and after the bit pattern and each of which has a run length that is longer than the minimum run length. The sync signal includes the specific code which indicates the position in the sector and which enables the DC control to be performed.
In
All of code words obtained by the 8-16 modulator 10 have pattern forms which satisfy any one of the following conditions of Next_State1 to Next_State4.
The modulating method has been published by the following paper.
Kees A. Schouhamer Immink “EFMPlus: The Coding format of the High-Density Compact Disc”, IEEE International Conference on Consumer Electronics, WPM6.1, 1995.
A sync signal generating circuit 20 generates 32 sync signals having different bit patterns as shown in
Those 32 sync signals are divided into eight groups of SY0 to SY7 as shown in
In
A sync pattern to identify the sync signal is allocated to bits 11 to 32 of the sync signal.
The sync pattern is a bit pattern of an arrangement such as (4T or more-14T-4T) in which a pattern of 14T that is larger than the maximum interval 11T in the 8-16 modulation signal by 3T is set to a nucleous and a pattern of a fixed length of 4T and a pattern of 4T or more are arranged after and before the pattern of 14T, respectively, namely, bit pattern of {0001000000000000010001}.
In this instance, the sync pattern is a fixed pattern which is common to all sync signals as shown in
In the sync pattern, even when the 11T pattern in the 8-16 modulation signal is edge-shifted due to an influence by an inter-symbol interference and is changed to a pattern of 12T and, further, the sync pattern itself is edge-shifted and is shortened by only 1T, in order to enable both of them to be distinguished, the pattern of 14T that is larger than the maximum interval 11T in the 8-16 modulation signal by 3T is used. The 14T pattern denotes a shortest length which can be set when considering the edge-shift.
By arranging an addition bit pattern of a fixed length of 4T and an addition bit pattern of 4T or more after and before the 14T pattern, an interval that is larger than the shortest bits of 3T by at least 1T is provided, thereby reducing an influence by the inter-symbol interference with a neighboring mark.
As shown in
The reason why the rear pattern of the 14T pattern is set to the fixed length of 4T and the front pattern is set to 4T or more is because when a specific code, which will be described hereinafter, is further set before the 14T pattern, a degree of freedom of the front pattern is increased and the number of patterns to be obtained as a specific code is sufficiently assured.
As shown in
The synthesizing circuit 30 in
As shown in
The operation of the synthesizing circuit 30 for forming the transmission signal of one sector will now be described with reference to a flow of FIG. 7.
A CPU (central processing unit) and a memory (they are not shown) are included in the synthesizing circuit 30 and information as shown in
In the flow of
The CPU selects the sync signal corresponding to the storage contents in the register X from the 32 kinds of sync signals shown in
That is, only the values of bit 10 in the specific codes differ with respect to the two sync signals SY0 and the numbers of inverting times of them different when they are NZI modulated. The CPU selects the pattern which is optimum for the DC suppression from the two kinds of patterns and sets the selected pattern to final SY0.
The CPU selects the sync signal corresponding to the storage contents in the register Y. For example, when SY5 has been stored in the register Y, the sync signal corresponding to SY5 is selected from the 32 kinds of sync signals shown in
That is, only the values of bit 5 in the specific codes differ with respect to the both patterns. The CPU selects the pattern which is optimum for the DC suppression from the two kinds of patterns and sets the selected pattern to final SY5 (step S3).
The CPU generates a pattern obtained by serially connecting the 8-16 modulation signal of 91 code words to each of the sync signals selected on the basis of the storage contents of the registers X and Y as mentioned above as a transmission signal of one line as shown in
The CPU judges whether the contents in the register n are larger than 13 or not (step S5). In step S5, until it is decided that the contents in the register n are larger than 13, the CPU adds 1 to the contents in the register n (step S6) and, after that, repetitively executes the operations in step S2 and subsequent steps. The transmission signals of the first to 13th lines (of one sector) as shown in
For example, when it is assumed that 16 sectors are error-correction encoded as one error correction block and the resultant block is transmitted, a decoder side which receives the transmission signal with the structure executes an error correcting process by using the transmission signals each of which has the sector structure as shown in FIG. 6 and which are collected by the number as many as 16 sectors as one error-correction block. In the decoder, it is important that after completion of the reception of the transmission signal, the head of the sector is searched, an address recorded is subsequently immediately read out, and data of the error-correction block is collected. When the high-density transmission is executed, there is a case where the sync signal SY0 as a head of the sector cannot be read out or a case where the other signal is erroneously read out as a sector head, so that a possibility such that a fatal error which cannot be corrected is caused occurs.
In the transmission signal according to the invention, as shown in
On the decoder side which receives the transmission signal having the structure, the line in one sector can be specified by recognizing the combination pattern of the sync signals, so that the position of SY0 at the sector head can be predicted. When the line is specified, a preventing function can be further raised for a read error of the sync signal by recognizing the repetitive patterns of SY1 to SY4. Since the line is specified on the basis of the combination pattern of the two sync signals existing in one line, it is sufficient to use eight kinds of SY0 to SY7 as kinds of sync signals in one sector
Even when the sync signal SY0 as a head of the sector cannot be read out due to the influence by the high-density transmission, therefore, on the decoder side, the head position of the sector is recognized on the basis of the sync signal existing after SY0, thereby enabling a correct error-correction block to be recognized.
As will be obviously understood by
As shown in
As mentioned above, in the digital data transmitting method according to the invention, when the digital data is retained in the sectors each comprising a plurality of sync frames and is sequentially transmitted, the sync frame comprises the sync signal and the run length limited code which satisfies the limitations of the minimum run length and the maximum run length, and the sync signal includes the sync pattern comprised of the bit pattern of a run length which is longer than the maximum run length by 3T and the addition bit patterns which are arranged before and after the bit pattern and each of which has a run length that is longer than the minimum run length.
According to the invention, therefore, even when the sync signal and signal by the run length limited code are edge-shifted by 1T, respectively, due to the influence by the inter-symbol interference, they can be correctly distinguished and detected.
In the digital data transmitting method according to the invention, the sync signal includes the specific code which indicates the position in the sector and which enables the DC control to be performed.
With the construction, therefore, even when the sync signal at the head of the sector cannot be read out or the other signal is erroneously read out as a sector head, a correct head of the sector can be predicated on the basis of other sync signals, so that digital data can be properly reproduced.
The invention has been described above with reference to the preferred embodiments thereof. It will be understood that many modifications and variations can be made by those skilled in the rt. All of the modifications and variations are incorporated within the scope of the appended claims.
Tanaka, Shinichi, Arai, Takao, Shimada, Toshiyuki, Moriyama, Yoshiaki, Kurahashi, Akira, Yamada, Hisashi, Yokogawa, Fumihiko, Hirayama, Koichi, Kojima, Tadashi, Takeuchi, Toshifumi
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4124778, | Nov 02 1977 | Minnesota Mining and Manufacturing Company | Digital frame synchronizing circuit |
4539667, | Nov 10 1981 | Sony Corporation | Disc players |
4544962, | Jul 06 1981 | Matsushita Electric Industrial Co., Ltd. | Method and apparatus for processing binary data |
4685098, | Mar 08 1983 | Sony Corporation | Apparatus for reproducing data signal |
4700337, | Sep 29 1984 | Kabushiki Kaisha Toshiba | Control apparatus for a recording medium drive motor in a digital information reproducing apparatus |
4731678, | Feb 25 1985 | Matsushita Electric Industrial Co., Ltd. | Digital data recording and reproducing method |
5333126, | Jan 03 1990 | Hitachi, Ltd. | Information recording method and optical disk apparatus using same |
5375249, | Dec 29 1989 | SAMSUNG ELECTRONICS CO , LTD , A CORP OF THE REP OF KOREA | Eight-to-fourteen-modulation circuit for a digital audio disc system |
5523991, | Sep 26 1989 | Hitachi, Ltd.; Hitachi Video Engineering, Inc. | Data recording/reproducing device |
5956306, | Mar 16 1994 | Kabushiki Kaisha Toshiba | Recording medium, signal recording apparatus thereof and signal reproducing apparatus thereof |
EP673027, | |||
EP673029, | |||
JP5334810, | |||
JP61196469, | |||
JP62272726, | |||
JP6267075, | |||
KR19910013186, |
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