A uart including a logic unit is disclosed, wherein the logic unit automatically enables or disables the uart receiver port whenever data is being processed by the uart for wireless transmission. More specifically, a logic unit is connected to a data store, to a transmit FIFO and to a uart processing unit as well as to an external CPU, wherein the logic unit analyzes the logic states of each of the signals from each of the specified connections to determine whether to enable or disable the receiver unit. An inventive method is also disclosed wherein the logic unit only enables the receiver when the data store is empty and the transmitter FIFO is empty and a receiver enable flag is set to true and a half duplex mode of operation has been specified by an external CPU. Otherwise, the logic enables the receiver only when a full duplex mode of operation has been specified and the receiver enable flag is set to a logic one.
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10. A control circuit for a uart, comprising:
means for receiving at least one of a first indicator of whether the uart operates is operating in a full-duplex full duplex mode, a second indicator of whether a receiver enable flag is set, and a third indicator of whether data for transmission is stored; and
control circuitry within the uart for completely selectively disabling a receiver responsive to at least one of the first, second and third indicators.
1. A uart capable of operating in both full duplex and half duplex mode for providing single channel communications, comprising:
a transmitter for transmitting signals on a single communications channel;
a receiver for receiving signals on the single communications channel;
processing means within the uart for indicating whether the uart is operating in a full duplex mode of operation or whether a receiver enable flag has been set; and
receiver control circuitry within the uart for disabling the receiver in response to at least one the indication of a an indication by the processing means that the uart is not operating in the full duplex mode of operation and the indication of the setting of the receiver enable flag an indication by the processing means that the receiver enable flag has not been set.
7. An apparatus for providing single channel communications, comprising:
a transmitter for transmitting signals on a single communications channel;
a receiver for receiving signals on the single communications channel;
processing means within the apparatus for generating an indication of at least one of whether the apparatus is in a full-duplex full duplex mode and whether a receiver enable flag is set;
means for storing data to be transmitted by the transmitter, the means for storing generating an indication when that data for transmission is contained therein; and
receiver control circuitry for disabling the receiver in response to at least one of:
the indications of whether an indication that the apparatus is not in a the full duplex mode, ;
the indication of whether an indication that the receiver enable flag is set, ; and
the indication of whether an indication that the means for storing contains data for transmission.
2. The uart of
3. The uart of
4. The uart of
a data store for queuing data to be transmitted by the transmitter; and
a FIFO for passing data between the data store and the transmitter.
5. The uart of
0. 6. The uart of
8. The apparatus of
a data store for queuing data to be transmitted by the transmitter; and
a FIFO for passing data between the data store and the transmitter.
9. The apparatus of
0. 11. The control circuit of
0. 12. The control circuit of
0. 13. The control circuit of
0. 14. The control circuit of
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1. Technical Field of the Invention
This invention relates to wireless communications and, more specifically, to bi-directional communications utilizing only one communications channel.
2. Description of Related Art
A known problem relating to wireless single channel communications is that of undesirable reception in the receiver portion of the signal transmitted by the transmitter of the same device or system. One approach which has been used to avoid this problem of undesired reception, is to transmit a signal in one channel and to receive a response in a different channel. However, based upon the technology, it is sometimes impractical or impossible to use different channels for transmitting and receiving signals.
Another approach for preventing signal processing of undesired receptions is to transmit a portion of data and then to delete an equivalent amount of data which was received very shortly after the transmission of the data. Such an approach, however, can become quite complicated in that a device must keep track of the timing of data transmissions so that it can determine what received data requires erasing or flushing.
The use of digital signal formats for transmitting data simplifies the problem of flushing data. The reason, of course, is that the exact amount of data which is transmitted is known and therefore an equivalent amount may be deleted. By way of example, a device may determine that N number of bytes was transmitted. Accordingly, and prior to the receipt of a response from another device, a current device must delete the last N number of bytes received. As may be seen, with this embodiment, a device is allowed to receive the data it transmits, but, by careful data management, such data may be deleted before real data is received from another device. A challenge with implementing this system, however, is that the received data must be deleted quickly so as to not interfere with the reception of actual signals being transmitted by another device.
One type of device which suffers from the above problems, is an infrared transmitter/receiver which produces non-coherent light, namely light which tends to diverge rather than follow a straight path. In a device which utilizes a known infrared digital signal protocol, such as INFRA-RED DIGITAL ASSOCIATION (IrDA), transmission and reception of the signals occurs over the same “channel” because signals transmitted in the spectral frequency domain cannot be separated into a plurality of channels as readily as can other electromagnetic signals from other spectrums, such as VHF or UHF. Thus, when non-coherent light is used as a signal medium, the transmitted signal is frequently received by the optical filters of the same system or device. Accordingly, single channel infrared systems are usually adapted to purge data received after every transmission since the received signal is the very signal which was transmitted.
As was stated before, however, a difficulty with purging undesired received signals transmitted by the same device's infrared transmitter is that the response time for purging data is very small because the receiver must be ready to receive an immediate response from another unit.
Thus, in those systems which utilize a light emitting diode (LED) and which include light detectors as receivers, or any other type of wireless single channel communication, the problem of receiving a device's own transmission is real. What is needed, therefore, is an apparatus and method which prevents a device's own receiver from receiving the signals it transmits in a way which requires less processing resources and which utilizes even less time to implement, and therefore, reduces the risk of missing an initial part of a block of data which is transmitted in response by another device.
An apparatus and method is disclosed, wherein bi-directional communications are being performed in a single channel of communication which avoids unnecessary processing and allows a more efficient data transmission process in a single channel environment. The inventive apparatus includes logic circuitry that automatically disables and enables the receiver port of the UART in a manner which avoids the UART the reception of data transmitted by a device's own transmitter. By employing such logic circuitry, at least two specific advantages are recognized.
First, software interrupt handling that occurs whenever data is received by a receiver part of a UART, and which must be processed, are no longer being generated and processed due to the unnecessary reception of data which was transmitted by the UART's own transmitter. This dramatically reduces the number of unnecessary software interrupts that must be processed. Second, because UARTs frequently must be prepared to receive a nearly immediate response from another system within a small and finite amount of time, the purging of undesired data to within the real time constraints is no longer a problem because there is no longer a need to purge such data. The disclosed apparatus and method herein circumvents the timing constraints of a real time system in which unwanted data must be purged quickly by utilizing a circuit and method which automatically disables the receiver while transmissions are occurring and which enables the receiver to receive when transmissions cease to occur.
In one embodiment, a UART control circuit within a UART is disclosed in which the UART control circuit includes an input for receiving a half duplex mode signal. The UART control circuit causes the UART to operate in a half duplex mode of operation when a half duplex mode of operation indication is received. While in a half duplex mode of operation, the UART disables the receiver whenever at least one signal received at least one input, indicates that there is data for the UART to transmit.
The UART control circuit in one embodiment, includes inputs from a FIFO register set and from a data store, indicating whether there is data therein, respectively, for transmission by the UART. The logic unit also includes an input from a processing unit indicating whether a standard UART receiver enable flag has been set. The UART control circuit also includes an input to receive the half duplex enable mode signal discussed above. The UART receiver is enabled, then, whenever a half duplex mode of operation has been specified, and the transmitter FIFO and the transmitter data store are both empty. The receiver is also enabled if the half duplex mode of operation is not being specified. Otherwise, the receiver is disabled.
The inventive method includes disabling the receiver if the Receiver Enable Flag is not set by the process unit. If the Receiver Enable Flag is set, then the receiver is enabled either if the half duplex mode of operation is not being specified by an external processor or if the transmitter data store and FIFO register sets are both empty. The receiver is disabled, otherwise, if a half duplex mode of operation is specified and either the transmitter data store or FIFO register set are not empty.
A more complete understanding of the method and system of the present invention may be obtained by reference to the following Detailed Description of the preferred embodiment (s) that follow, taken in conjunction with the accompanying drawings, wherein:
Referring now to
The use of a digital signal format simplifies the problem of flushing signals, as described above. The reason, of course, is that the exact amount of data which is transmitted is known and therefore an equivalent amount may be deleted. By way of example, a device may determine that N number of bytes was transmitted. Accordingly, and prior to the receipt of a response from another device, a current device must delete the last N number of bytes received. As may be seen, with this embodiment, a device is allowed to receive the data it transmits, but, by careful data management, such data may be deleted before real data is received from another device. A challenge with implementing this system, however, is that the received data must be deleted quickly to not interfere with the reception of actual signals being transmitted by another device.
Similarly, whenever receiver 270 receives a signal 250, it generates a software interrupt which software interrupt is transmitted to processing unit 260 over line 214. Receiver 270 also transmits the received signal to receive data store 280 over line 216.
In the UART of
In the embodiment of
The UART 200 of
Referring now to
Rx Enable=(Data Store Empty AND Transmit FIFO Empty) OR Half Duplex Disable) AND Rx Enable Flag
It is understood, of course, that the above expression as well as the circuit of
Referring now to
Based upon the foregoing, those skilled in the art should now fully understand that the present invention provides an apparatus and method which significantly reduces software interrupt processing and reduces processor workload. The advantages of the invention, based upon the foregoing, also includes faster UART readiness for receiving a response from another system, and, therefore, having a lower likelihood that incoming signals will not be received.
Although a preferred embodiment of the method and apparatus of the present invention has been illustrated in the accompanying drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the embodiment disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.
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