The present invention provides a synchronizing signal separation. In accordance with the present invention, a sync pulse processing circuitry slices a video signal and senses the peaks of the synchronizing pulse. A reference generating circuitry divides the output from the sync pulse processing circuitry into a plurality of reference signals that are compared with the video signal, thereby producing logic level outputs. A sync restoring circuitry combines the logic level outputs to provide precisely reconstructed synchronizing pulses of the video signal. The present invention incorporates different standard functions with superior performance because it may be applied for different types of video signals.
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22. A method of generating an output sync signal corresponding to the sync portion of a composite video signal which sync portion comprises a plurality of sync tip levels and a blanking level, said method including:
a. generating a plurality of level signals having magnitudes responsive to said sync tip levels,
b. establishing a plurality of reference levels between said sync tip levels in response to said level signals,
c. generating a plurality of binary pulse versions of said sync portion by comparison of said reference levels and said sync portion,
d. combining said plurality of binary pulse versions to generate said output sync signal.
0. 67. A method of generating an output sync signal corresponding to a sync portion of a composite video signal, wherein the sync portion comprises a plurality of sync tip levels and a blanking level, the method comprising the steps of:
a.) generating a plurality of level signals having magnitudes responsive to the sync tip levels,
wherein at least one of the level signals is held on a first capacitor;
b.) establishing a plurality of reference levels between the sync tip levels in response to the level signals;
c.) generating a plurality of binary pulse versions of the sync portion by comparison of the reference levels and the sync portion; and
d.) combining the plurality of binary pulse versions to generate an output sync signal.
13. A video signal processing apparatus, said video signal having synchronous pulses of a pulse amplitude, said apparatus comprising:
sync tip clamping means for clamping said video signal to provide a clamped pulse signal, respective pulse of said clamped pulse signal having a leading edge and a trailing edge;
peak detecting means for sampling said video signal in response to said leading and trailing edges to generate a positive peak signal and a negative peak signal;
level dividing means for dividing level between said positive and negative peak signals into a first reference level, a second reference level and a third reference level; and
comparing means for comparing said video signal with respective said reference levels to generate logic level outputs.
4. A video signal processing apparatus for use with synchronizing pulses of a video signal including:
at least one sampling circuit for sampling said synchronizing pulses in response to a plurality of sampling signals provided, in response to said synchronizing pulses to generate at least a first reference signal and a second reference signal, said reference signals respectively representing different levels of said synchronizing pulses; and
comparing circuit for comparing said synchronizing pulses with a level responding to said reference signals to generate precision sliced pulses, with said sampling being independent of said precision sliced pulses, and further comprising combining said precision sliced pulses to generate horizontal rate and vertical rate pulse signals.
6. A synchronous signal processing apparatus for a video signal comprising:
slicing means for slicing said video signal to generate sliced pulses, said sliced pulses corresponding to respective synchronous pulses of said video signal, each of said sliced pulses having a leading edge and a trailing edge;
level detecting means for detecting respective levels of said synchronous pulses of said video signal in response to said leading and trailing edges and providing a first level signal in response to one of said edges and a second level signal in response to the other of said edges; and
sync restoring means for detecting different levels of said synchronous pulses in response to said first and second level signals and generating a derived sync pulse output in response thereto.
21. A method of generating an output sync signal corresponding to the sync portion of a composite video signal which sync portion comprises a plurality of sync levels, one of which said sync levels includes blanking level, said method including the steps of:
a. generating a plurality of level signals having magnitudes responsive to said sync levels,
b. establishing at least one reference level between each of said sync levels in response to said level signals, the number thereof changeable in response to the number of said sync levels,
c. for each said reference level established, generating a binary pulse version of said sync portion by comparison of said reference levels and said sync portion,
d. generating said output sync signal in response to said binary pulse versions of step c.
27. An apparatus for deriving a logic level version of the sync portion of a video type signal, said sync portion having a plurality of levels, one of which may be a blanking level, said apparatus including:
circuitry responsive to said sync portion to clamp the sync tip thereof to a known level thereby providing a clamped sync portion and to generate at least a first logic level sync signal in response to said clamped sync portion;
circuitry for clamping said sync portion to a known level to provide a second clamped sync portion;
circuitry for providing at least one reference signal in response to said first logic level sync signal and said second clamped sync portion;
circuitry for comparing said second clamped sync portion to said reference signal to provide said logic level version.
39. A method for processing a sync portion of a video type signal, said sync portion having a plurality of levels, comprising steps to:
a) a first separation of said sync portion to generate a first separated sync signal, including clamping the sync tip of said sync portion to a known level before said first separation;
b) generating a plurality of level signals each being representative of a level of a second clamping of said sync portion, at least one of said level signals is also generated in response to said first separated sync signal;
c) providing a reference signal in response to said plurality of level signals;
d) a second separation of said second clamped sync portion in response to said reference signal to provide a second separated sync signal which is a version of said sync portion.
31. An apparatus for deriving a logic level version of the sync portion of a video type signal, said sync portion having a number of levels N, one of which may be a blanking level, and where N may be two or more depending on the format of said video type signal, said apparatus including:
circuitry to provide a format signal changeable in response to the format of said video type signal;
circuitry responsive to said sync portion to generate at least a first separated sync signal;
circuitry for providing at least N−1 reference signal(s) in response to said sync portion and said first separated sync signal; and
circuitry responsive to said sync portion and said format signal and said reference signal(s) for comparing said sync portion to said reference signal(s) to provide said logic level version.
40. A method for processing a sync portion of a video type signal, said sync portion having a plurality of levels, comprising steps to:
a) a first separation of said sync portion to generate a first separated sync signal, including clamping the sync tip of said sync portion to a known level established by one or more semiconductor junction voltage drops before said first separation;
b) generating a plurality of level signals each being representative of a level of a second clamping of said sync portion, at least one of said level signals is also generated in response to said first separated sync signal;
c) providing a reference signal in response to said plurality of level signals;
d) a second separation of said second clamped sync portion in response to said reference signal to provide a second separated sync signal which is a version of said sync portion.
0. 65. A video signal processing apparatus, wherein a video signal includes synchronous pulses of a pulse amplitude, comprising:
a sync tip clamping device for clamping the video signal to provide a clamped pulse signal,
wherein the sync tip clamping device includes a current,
wherein the current varies in amount and polarity, and
wherein a respective pulse of the clamped pulse signal includes a leading edge and a trailing edge;
a peak detecting device for sampling the video signal in response to the leading and trailing edges to generate a positive peak signal and a negative peak signal;
a level dividing device for dividing levels between the positive and negative peak signals into a first reference level, a second reference level and a third reference level; and
a comparing device for comparing the video signal with respective reference levels to generate logic level outputs.
1. A video signal processing apparatus for use with the synchronizing pulses thereof, said synchronizing pulses having at least a leading edge and a trailing edge including in combination:
at least one sampling circuit for sampling said synchronizing pulses in response to a plurality of sampling signals to generate at least a first reference signal and a second reference signal, said reference signals respectively representing different levels of said synchronizing pulses, wherein said sampling circuit includes DC restoring for restoring said synchronizing pulses to a predetermined DC reference level which said DC restored synchronizing pulses are coupled to at least one comparing circuit for comparing said video signal with a level responding to said reference signals thereby providing at least a precision sliced pulse signal, with said sampling being independent of said precision sliced pulse signal.
19. A method for processing a synchronous signal of a video signal comprising steps of:
slicing said video signal to generate a sliced sync pulse signal;
sampling said video signal in response to respective leading edges and trailing edges of said sliced pulse signal so as to generate a first sample level signal and a second sample level signal; converting said first and second sample level signals into a first reference signal, a second reference signal and a third reference signal, said first reference signal representing a middle level of each synchronous pulse of said video signal, said second reference signal representing a upper level above said middle level and said third reference signal representing a lower level below said middle level;
comparing said respective reference signals with said video signal to generate logic level outputs; and restoring desired synchronous pulses in response to said logic level outputs.
17. A video signal processing apparatus, said video signal having synchronous pulses of a pulse amplitude, said apparatus comprising:
format selecting means responsive to the format of said video signal for determining the format of said video signal being processed;
sync tip clamping means for clamping respective sync tips of said video signal to provide a clamped pulse signal corresponding to said synchronous pulses, each respective pulse of said clamped pulse signal having a leading edge and a trailing edge;
sync slicing means coupling to said sync tip clamping means, for limiting an amplitude of said clamped pulse signal to provide a coarse sliced sync signal;
peak detecting means for sampling positive and negative peaks respectively of said synchronous pulses of said video signal in response to said leading and trailing edges, thereby generating a positive peak signal and a negative peak signal;
level dividing means for dividing level between said positive and negative peak signals into a first reference level, a second reference level and a third reference level, said first, second and third reference levels respectively representing different portion levels of said pulse amplitude;
comparing means for comparing said video signal with respective said reference levels to generate logic level outputs; and
restoring means coupling to said comparing means, for combining said logic level outputs to generate a plurality of precision synchronous outputs.
0. 66. A video signal processing apparatus, wherein a video signal includes synchronous pulses of a pulse amplitude, comprising:
a format selecting device responsive to a format of the video signal for determining the format of the video signal being processed;
a sync tip clamping device for clamping respective sync tips of the video signal to provide a clamped pulse signal corresponding to the synchronous pulses,
wherein the sync tip clamping device includes a current,
wherein the current varies in amount and polarity, and
wherein each respective pulse of the clamped pulse signal includes a leading edge and a trailing edge;
a sync slicing device, coupled to the sync tip clamping device, for limiting an amplitude of the clamped pulse signal to provide a coarse sliced sync signal;
a peak detecting device for sampling positive and negative peaks respectively of the synchronous pulses of the video signal in response to the leading and trailing edges to generate a positive peak signal and a negative peak signal;
a level dividing device for dividing levels between the positive and negative peak signals into a first reference level, a second reference level and a third reference level,
wherein the first, second and third reference levels respectively represent different portion levels of the pulse amplitude;
a comparing device for comparing the video signal with respective reference levels to generate logic level outputs; and
a restoring device, coupled to the comparing device, for combining the logic level outputs to generate a plurality of precision synchronous outputs.
35. A video sync pulse circuit responsive to composite sync pulses which may be part of a composite video signal said circuit operative to provide a reference voltage corresponding to the 50% level of sync, including in combination:
a) a coupling capacitor coupled to an input terminal to AC couple said composite sync pulses to a sync tip clamp circuit, said sync tip clamp circuit including a source of current operative to charge said coupling capacitor in a first direction and further including circuitry to charge said coupling capacitor in the opposite direction during at least a portion of the time said AC coupled sync tips surpass a reference, said charging action thus providing sync tip clamping to provide a sync tip clamped signal;
b) a buffer, responsive to said sync tip clamped signal to buffer same to provide a buffered signal;
c) a comparator responsive to said buffered signal and a reference to provide a compared sync signal;
d) a plurality of pulse circuits responsive to said compared sync signal from said comparator to provide a first sample and hold pulse in response to the leading edge of said compared sync signal and a second sample and hold pulse in response to the trailing edge of said compared sync signal;
e) a first sample and hold circuit responsive to said first sample and hold pulse and a DC restored form of said composite sync pulses to sample and hold the voltage level of sync tip;
f) a second sample and hold circuit responsive to said second sample and hold pulse and blanking level of said DC restored form of said composite sync pulses to sample and hold the voltage level of blanking;
g) a divider circuit responsive to the held voltage of sync tip and the held voltage of blanking to provide an in between voltage which is said reference voltage;
wherein circuitry used to accomplish one of elements a) through g) may be shared between two or more elements.
36. A video sync pulse separator separator circuit responsive to a composite video signal for providing horizontal and vertical sync pulses including in combination:
a) a coupling capacitor to AC couple said composite video signal to a sync tip clamp circuit, said sync tip clamp circuit including a source of current operative to charge said coupling capacitor in a first direction and further including circuitry to charge said coupling capacitor in the opposite direction during at least a portion of the time any AC coupled sync tip surpasses a reference, said charging action thus sync tip clamping to provide a sync tip clamped signal;
b) a buffer responsive to said sync tip clamped video signal to buffer said sync tip clamped video to provide a buffered signal;
c) a comparator responsive to said buffered signal and a reference to provide a compared sync signal;
d) a plurality of pulse circuits responsive to said compared sync signal from said comparator to provide a first sample and hold pulse in response to the leading edge of said compared sync signal and a second sample and hold pulse in response to the trailing edge of said compared sync signal;
e) a first sample and hold circuit responsive to said first sample and hold pulse and sync tip of a DC restored form of said composite video signal to sample and hold the voltage level of sync tip;
f) a second sample and hold circuit responsive to said second sample and hold pulse and blanking level of said DC restored form of said composite video signal to sample and hold the voltage level of blanking;
g) a divider circuit responsive to the held voltage of sync tip and the held voltage of blanking to provide an in between reference voltage;
h) a further comparator responsive to said reference voltage and comparison video to provide reference sync pulses, said comparison video being a version of said composite video signal of element a) having a known DC level;
i) a half horizontal pulse eliminator circuit responsive to said reference sync pulses to output horizontal rate pulses;
j) a vertical synchronizing filter circuit responsive to said reference sync pulses to output a vertical rate pulse;
k) a field synchronizing circuit responsive to at least circuit element j) and to the relationship of horizontal sync pulses and the leading edge of vertical sync to output a field synchronizing pulse signifying odd and even fields,
wherein circuitry used to accomplish one of elements a) through k) may be shared between a plurality of elements.
2. A video signal processing apparatus as recited in
a detecting circuit for detecting respective levels of said synchronizing pulses in response to said leading and trailing edges and outputting a first level signal and a second level signal; and
converting circuit for converting said first and second level signals into said first and second reference signals.
3. A video signal processing apparatus as recited in
5. A video signal processing apparatus as recited in
7. A synchronous signal processing apparatus as recited in
transforming means a resistor divider circuit for transforming said first and second level signals into a first reference signal, a second reference signal and a third reference signal; and
comparing means for comparing said synchronous pulses with said first, second and third reference signals to generate logic level outputs.
8. A synchronous signal processing apparatus as recited in
9. A synchronous signal processing apparatus as recited in
10. A synchronous signal processing apparatus as recited in
11. A synchronous signal processing apparatus as recited in
12. A synchronous signal processing apparatus as recited in
14. A video signal processing apparatus as recited in
15. A video signal processing apparatus as recited in
16. A video signal processing apparatus as recited in
18. A video signal processing apparatus as recited in
20. A video signal processing apparatus method as recited in
23. A method as claimed in
24. A method as claimed in
25. A method as claimed in
26. A method as claimed in
28. An apparatus as claimed in
29. An apparatus as claimed in
30. An apparatus as claimed in
32. An apparatus as claimed in
33. An apparatus as claimed in
34. An apparatus as claimed in
each of which reference signals are is responsive to at least one sync portion level.
37. The video sync pulse circuit of
38. The video sync pulse circuit of
41. A method as claimed in
0. 42. The video signal processing apparatus of
wherein the current varies in amount and polarity.
0. 43. The method of
e.) clamping the composite video signal,
wherein step (e) utilizes a current,
wherein the current varies in amount and polarity, and
wherein step (a) is performed in response to step (e).
0. 44. The method of
wherein a first reference level value lies substantially equidistant from outer level signals, and
wherein a second reference level value lies substantially one quarter of the distance from one of the outer level signals.
0. 45. The method of
wherein a first reference level value lies substantially equidistant from outer level signals,
wherein a second reference level value lies substantially one quarter of the distance from a first of the outer level signals, and
wherein a third reference level value lies substantially three quarters of the distance from the first of the outer level signals.
0. 46. The method of
wherein a first reference level value comprises a voltage of substantially half-way between sync tip and blanking levels, and
wherein a second reference level value comprises a voltage of substantially half-way between the half-way level and blanking level.
0. 47. The method of
wherein a first reference level value comprises a voltage of substantially half-way between sync tip and blanking levels, and
wherein a second reference level value comprises a voltage of substantially half-way between the half way level and sync tip level.
0. 48. The method of
e.) clamping the composite video signal to a known level before step (a),
wherein step (e) includes the steps of:
f.) comparing the composite video signal to the known level; and
g.) selectively injecting a current into a coupling capacitor carrying the composite video signal,
wherein the amount of the current is responsive to the difference between the composite video signal and the known level.
0. 49. The method of
e.) clamping the composite video signal,
wherein step (e) utilizes a current,
wherein the current varies in amount and polarity, and
wherein step (a) is performed in response to step (e).
0. 50. The apparatus of
wherein the current varies in amount and polarity.
0. 51. The apparatus as claimed in
0. 52. The apparatus as claimed in
0. 53. The apparatus of
circuitry operable to clamp the video type signal to a known level by use of a current, the current having a variable amount and changing polarity, and
wherein the current is responsive to the video type signal and the known level.
0. 54. The apparatus of
0. 55. The apparatus of
0. 56. The apparatus of
0. 57. The apparatus of
0. 58. The video sync pulse circuit of
wherein the variable current is capable of changing polarity.
0. 59. The video sync pulse circuit of
0. 60. The video sync pulse separator circuit of
wherein the variable current is capable of changing polarity.
0. 61. The method of
wherein the variable current is capable of changing polarity.
0. 62. The method as claimed in
0. 63. The method as claimed in
0. 64. The method of
wherein the variable current is capable of changing polarity.
0. 68. The method of
e.) sampling a first of the sync tip levels and holding a first sample value on the first capacitor; and
f.) sampling a second of the sync tip levels and holding a second sample value on a second capacitor.
0. 69. The method
0. 70. The method of
0. 71. The method of
wherein a second reference level is at substantially a midpoint between one sync tip level and blanking level.
0. 72. The method of
wherein a second reference level is at substantially a midpoint between a first sync tip level and blanking level, and
wherein a third reference level is at substantially a midpoint between a second sync tip level and blanking level.
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This application is a continuation of application Ser. No. 07/837,323, filed Feb. 18, 1992, now abandoned.
The present invention relates to signal processing systems and, in 116 101 is applied to differential input amplifier 102 where video signal 101 is amplified to improve the ratio of signal/common mode noise. The video signal amplified by input amplifier 102 is fed to sync pulse processing section 104 which includes a sync tip clamp 116, a sync slicer 118 and a sync tip peak 15 detector 120.
The video signal is first clamped by sync tip clamp 116 to generate a clamped signal which has a known DC level of the synchronizing pulses. The clamped signal is then transferred to sync slicer 118 where the clamped signal is sliced, thereby generating a signal that has the same time period as that of the synchronizing pulses but at standard levels as compared to that of the synchronizing pulses, in this example TTL levels. To effectively eliminate interference and noise, the sync slicer 118 slices the synchronizing pulses at a known level which is preferred to be about half of the nominal expected amplitude of the synchronizing pulses. Due to the a known level which is approximately half the expected level, the operation of sync slicer 118 may be considered a coarse slicing operation which provides coarse sliced pulses. The sliced signal is coupled to sync tip peak detector 120, in which peaks of synchronizing pulses of the video signal from DC restoration device 110 are sampled in response to the sliced signal.
The clamped signal is also delivered to pulse width adjust 106. This clamped signal activates pulse width adjust 106 to generate a pulse trigger signal coupling to DC restoration device 110. The pulse trigger signal determines the pulse width of the synchronizing pulses. A switch SWP is provided with pulse width adjust 106. Changing the status of the switch SWP may adjust the width of the pulse trigger signal.
The video standard detector 103 is provided for determining the video signal output from the input amplifier 102. When the video signal, for example, is a NTSC video signal, video standard detector 103 controls switch SWL, so that this switch is open, which indicates that the video signal is a NTSC TV signal. On the other hand, when the video signal output from the input amplifier 102 is a HDTV signal, the video standard detector 103 will turn switch SWP on. The video standard detector 103 also control switches SWT, SWU and SWL. The switches may be operated automatically in response to a video standard detector 103 which detects the type of signal 101. Therefore, the synchronizing signal processing apparatus 100 in accordance with the present invention may process different video signals.
Offset device 108 provides a DC reference for DC restoration 110. The amplified video signal from the input amplifier 102 is also coupled to DC restoration 110. In response to the reference from offset device 108, DC restoration 110 clamps the amplified video signal to eliminate DC shift and residual common mode noise.
Other types of DC restoration circuits may be used as is well known in the art. It is desired to have the video signal VO1 and VO2 restored to a known value. However, it should be noted that the DC restoration device 110 may be eliminated by directly AC coupling the video signal output from the input amplifier 102 to the reference sync generating section 112 and sync pulse processing section 104. The operation of sync tip peak detector 120 will track the variations in the AC coupled video signal output from the input amplifier 102 and allow the comparator 122 to function properly. However, the use of a DC restoration device is preferred.
The DC restoration device 110 produces two output signals VO1 and VO2. The clamped video signal VO2 is delivered to sync tip peak detector 120. In response to the sliced signal from the sync slicer 118, sync tip peak detector 120 samples the positive and negative peaks of synchronizing pulses of the clamped video signal so as to provide two peak sample pulse signals. For purpose purposes of the present example, video is described with respect to positive white with the negative level of sync being that which is farthest from peak white video and the positive level of sync being that which is closest to the peak white value of the video. For two level sync, such as NTSC, the positive peak will correspond to video blanking level. The two peak sample pulse signals define each of the synchronizing pulse pulses. Divider 124 receives them and converts them into three pulse reference signals. The amplitudes of the pulse reference signals represent percentage levels of sync of VO2 during the respective ones of the peak sample pulses as represented by Vh and VI.
Reference sync generating section 112 also includes a comparator 122. The clamped video signal from DC restoration 110 and three pulse reference signals are coupled to comparator 122. By comparison, comparator 122 outputs four level signals during each synchronizing pulse of the video signal. Due to the use of references which are responsive to the actual level of the sync pulse, the comparator 122 may be considered a precision comparator, which outputs precision sliced pulses. The four level signals represent different amplitudes of each synchronizing pulse as determined by the video sync being greater than none, one, two or three of the pulse reference signals.
A sync restoring section 114, which includes combination logic 126 and vertical sync filter 128, is arranged to receive the output signals from the comparator 122 of reference sync generating section 112. The combination logic 126 is used to combine the four output signals from comparator 122 to recover reliable synchronizing signals. Switches SWU and SWL are arranged to control the switching between the HDTV video signal and conventional TV video signals, for example NTSC TV video signal.
The opening of switches SWU and SWL indicates that the synchronizing signal processing apparatus operates with conventional video signal. Otherwise, the closing of the switches SWU and SWL shows out that the apparatus operates with HDTV video signal. The position of another switch SWT is also related to the video signal being processed by the apparatus in according accordance with the present invention. Therefore, the apparatus of the present invention is suitable to different video signals by changing status of these switches, which may respond automatically to the video standard detector 103 as well.
The vertical sync filter 128 is coupled to the combination logic 126. A composite synchronizing signal CS from the combination logic 126 is coupled to it. The vertical sync filter 128 filters the composite synchronizing signal CS to provide a vertical synchronizing signal VS. The vertical sync filter 128 may respond to a composite synchronizing signal from other sections as well, for example from 112.
The sync pulse processing section 104 of synchronizing signal processing apparatus 100 is detailed with reference to FIG. 2. Input amplifier 102 includes two operational amplifiers OP1 and OP2. OP1 is used with OP2 to eliminate common mode noise of the video signal 101. The positive input of OP1 receives one of input video signal 101 which is the common one (shield) of the input signals. Resistor R1, 100 KΩ, is an input resistor for stabilizing the DC component of the input video signal.
A resistor R2 (75 Ω) and a switch SWl are connected between the input lines for terminating video signal 101. When the input is taken from other than the end of a coaxial cable run, SWI is open. While the video signal 101 is applied to input amplifier 102 at the end of a coaxial cable run, SWL is closed so that the input resistance of input amplifier 102 is matching the output resistance of the circuitry providing video signal 101, thereby reducing signal loss. Capacitor C1 (0.1 μf) provides a high frequency bypass from the common to ground. R2 is the terminating resistor (75 Ω). OP1 and resistors R3 (1.10 k KΩ) and R4 (499 Ωconstitute Ω) constitute a negative feedback amplifier its gain being two approximately. The output of OP1 is coupled to the negative input of OP2 via resistor R5, 2.21 KΩ.
The positive input of OP2 receives the signal directly from the input signal 116 101. OP2 and resistors R6, R7 and potentiometer R8 provide another feedback amplifier. Resistor R6 and R7 have the same resistance, 1.0 KΩ. The potentiometer R8 has a resistance from 0-10 KΩ. Thus, the gain of the input amplifier 102 may be adjusted between 1.5-3. Due to the delay caused by OP1, the common mode component of input signal 101 arrives at the positive and negative inputs of OP2 at slightly different moment. Under low frequency, the delay due to OP1 is tolerable. However, high frequency components of the input video signal, after delay by OP1, would severely affect correlation of the common mode signal, causing distortion of the video signal. Therefore, a filter having capacitor C1 of 0.01 μf is utilized to filter the interference and noise to ground.
The output of OP2 is coupled to the sync tip clamp 116 of the sync pulse processing section 104. The sync tip clamp 116 includes buffers OP3 and OP4, and an amplifier OP5. Resistor R9 (5.6 KΩ) is used with capacitor C2 to by-pass undesired frequency components. The buffered video signal is coupled to the positive input of another buffer OP4 via an isolating capacitor C3, 0.1 μf. A negative 12 V is applied to the isolating capacitor C3 and the positive input of OP4, via a current limit resistor R10, 147 KΩ. R10 effectively constitutes a constant current source. The isolating capacitor C3 is used to isolate the direct current components of the video signal.
The negative 12 V applied to the capacitor C3 draws node N1 toward a negative level, pulling the video signal output from OP3 to a negative level. The negative video signal, after buffering by buffer OP4, is coupled to the negative input of the amplifier OP5 via a resistor R11 with resistance of 10 KΩ. OP5 and a resistor R12 with resistance of 39 KΩ establishes a negative feedback amplifier. The positive input of OP5 is grounded. The resistance of the resistor R12 determines the maximum gain of amplifier OP5, which may be lowered if D3, D4 conduct.
Normally, the output of OP5 is negative. Two diodes D1 and D2 are provided to isolate the output of OP5 from the node N1. When the output of OP5 is above a level required to turn the D1 and D2 on, for example 1.2 V, the capacitor C3 is charged positive. The resistor R10 charges C3 negative, but is countered by the current through D1 and D2 when the video signal is below the ground of the positive input of OP5, thus causing N1 to move in a positive direction, which forces the output signal of OP5 to be returned to a negative value. The other two diodes D3 and D4 are arranged between the negative input and output of OP5. When the video signal at the negative input of OP5 is more positive by a level high enough to turn D3 and D4 on, the negative input and output of OP5 are shorted so that OP5 functions as a buffer and prevents large negative excursions at the output, thereby causing OP5 to recover to normal status very quickly, when returning positive.
Sync slicer 118 includes a comparator CP6. The output of OP5 is directed to the positive input of CP6. The output of OP4 is directed to the negative input of CP6. By comparison of the signals at its inputs, CP6 slices the synchronizing pulses of the video signal at about half of the amplitude. By using both the outputs of OP4 and OP5, the comparison is less sensitive to noise and sync amplitude variations than if a fixed level were used. For the NTSC and HDTV video signals, the output of CP6 has a delay of about 0.1 μs. Comparator CP6 slices the amplitude of the synchronizing pulses without appreciable change of pulse width.
The sliced pulses output from CP6 are directed to the sync tip peak detector 120. The sync tip peak detector 120 includes sample switches SW1 and SW2, and two sample holders consisting of resistors R15 and R16 with the same resistance of 1 KΩ, and capacitors C6 and C7 with the same capacitance of 0.1 μf. Resistor R15, capacitor C6 and switch SW1 constitute a sample and hold circuit. Resistor R16 and capacitor C7 and SW2 constitute another sample and hold circuit. Two buffers OP7 and OP8 are respectively coupled to the two sample and hold circuits to output the sampled signals.
The sliced pulses from CP6 are first inverted by an invertor I1. Thus, the rising edge of the inverted pulses coincide with the trailing edge of the output pulses of CP6. Each of the inverted pulses is then differentiated at its rising edges, by means of a differential capacitor C4 of 0.001 μf and a differential resistor R13 of 330Ω. The switch SW1 is in the receipt of the signal VO2 output from the DC restoration device 110. Usually, switch SW1 is tied to ground via resistor R13. Only upon the arrival of the rising edges of the inverted pulses, switch SW1 is activated to couple to the hold circuit having R15 and C6. Therefore, corresponding to each falling edge of the sliced pulses output from CP6, R15 and C6 sample the positive peaks of the pulses. Note that the sliced sync from CP6 is opposite in polarity to the sync of VO2. The sampled positive peak is held for the buffer OP7 to output. The width of the differential pulse for sampling the video signal is set by C4 and R13.
Similarly, after inversion twice by invertors I2 and I3, the output of CP6 is differentiated by a differential capacitor C5 of 0.001 μf and a different differential resistor R14 of 330Ω. Thus a differential pulse is coupled to switch SW2. The differential pulses produced by C5 and R14 cause the switch SW2 to close so that a resistor R16 of 1 KΩ and a capacitor C7 of 0.1 μf hold the negative peaks of the synchronizing pulses. The two signals which operate sample switches SW1 SW1 and SW2 SW2 can be described as reference taking signals, since they take the instant samples which are in turn held by the hold capacitors to generate the voltage reference signals used by the divider 124 to provide reference for comparator 122.
As a result, each of the pair of differential pulses produced by C4, R13, C5 and R14 defines the pulse position of respective synchronizing pulses. The relationship of the output pulses of CP6 and the differential pulses is shown in FIG. 5. Furthermore, buffers OP7 and OP8 deliver the peak sample signals to divider 124 for further processing.
The video signal amplified by the input amplifier 102 is also coupled to the DC restoration device 110, referring to FIG. 3. The DC restoration device 110 includes a voltage comparator CP9, a photosensitive element having a LED (light-emitting diode) Du and a photoresistor R59, an amplifiers amplifier OP10 and a buffer OP11. A positive 5 V DC voltage is tied to a resistor R17 or 1.0 KΩ, the left part of the photoresistor R59 and the tap of R16 R59 is connected to ground. Thus, the voltage applied to the positive input of the CP9 depends on the resistance of left part of R59. On the other hand, the positive 5 V is tied to a series connection of potentiometer R18 and a resistor R19 and to ground. Thus, the reference voltage at the negative input of CP9 is defined by the position of the wiper of potentiometer R18. Therefore, adjusting the position of the wiper of potentiometer R18 may change the input voltage at the negative input of CP9.
At the output of CP9, a positive 5 V is applied to the LED Du through a resistor R20 of 200Ω. The positive 5 V provides an offset current to LED Du. The light intensity of the LED Du is in proportion to the current flowing through it. The resistance of photoresistor R59 is inversely proportional to the light intensity. Therefore, the higher the output of CP9, the larger the current through the LED Du, the lower the resistance of the photoresistor R59. The lower resistance of R59 makes the voltage applied to the positive input of CP9 go down, thereby causing the output of CP9 to decrease. CP9 thus causes R59 to maintain the voltage at the positive and negative inputs of CP9 to be equal.
The output of the input amplifier 102 is coupled to the positive input of the amplifier OP10 of DC restoration device 110, via a resistor R1 R21 of 330Ω. The output of OP10 is tied to the negative input via a feedback resistor R22, 1.0 KΩ and the right part of the photoresistor R59 ties the negative input of OP10 to ground. Because the output of CP9 may change the resistance of R59, the gain of OP10 is also controlled by the output of CP9. Therefore, changing the position of the wiper of potentiometer R18 changes the gain of OP10.
The output of OP10 is applied to the positive input of amplifier OP11. Along with a resistor R23 of 1.0 KΩ, the operational amplifier OP11 buffers the output of OP10. The video signal from buffer OP11 is transferred to the sync tip peak detector 120 where the video signal is sampled in response to the pulses from the sync slicer 118, as shown in FIG. 2. The video signal output amplified by OP10 is also sent out by an output resistor R24, 71.5Ω for other purposes.
An offset device 108 is arranged to provide a DC offset required by the operational amplifier OP13 of the DC restoration device 110. The offset device 108 includes a resistor network having a resistor R57 (100 KΩ), a resistor R57 R56 (100 Ω) and a potentiometer R55. A positive 12 V is coupled to resistor R57 and a negative 12 V is coupled to resistor R25 R56. A voltage determined by the position of the wiper of potentiometer R55 charges a capacitor C13 of 0.1 μf via a resistor R58 of 100 KΩ. The level on the capacitor C13 is applied to the positive input of a buffer OP12.
The offset voltage is delivered to an integrator circuit established by a operational amplifier OP 13 and a capacitor C8 (0.1 μf) bridging between the negative input and output of OP13. The positive input of OP13 receives the offset voltage. The offset voltage is also coupled to a switch SW3. The common close status of SW3 couples the offset voltage to the negative input of OP13 via a resistor R25 of 10 KΩ. A capacitor C9 of 0.001 μf is tied between ground and SW3 for filtering undesired frequency components and switching transients.
In accordance with the present invention, the pulse width adjust 106 is provided for . The pulse width adjust 106 includes two multivibrators 301 and 302. The output from the sync slicer 118 is coupled to the A Ā input of 301, as shown in
The output from sync slicer 118 is also coupled to the B input of multivibrator 302 via a delay circuit. This delay circuit includes two RC filters. A capacitor C14 (51 pf) and a resistor R28 (10 KΩ) form a RC filter and a capacitor C12 (56 pf) and a resistor R60 (2.5 KΩ) provide another one. Two invertors I4 and I5 are arranged between the two RC filters. An invertor I6 is positioned between the B input of 302 and RC filter having C12 and R60. A positive 5 V is applied to R28 via a resistor R58 R27 (1 k KΩ) for providing a DC bias. This delay circuit delays the sliced signal from sync slicer 118 about 0.75 μs to 0.9 μs.
The pulses at the
Therefore, the pulse width of Q output of 302 is between 2 μs and 2.5 μs for the NTSC video signal. This pulse occurs during blanking and burst portion of the NTSC video signal. On the other hand, the pulse width of the Q output of 302, for the HDTV video signal, is from 0.5 μs to 0.7 μs. The pulse of Q output of 302 coincides with the blanking portion without exceeding it. The waveform at the Q output of 301 is shown in FIG. 5.
The output pulses at the Q output of 302 activate the SW3 so that the output from OP11 is coupled to the negative input of OP13 via the RC filter having the resistor R25 and the capacitor C9. During the high level of the pulses from 302, the capacitor C8 of the integrator OP13 is charged up and down by the video signal from the buffer OP11 depending on whether it is above or below the reference on the plus input of OP13, drawing the input voltage at the positive input of OP10 up or down. As a result, the output of OP10 is drawn up or down. After the Q output of 302 recovers to a low level, the switch SW3 is released so that the negative input of the operational amplifier OP13 is coupled to the output of OP12 of the offset device 108. Thus, the 10 output of the operational amplifier OP13 does not change.
The divider 124 of the reference sync generating section 112 includes four resistors R31, R32, R33 and R34. The resistors R31-R34 have the same resistance of 10 KΩ. Therefore, the output potential of the sync tip peak detector 120 is equally divided so that three reference potentials are provided. The first reference potential between the resistors R33 and R34 equals half of the output potential from the sync tip peak detector 120. The second reference potential between the resistors R31 and R33 equals three-fourth of the output level from the sync tip peak detector 120. The third reference potential between the resistors R32 and R34 equals one-fourth of the output level from the sync tip peak detector 120. However, different reference potentials may also be obtained by changing the resistance of resistors R31-R34. Different combination of potentials on the positive inputs of CP14-CP16 can be easily realized.
In accordance with the present invention, the comparator 122 of reference sync generating section 112 includes three comparators CP14, CP15 and CP16. The first reference potential between the resistors R33 and R34 is applied to the positive input of comparator CP14. The second reference potential between the resistors R31 and R33 is applied to the positive input of the comparator CP15. The third reference potential is then applied to the positive input of the comparator CP16. The video signal output VO1 from the amplifier OP10 of the DC restoration device 110 is coupled to respective negative inputs of three comparators CP14-CP16 via resistor R35, R36 and R37.
As for conventional TV video signals, for example, the NTSC video signal, CP14 compares the first reference potential and the video signal VO1 so as to sense the middle levels of the horizontal and vertical synchronizing pulses. The comparator CP15 then senses the video signal VO1 in response to the second reference potential and the rest of the video signal VO1 is regarded as noise. Because the switch SW1 of sync tip peak detector 120 closes during the blanking-burst period to sample the video signal, the second reference potential is set to a level lower than the blanking level. The switch SW2 of sync tip peak detector 120 closes during the negative synchronizing tip to sample the video signal, the third reference potential is thus set to a level higher than the negative tip. Two complementary outputs VP3 and VC3 from CP16 are delivered to the combination logic 126.
As a second example, when the apparatus 100 in accordance with the present invention is used for processing the HDTV video signal, the second reference potential represents a value between the blanking and positive peak synchronizing tip for the synchronizing pulses. The rest of the video signal VO1 is considered as noise. The first reference potential is set at the middle of the negative and positive synchronizing tip during synchronizing pulses, meaning at the blanking level. The purpose of this comparator CP14 is to sense transition from the negative synchronizing tip to the positive synchronizing tip. The rest of the video signal VO1 is considered as noise. The reference potential and the output VP3 of CP16 is the same as under the NTSC video signal. Therefore, outputs of comparator 122 are logic levels corresponding to the negative sync for these video signals.
The logic level outputs VP1, VP2, VP3 and VC3 from the comparator 122 are directed to the combination logic 126 of the sync restoring section 114, as shown in FIG. 4. The output VP1 of the comparator CP14 is directed to an input of an AND gate A1. The signal VC3 output from the comparator CP16 is inverted by an invertor I7, and is filtered by a RC filer having a resistor R53 (200Ω) and a capacitor C17 (0.001 μf). Before it is applied to another input of the AND gate A1, the filter signal VC3 is inverted again by an invertor I8. In order to preserve the combination logic generated sync information at the half way crossing, the output VC3 from the comparator CP16 is delayed by the invertor I7 and I8 circuit for 85 ns-200 ns. Thus, the two input pulses are anded at the inputs of the AND gate A1 so that the output of A1 is a positive pulse.
Along with the output from the AND gate A1, the output VP2 from the comparator CP15 is directed to an input of an OR gate O1. The positive pulse from A1 and the VP2 active the OR gate O1, thereby producing a pulse which has a rising edge defined by the positive pulse from A1 and a falling edge defined by V′P2. The output of OR gate O1 is directed to another OR gate O2.
The output VC3 is also used to trigger a multivibrator 401 so that a high level is set at the
The ANDed output from A2 is applied to another input of OR gate O2 so that the output from OR gate O1 is ORed with the ANDed output from A2. Particularly, under processing the NTSC video signal, the ORed output of OR gate O1 is completely determined by the ANDed output pulse from A2. The reason is that the negative ANDed output from A2 is narrower than the negative ORed output from O1. The output of O2 is a composite synchronizing output CS.
In order to extract horizontal synchronizing pulses from the output CS from the OR gate O2, a circuitry including multivibrators 402 and 403, and OR gates O3 and O4 is designed. This circuitry eliminates every second half horizontal pulse from the vertical interval. The signal VC3 output from the comparator CP16 is directed to the multivibrator 402, where VC3 triggers the B input of 402 to set a low level at its
The
The Q output of 403, along with the
A multivibrator 404 is used to generate a horizontal square waveform output HQ. The output HS of the OR gate O4 is coupled to the B input of 404 via the switch SWT. When the apparatus 100 of the present invention operates under the HDTV video signal, the rising edges of output HS triggers 404 at the B input to set a high level output at its Q output. Meanwhile, the switch SWL is closed so that the positive 5 V is applied to 404 via shunted resistors R42 and R43 and a capacitor C21. Accordingly, the duration of the high level depends on a capacitor C21 and the resistance of shunted resistors R42 and R43. If the capacitance of C21 is set as 0.001 μf and R42 and R43 are respectively set as 51 KΩ, the duration is then 30 μs.
If the apparatus 100 of the present invention operates with the NTSC video signal, the output HS is reversed by an invertor I6 I9 so that the B input of 404 is triggered by the falling edges of the synchronizing pulse, setting a high level at its Q output. At the same time, the switch SWL is open so that the positive 5 V voltage is applied to 404 via only a resistor R42. Assuming R42 has the resistance of 51 KΩ and C31 C21 has the capacitance of 0.001 μf, the duration of the high level at the Q output of 404 is 30 μs.
The output CS of OR gate O2 is also directed to a vertical synchronizing filter circuitry including operational amplifiers OP17 and OP18. A resistor R44 of 37.4 KΩ and a capacitor C22 of 0.001 μf bridge across the output and negative input of OP17 to form a first stage low pass filter. The positive input of OP17 is tied to ground. The composite synchronizing output CS is coupled to the negative input of OP17 via a resistor R52 of 39 KΩ. The output from OP17 is coupled to the negative input of OP18 via a 10 Ω resistor R50. The positive input of OP18 is tied to ground. A resistor R45 (10 KΩ) and a capacitor C15 (0.001 μf) are shunted across the negative input and the output of OP18, thereby providing a second stage low pass filter.
This vertical filter circuitry employs a design 25 offsetting conventional optimal design. This design provides a frequency response characteristic without matching standard filter design curves which are commonly known. However, it is this design that provides a frequency response characteristic good for vertical synchronizing separation of the NTSC or HDTV video signal. This frequency response of the filter circuitry is shown in FIG. 6.
The filtered signal is applied to a positive input of a comparator CP19 via a 330Ω resistor R51. A resistor R46 of 3.3 k KΩ is bridged between the positive input and output of CP19 to provide positive feedback hysteresis for CP19. A positive 5 V voltage is tied to ground via resistors R47 and R48. R47 has resistance of 20 KΩ and R48 has resistance of 10 KΩ. A capacitor C16 of 0.1 μf is shunted across resistor R48, thereby providing a stable reference voltage to the negative input of CP19. Furthermore, a positive 5 V voltage is applied to the output of CP19 via a resistor R49 (1 KΩ). Filter circuitry provides a vertical synchronizing output VS via CP19 and inverted by an invertor 110.
To obtain a field synchronizing output, the vertical synchronizing output from CP19 is directed to a flip-flop 405. The clear input CLR and set input PR of 405 are coupled to a positive 5 V. The CK input of 405 receives vertical sync and the D input of 405 is coupled to H sync square waveform the
A processing method 700 for synchronizing pulses of the video signals is shown in FIG. 7. At step 701, the video signal is sliced to produce synchronizing pulses. The video signal is then sampled in response to the sliced sync to precisely sense the sync tip peaks pulses, at step 702, thereby providing two peak signal values representing the positive and negative peak values of each synchronizing pulse.
The peak signal values are further converted, at step 703, into three reference signals which respectively represent the different levels relative to each synchronizing pulse. In particular, the three reference levels respectively represent the middle, upper and lower middle levels of the synchronizing pulse. Comparison of the three reference levels and the video signal is conducted at step 704. As a result of this comparison, the logic pulse outputs are obtained. Step 705 is for restoring synchronizing pulses of the video signal by combining the logic outputs.
One skilled in the art will recognize that the above described functions and components are somewhat more complex than represented by the present block diagrams, however from the disclosure and teachings herein, taken with the available applications literature available from the manufacturers of the suggested components, or from other components which may be substituted as will be known from the above disclosure, the construction of a practical and operatable device will be well within the capability of one or ordinary skill in the art without resorting to further invention or undue experimentation.
It will be understood that the previous descriptions and explanations are given by way of example, and that numerous changes in the combinations of elements and functions as well as changes in design of the above may be made without departing from the spirit and scope of the invention as hereinafter claimed. In particular, it will be useful to combine the functions of the invention with other functions in a fashion so that such functions may be shared between devices or methods. These and other modification to and variations upon the embodiments described above are provided for by the present invention, the scope of which is limited only by the following claims.
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