Structure of delta-sigma fractional type divider

Abstract

The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.

Description

V_C(t)=A_m·sin(ω_out)
ω=ω₀+K_VCO·V_C(t),
${\varphi }_0=\int \left({\omega }_0+K_{\mathrm{VCO}}·V_c\left(t\right)\right)dt={\omega }_{0}t+K_{\mathrm{VCO}}{\int }_{-\infty }^t{V}_c\left(t\right)dt$
Therefore, V_out(t) can be approximated as $V_{\mathrm{out}}\left(t\right)\approx A\cos w_{0}t-A_m·A·\frac{K_{\mathrm{VCO}}}{{\omega }_m}·\sin {\omega }_{0}t·\sin {\omega }_{m}t=A\cos {\omega }_{0}t-\frac{A_{m}A{K}_{\mathrm{VCO}}}{2{\omega }_m}\left\{\cos \left({\omega }_0-{\omega }_m\right)t+\cos \left({\omega }_0+{\omega }_m\right)t\right\}$

Therefore, spur is generated at to ω₀±ω_m.

[Multi-Modulus Fractional N]

The dual modulus fractional ratio N can be implemented into a first order delta-sigma. As the dual modulus fractional ratio N has the quantization level of /P and /(P+1) by one bit control, at this time, the energy of spur can be effectively dispersed and reduced. In general, the dual modulus fractional ratio N is implemented into a delta sigma of over third order. In case of designing the dual modulus fractional ratio N having a delta sigma of over third order, a delta-sigma modulator of a mash type that can obtain an effect of transformation of energy shape and can obtain high stability is usually applied to a frequency synthesizer. As an output of the modulator of a mash type is multi-bit, a multi-modulus prescaler is required in order for the dividing circuit to accept it. As a result, the dividing circuit requires complicated dividing unit and control unit.

A process of inducing the mash type structure is first described, and problems in the conventional multi-modulus dividing circuit is then described.

At first, over-sampling (quantization) is described. If quantization errors are white noise, the mean square value is: $e_{\mathrm{rms}}^2=\frac{1}{\Delta }{\int }_{-\Delta /2}^{+\Delta /2}{e}^{2}de=\frac{{\Delta }^2}{12}$

And if the quantized signal is sampled to f_S=1/t, the spectral density of a band is: $E\left(f\right)={e_{\mathrm{rms}}\left(\frac{2}{f_s}\right)}^{1/2}=e_{\mathrm{rms}}\sqrt{2\tau }$

Noise power of a signal band 0≦f≦f₀ is $n_0^2={\int }_0^{f_0}{e}^2\left(f\right)df=e_{\mathrm{rms}}^2\left(2f_0\tau \right)=\frac{e_{\mathrm{rms}}^2}{OSR}$
, where
OSR=f_s/2f₀=1/2f₀t.

From the above results, it could be seen that over-sampling reduces the in-bands rms quantization noise(n₀) to a square root of OSR. Further, it could be seen that the in-band noise is reduced by about 3 dB (corresponding to ½ bit resolution) when the sampling frequency is doubled.

Referring now to FIGS. 2a˜FIG. 2c, first order delta-sigma modulation will be described. It was found that quantization using a simple over-sampling and filtering could improve SNR of 3 dB when the sampling frequency is made twice, while the in-band noise of a signal could be more reduced if feedback is introduced to the process.

FIGS. 2a˜FIG. 2c are block diagrams of the first order delta-sigma modulator. FIG. 1a illustrates a first order delta-sigma modulator, FIG. 2b illustrates an equivalent model of sampled data and FIG. 2c illustrates a Z-domain model. Analysis for the first order delta-sigma can be :expressed as follows:
S(I)=x(I)=y(I), w(I+1)=s(I)+w(I), y(I)=w(I)30 c(I)
y(I)=x(I)=s(I)=x(I)−[w(I+1)−w(I)]
w(I)+e(I)=x(I)−w(I+1)+w(I)
w(I+1)=x(I)−e(I)=y(I+1)−e(I+1)
y(I)=x(I−1)+e(I)−(I−1)

Therefore,
y(I)=x_i-1+(e_i−e_i-1).

In other words, the delta-sigma shown in FIG. 2 causes to time-delay an original signal so that the original signal can be maintained intact, and reduce quantization errors by differentiation.

In order to obtain the spectral density of n_i=(e_i−e_i-1), i.e., a noise due to modulation, Z-transform is performed. Thus, as N(z)=(1−z⁻¹)E(z) and z=e^jωL (L is sampling frequency), $N\left(f\right)=E\left(f\right)1-e^{-\mathrm{j\omega }\tau }=2e_{\mathrm{rms}}\sqrt{2\tau }\sin \left(\frac{\mathrm{\omega \tau }}{2}\right)$

Therefore, it could be seen that the noise component of a low frequency can be reduced.

The noise power at the signal band is: $n_0^2={\int }_0^{f_0}{N\left(f\right)}^{2}df\approx e_{\mathrm{rms}}^2\frac{{\pi }^2}{3}{\left(2f_0\tau \right)}^3,f_s^2⪢f_0^2$

Also, the rms value is: $n_0=e_{\mathrm{rms}}\frac{\pi }{\sqrt{3}}{\left(2f_0\tau \right)}^{3/2}=e_{\mathrm{rms}}\frac{\pi }{\sqrt{3}}{\left(OSR\right)}^{-3/2}$

Thus, it could be seen that a noise is reduced by about 9 dB (corresponding to 1.5 bit resolution) if the over-sampling ratio is doubled. If the input of the delta sigma is a direct current (DC), repetitive noise patterns appear, which is called a patterned noise. And the above equation can be easily obtained through a closed-loop transfer function of a Z-domain model shown in FIG. 2(c). $\begin{array}{c}Y\left(z\right)=\frac{1/\left(1-z^{-1}\right)}{1+z^{-1}/\left(1-z^{-1}\right)}·X\left(z\right)+\frac{1}{1+z^{-1}/\left(1-z^{-1}\right)}·E\left(z\right)\\ =X\left(z\right)+\left(1-z^{-1}\right)·E\left(z\right)\end{array}$

The delta sigma performs a noise shaping by which the energy of modulation noise is pushed out to the signal band by a feedback using the integrator. At this time, the characteristic of the integrator determines the shape of the noise spectrum.

Generally, in case that a L-order loop is formed and system is stable, the spectral density is: $N\left(f\right)e_{\mathrm{rms}}\sqrt{2\tau }{\left(2\sin \left(\frac{\mathrm{\omega \tau }}{2}\right)\right)}^L$

In case of OSR>2, the rms noise at the signal band is:

FIG. 3 illustrates a third order delta-sigma (L=3). The rms noise of the $n_0=e_{\mathrm{rms}}\frac{{\pi }^L}{\sqrt{2L+1}}{\left(OSR\right)}^{-\left(L+\frac{1}{2}\right)},OSR=1/2f_0\tau$ $n_0=e_{\mathrm{rms}}\frac{{\pi }^L}{\sqrt{2L+1}}{\left(OSR\right)}^{-\left(L+\frac{1}{2}\right)},OSR=1/2f_0\tau$
third order delta-sigma is expressed as

The delta-sigma modulator of this high order can further reduce the quantization noise of a signal band while the delta-sigma structure shown in FIG. 3 has a problem in the stability since it is a control system of a high order constituting a multi-loop. For example, the first and second order delta-sigma modulator has loop gains of 2.0 and 1.33. However, the third order delta-sigma modulator is unstable even having the loop gain of 1.15. The modulator in FIG. 3 has one bit output of +1 and −1, and also has the division ratio at the time region expressed as $f_{\mathrm{REF}}=\frac{f_{\mathrm{VCO}}}{N+b\left(t\right)},$
wherein b(t) is a bit stream of the modulator controlling the dual modulus prescaler. Therefore, assuming that the fractional value (DC) to be obtained is K/M and the quantization noise is q(t), $f_{\mathrm{REF}}=\frac{f_{\mathrm{VCO}}}{N+\frac{K}{M}+q\left(t\right)}$

At this time, K is a constant of the modulator input and M is the modulus of the modulator adder.

Now, mash type delta-sigma modulator will be described.

The mash structure where a stable first order delta-sigma structure is cascaded has a high-order noise-shaping characteristic and also allows an stable structure to be implemented.

FIG. 4 illustrates the mash type modulator in a Z-domain. At this time, the noise transfer function can be obtained by the following equation.
Y₁(z)=(1−z⁻¹)E₁(z)+X(z)
Y₂(z)=−E₁(z)+(1−z⁻¹)E₂(z)
Y₂′(z)=−(1−z⁻¹)E₁(z)+(1−z⁻¹)²E₂(z)
Y₃(z)=−E₂(z)+(1−Z⁻¹)E₃(z)
Y₃′(z)=−(1−z⁻¹)E₂(z)+(1−z⁻¹)³E₃(z)
Therefore,
Y(z)=X(z)+(1−z⁻¹)³E₃(z)
where the delta-sigma input X(z) is a fractional value of the PLL frequency synthesizer. If the division number of a prescaler is P, N(z)=P(z)+Y(z)=P(z)+X(z)+(1+z⁻¹)³E₃(z) can be obtained. From the above result, it could be seen that the mash type modulator used in the present invention has noise-shaping characteristics.

Most of conventional frequency synthesizers requires a multi-modulus dividing circuit since it uses a mash type modulator having a multi-bit output so that the above stability and a noise shaping effect of a high order can be satisfied.

FIG. 5 illustrates multi-modulus dividing circuit using a conventional direct-convertible counter. The multi-modulus dividing circuit includes a control unit 11 for receiving control signals D0, D1, and a phase selector 13 for producing /4/5/6/7 using the control signals. At this time, D2, D3, D4 and D5 control the division ratio depending on respective code values. The multi-modulus dividing circuit can be implemented in various structure as well as the structure shown in FIG. 5. The multi-modulus division structure, however, requires several dividing circuits 12 such as 2/3, and the like. Further, as control of those dividing circuits must be performed by each of dividing stages. Thus, the multi-modulus division structure has disadvantages that it is complicated and is difficult to be designed.

Claims

1. A delta-sigma fractional type divider, comprising:

a delta-sigma modulator for receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer;

a swallow adder group for receiving an output value of said delta-sigma modulator and a second digital value to add an integer dividing ratio of a swallow counter and said output value of said delta-sigma modulator, said second digital value being used to program an integer ratio frequency of the frequency synthesizer;

a program register group for storing an output value of said swallow adder group; and

a pulse swallow counter group having a dual modulus prescaler, a program counter and said swallow counter, for dividing an input frequency depending on said value stored by said program register group.

2. The delta-sigma fractional type divider as claimed in claim 1, wherein said swallow adder group comprises:

a first adder for adding the integer dividing ratio of the swallow counter and a sign value; and

a second adder for adding the output value of said delta-sigma modulator and an output value of said first adder.

3. The delta-sigma fractional type divider as claimed in claim 2, wherein said sign value is the most significant bit of said first digital value used to program the fractional ratio frequency of the frequency synthesizer.

4. The delta-sigma fractional type divider as claimed in claim 1, wherein said program register group further comprises:

a swallow register for storing said output value of said swallow adder group; and

a main division register for storing the integer dividing ratio.

5. A delta-sigma fractional type divider, comprising:

a modulator configured to use a first digital value to program a fractional ratio frequency of a frequency synthesizer;

an adder group configured to use an output value of said modulator and a second digital value, said second digital value being used to program an integer ratio frequency of the frequency synthesizer;

a program register group configured to store an output value of said adder group; and

a counter group configured to divide an input frequency depending on said value stored by said program register group.

6. The delta-sigma fractional type divider as claimed in claim 5, wherein said adder group comprises:

a first adder operable to add an integer dividing ratio of a counter and a sign value; and

a second adder operable to add the output value of said modulator and an output value of said first adder.

7. The delta-sigma fractional type divider as claimed in claim 6, wherein said sign value is a most significant bit of said first digital value used to program the fractional ratio frequency of the frequency synthesizer.

8. The delta-sigma fractional type divider as claimed in claim 5, wherein said program register group further comprises:

a register operable to store said output value of said adder group; and

a main division register operable to store the integer dividing ratio.

9. The delta-sigma fractional type divider as claimed in claim 5 wherein said modulator is a delta-sigma modulator and wherein said second digital value represents an integer dividing ratio of a counter.

10. The delta-sigma fractional type divider as claimed in claim 5 wherein the counter group comprises a dual modulus prescaler, a program counter and a counter, for dividing an input frequency depending on said value stored by said program register group.

11. A method for delta-sigma fractional type dividing comprising:

receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer;

adding an integer dividing ratio of a counter and an output value of said modulator to produce a second output value;

receiving a second digital value to program an integer ratio frequency of the frequency synthesizer;

storing the second output value using a program register group; and

dividing an input frequency depending on said value stored by said program register group.

12. The method of claim 11 wherein the adding an integer dividing ratio comprises:

adding an integer dividing ratio of the counter and a sign value; and

adding the output value of said modulator and an output value of said adding an integer dividing ratio of the counter and a sign value.

13. The method of claim 12, wherein said sign value is a most significant bit of said first digital value used to program the fractional ratio frequency of the frequency synthesizer.

14. The method of claim 11, further comprising:

storing said second output value in a register; and

storing the integer dividing ratio in a main division register.

15. The method of claim 11 wherein said modulator is a delta-sigma modulator.