An sram memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The sram memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein and the first thickness is different from the second thickness.
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6. A semiconductor circuit comprising:
a first transistor having a first width and a first gate including a gate oxide layer having a first thickness; and
a second transistor having a second width and a second gate including a gate oxide layer having a second thickness, wherein a product of the second first width and the second thickness is greater than a product of the first second width and the first thickness.
0. 13. A semiconductor circuit, comprising:
a first transistor including a first gate having a first width and including a first gate insulator having a first thickness; and
a second transistor including a second gate having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.
0. 17. A semiconductor circuit, comprising:
a first transistor including a first channel region having a first width and including a first gate insulator having a first thickness; and
a second transistor including a second channel region having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.
0. 22. A memory cell, comprising:
a pull-down transistor including a first channel region having a first width and including a first gate insulator having a first thickness; and
a transfer gate transistor including a second channel region having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.
0. 21. A memory cell, comprising:
a pull-down transistor including a first gate having a first width and including a first gate insulator having a first thickness; and
a transfer gate transistor coupled to the pull-down transistor and including a second gate having a second width and including a second gate insulator having a second thickness, a product of the first width and the second thickness being greater than or equal to a product of the second width and the first thickness.
1. An sram memory cell comprising:
a first and second transfer gate transistors, the first transfer gate transistor having a first source/drain connected to a bit line and the second transfer gate transistor having a first source/drain connected to a complement bit line and each transfer gate transistor having a gate connected to a word line; and
first and second pull-down transistors configured as a storage latch, the first pull-down transistor having a first source/drain connected to a second source/drain of said first transfer gate transistor and the second pull-down transistor having a first source/drain connected to a second source/drain of said second transfer gate transistor, both first and second pull-down transistors having a second source/drain connected to a power supply voltage node; and
wherein the first and second transfer gate transistors each have a first width and include a gate oxide layer having a first thickness, the first and second pull-down transistors each have a second width and include a gate oxide layer having a second thickness, and a product of the first second width and the first thickness is greater than or equal to a product of the second first width and the second thickness.
2. The sram memory cell of
3. The sram memory cell of
4. The sram memory cell of
where RATIO is the desired ratio of the transfer gate transistors and the pull-down transistors, Toxtg is the gate oxide thickness of the transfer gate transistor, Toxpd is the gate oxide thickness of the pull-down transistor, Wpd is width of the pull-down transistor, Lpd is the length of the pull-down transistor, Wtg is the width of the transfer gate transistor, Ltg is the length of the transfer gate transistor, Vttg is the threshold voltage of the transfer gate transistor, and Vtpd is the threshold voltage of the pull-down transistor.
7. The semiconductor circuit of
8. The semiconductor circuit of
9. The semiconductor circuit of
where RATIO is the desired ratio of the transfer gate transistors and the pull-down transistors, Toxtg is the gate oxide thickness of the transfer gate transistor, Toxpd is the gate oxide thickness of the pull-down transistor, Wpd is width of the pull-down transistor, Lpd is the length of the pull-down transistor, Wtg is the width of the transfer gate transistor, Ltg is the length of the transfer gate transistor, Vttg is the threshold voltage of the transfer gate transistor, and Vtpd is the threshold voltage of the pull-down transistor.
11. The semiconductor circuit of
12. The semiconductor circuit of
0. 14. The semiconductor circuit of
0. 15. The semiconductor circuit of
0. 16. The semiconductor circuit of
0. 18. The semiconductor circuit of
0. 19. The semiconductor circuit of
0. 20. The semiconductor circuit of
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This application is a continuation in part of an application entitled “METHOD OF MAKING TRANSISTOR DEVICES IN AN SRAM CELL”, Ser. No. 08/390,117, filing date Feb. 17, 1995 PG1 and PG2 TG1 and TG2 typically have a width of 0.9μ and a length of 0.8μ.
Referring now to
As can be seen in
Transfer gate transistor 28 in
Thereafter, the gate of pull-down transistor 28 is formed as illustrated in FIG. 3E. The gate of pull-down transistor 28 includes gate oxide layer 48 and polysilicon layer 50. Source/drains 52 also are implanted in substrate 30. Source/drains 52 include LDDs 54, which are again defined using sidewall oxide spacers 56. The thickness of gate oxide 32 is greater than the thickness of gate oxide 48. This type of processing is employed to create transfer gate transistors and pull-down transistors with different gate oxide thicknesses, which allows for a reduction in the width of pull-down transistors in an SRAM cell.
Although the depicted embodiment illustrates completely etching away the gate oxide of pull-down transistor 28, then producing a gate oxide of the desired thickness, other methods of producing different gate oxides may be employed according to the present invention. For example, a gate oxide layer may be grown for transfer gate transistor 28 first, and then an additional gate oxide layer can be grown on both pull-down transistor 26 and transfer gate transistor 28 to produce gate oxide layers of different thicknesses for each of the transistors. Transfer gate transistor 28 is completely masked from processing after completion, and remains in the form depicted in
According to the present invention, a reduced width pull-down transistor dimension may be employed by adjusting the ratio of the gate oxide thickness between the transfer gate transistors and the pull-down transistors in the SRAM cell. The needed thicknesses of the two gate oxides may be selected using the following equation:
where RATIO is the desired ratio of the transfer gate transistor and the pull-down transistor, TOXtg is the gate oxide thickness of the transfer gate transistor, TOXpd is the gate oxide thickness of the pull-down transistor, Wpd is the width of the pull-down transistor, Lpd is the length of the pull-down transistor, Wtg is the width of the transfer gate transistor, Ltg is the length of the transfer gate transistor, Vcc is the upper power supply voltage, Vttg is the threshold voltage of the transfer gate transistor, and Vtpd is the threshold voltage of the pull-down transistor.
In the depicted example, RATIO is 2.6, VCC is equal to 3.3 volts, Vttg is 0.9 volts with a back bias, and Vtpd is equal to 0.7 volts. If 0.5μ feature design rules are utilized (L equal 0.5μ, W equal 0.6μ), the pull-down transistor width is 1.56μ. If the pull-down gate oxide thickness is 120 Å, a 36% reduction in pull-down transistor width (1.0μ feature), will require a 134 Å transfer gate oxide thickness. A 50% reduction in pull-down transistor width (0.8μ feature) requires a 165 Å transfer gate oxide thickness. By reducing the width (Wpd) of the pull-down transistor, the overall area of SRAM cell may be reduced.
In
Thus, the present invention provides a method and structure for reducing the overall cell area of a memory cell. The present invention provides an ability to reduce the area of a memory cell by allowing the widths of the pull-down transistors to be reduced. The reduction in width is accomplished according to the present invention by selecting different gate oxide thicknesses for the pull-down transistor and the transfer gate transistor to maintain the desired ratio.
Although the depicted embodiment defines specific numbers for ratios, widths, lengths, in other parameters may be utilized by those of ordinary skill in the art following this disclosure. In addition, the different gate oxide thicknesses for transistors in the SRAM memory cell may be applied to other types of memory cells in which widths or lengths of transistors can affect the area that a cell requires.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Chan, Tsiu Chiu, Bryant, Frank Randolph
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4866002, | Nov 26 1985 | FUJIFILM Corporation | Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof |
5285096, | Sep 13 1991 | Renesas Electronics Corporation | High stability static memory device having metal-oxide semiconductor field-effect transistors |
5373170, | Mar 15 1993 | Motorola Inc. | Semiconductor memory device having a compact symmetrical layout |
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