A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor processor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface. Also, included is a system having a display controller with an asynchronous bus interface and methods for performing read and write operations between a microprocessor and a display controller.
|
0. 32. An asynchronous bus interface configured to communicate with a display controller that is operated at a first clock speed and a microprocessor that is operated at a second clock speed, the asynchronous bus interface comprising:
flip flop chain redundancy circuitry;
wherein the asynchronous bus interface is further configured to be independent of both the second clock speed and a difference between the first clock speed and the second clock speed.
10. A system, comprising:
a central processing unit (CPU);
a data bus;
a display controller in communication with the CPU through the data bus, the display controller including a bus interface to enable communication over the data bus with the CPU, the bus interface being configured to be independent of both a clock of the CPU and a difference between a clock speed of the CPU and a clock speed of the display controller, the asynchronous bus interface including flip flop chain redundancy circuitry.
1. A display controller configured to communicate with a microprocessor; the display controller operating at a first clock speed, the microprocessor operating at a second clock speed, the display controller comprising:
a memory core for storing image data to be displayed;
a register set containing configuration data enabling presentation of the image data; and
an asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor, the asynchronous bus interface being configured to be independent of both the second clock speed and a difference between the first clock speed and the second clock speed, the asynchronous bus interface including flip flop chain redundancy circuitry.
25. A method for performing one of a read operation and a write operation between a microprocessor and a display controller over a data bus, the method comprising:
operating a microprocessor at a first clock speed;
operating a display controller at a second clock speed;
executing a handshaking routine including a request and an acknowledgement between the microprocessor and the display controller, the request being associated with a different clock speed than the acknowledgement; and
initiating a read operation or a write operation over the data bus upon completion of the handshaking routine, wherein performance of the read or the write operation is independent of both the first clock speed and a difference between the second clock speed and the first clock speed.
0. 33. An asynchronous bus interface, configured to:
receive a request signal generated at a first clock speed;
sample the request signal at a second clock speed that is different from the first clock speed;
drive a write controlling signal at a clock speed substantially equal to the second clock speed;
drive a byte selecting signal at a clock speed substantially equal to the second clock speed;
output an acknowledge signal at a first level, the acknowledge signal being driven at a clock speed substantially equal to the second clock speed;
start outputting a data signal at a clock speed substantially equal to the second clock speed;
output the acknowledge signal at a second level different from the first level, the acknowledge signal being driven at a clock speed substantially equal to the second clock speed; and
stop outputting the data signal.
19. A method for communicating between a display controller operating at a first clock speed and a microprocessor operating at a second clock speed, the method comprising:
receiving a request from a microprocessor, the request from the microprocessor being generated according to a microprocessor clock having the second clock speed;
sampling the request according to a display controller clock having the first clock speed, the sampling including double sampling of command signals to minimize an occurrence of a metastable condition;
sending an acknowledgment to the request from the microprocessor to initiate an internal cycle of the display controller;
providing data associated with a read operation or a write operation;
issuing a request from the display controller to end the internal cycle, the request from the display controller being generated according to the display controller clock; and
receiving an acknowledgement from the microprocessor, the acknowledgement being generated according to the microprocessor clock.
0. 34. A system, comprising:
a microprocessor;
a display controller configured to communicate with the microprocessor, the display controller including a memory core for storing image data to be displayed, and a register set containing configuration data enabling the presentation of data; and
an asynchronous bus interface that is configured to receive a request signal generated at a first clock speed, sample the request signal at a second clock speed that is different from the first clock speed, drive a write controlling signal at a clock speed substantially equal to the second clock speed, drive a byte selecting signal at a clock speed substantially equal to the second clock speed, output an acknowledge signal at a first level, the acknowledge signal being driven at a clock speed substantially equal to the second clock speed, start outputting a data signal at a clock speed substantially equal to the second clock speed, output the acknowledge signal at a second level different from the first level, the acknowledge signal being driven at a clock speed substantially equal to the second clock speed, and stop outputting the data signal.
2. The display controller of
3. The display controller of
4. The display controller of
5. The display controller of
6. The display controller of
7. The display controller of
8. The display controller of
9. The display controller of
11. The system of
12. The system of
13. The system of
14. The system of
a display screen in communication with the display controller, the display screen configured to display image data from the display controller.
15. The system of
16. The system of
17. The system of
18. The system of
20. The method of
21. The method of
22. The method of
23. The method of
26. The method of
receiving the request from the microprocessor according to a clock associated with the microprocessor; and
sampling the request from the microprocessor according to a clock associated with the display controller.
27. The method of
defining a set of command signals configured to determine whether a bus cycle is a read operation or a write operation and a location of valid data on the data bus.
28. The method of
29. The method of
30. The method of
minimizing an occurrence of a metastable condition by double sampling the command signals.
31. The method of
processing the command signals through flip flop chain redundancy circuitry.
|
1. Field of the Invention
This invention relates generally to computer systems and more particularly to a generic asynchronous bus interface capable of communicating with a variety of microprocessors.
2. Description of the Related Art
Portable consumer electronic devices are pervasive in all aspects of society today. Examples of such devices include personal digital assistants (PDA), mobile phones, pagers, web tablets, etc. These portable devices contain embedded systems that include central processing units (CPU). Due to the narrow range of functions provided by these handheld devices, the CPUs associated with these embedded systems are not required to have as powerful computing power as desktop or laptop CPUs. A number of vendors provide CPUs designed specifically for a type of handheld device. As is well known, the CPUs also include native buses that support the CPUs. Additionally, the devices include a display screen where images are presented under the control of a display controller, such as a liquid crystal display (LCD) controller. The display controller, typically manufactured by a vendor different from the CPU vendor, is customized to include a bus interface that allows the display controller to communicate with specific CPUs through a system bus. Because of the wide variety of the CPUs, the display controllers tend to be customized to interface with a narrow range of CPUs.
Additionally, the various CPUs and the display controllers available on the market can run at different clock speeds. Thus, the data bus through which the CPU and the LCD controller communicate, may be asynchronous to accommodate the different speeds at which the CPU and LCD controller operate. That is, since events do not happen at predetermined times, as would be the case if the CPU and the LCD controller were using the same clocks, the bus interface accommodates interlocked communication, also referred to as handshaking. Moreover, for power save purposes the display controllers targeted for specific CPUs switch to an external crystal to provide the clock. However, the external crystal may be running at a fraction of the frequency of the nominal bus frequency. Thus, certain limitations on the difference between clock speeds have to be put in place in order for the CPU and the display controller to communicate. Furthermore, it should be appreciated that the term “asynchronous” is applied loosely to bus interfaces that include a WAIT signal to allow for a variable length access. If the bas interface allows variable length access through a WAIT signal and the bus master and the bus slave use the same bus clock, i.e., define all bus events relative to a bus clock signal, then the bus interface is not truly asynchronous since the timing is slaved to a single CPU oscillator. Different clocks are used to drive and sample signals under a truly asynchronous bus interface.
One approach to address the issues caused by the different operating speeds is to set a limit for a difference between the speeds of the LCD controller and the CPU. That is, the LCD controller is targeted for CPUs having particular clock speeds based upon the clock speed difference between the LCD controller and the CPU. In addition, the LCD controller will double or triple sample a signal to guarantee within a certain time period that the signal will be sampled in order to compensate for the speed differences. That is, repeating the sampling of the signal when the speeds of the controllers are within a certain range will guarantee that the signal is sampled within the allotted clock period. One limitation of this approach is that the CPU and the LCD controller must be within a certain speed range of each other or this approach to operating in an asynchronous mode will not work.
Furthermore, because the CPU asserts signals on a different clock from the clock used by the LCD controller to receive the signals, an asynchronous bus interface can encounter a metastable condition. A flip flop or latch circuit within the bus interface of the LCD controller that receives a signal generated from the CPU has a setup and a hold time associated with the D input to the flip flop. If the setup or hold time of the flip flop is violated, then the output (Q) could become metastable. That is, the flip flop becomes “confused” to which state to go into when the rising edge of the clock for the LCD controller occurs at the same time that the CPU asserts the signal, thereby providing two infinite slopes on a signal. Since the clock for the flip flop is the LCD clock, which is separate from the clock used by the CPU to generate the signals, it can not be guaranteed that input transitions do not occur during setup intervals. The metastable condition is disastrous for a chip, since the bus cycle will fail. Thus, the occurrence of metastable conditions must be minimized in order for an asynchronous bus interface to reliably operate.
As a result, there is a need to solve the problems of the prior art to provide a display controller with an asynchronous generic bus interface capable of communicating with a variety of microprocessors irrespective of the difference in operating speeds between the display controller and the microprocessor. Additionally the circuitry of the display controller should be configured to minimize the occurrence of a metastable condition.
Broadly speaking, the present invention fills these needs by providing a generic bus interface of a display controller configured to support asynchronous data exchange that is independent of the difference in clock speed between the LCD controller and a CPU in communication with the LCD controller. Additionally, the asynchronous bus interface includes flip flop chain redundancy circuitry for minimizing the occurrence of a metastable condition. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, a system, or a device. Several inventive embodiments of the present invention are described below.
In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and the microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface.
In another embodiment, a system that allows for the asynchronous exchange of data is provided. The system includes a central processing unit (CPU) and a data bus. A display controller in communication with the CPU through the data bus is also included. The display controller has a bus interface to enable communication over the bus with the CPU. The bus interface is configured to be independent of both a clock of the CPU and a difference between a clock speed of the CPU and a clock speed of the display controller. The asynchronous bus interface also includes flip flop chain redundancy circuitry.
In yet another embodiment, a method for communicating between a display controller operating at a first clock speed and a microprocessor operating at a second clock speed is provided. The method initiates with a request from a microprocessor being received by a display controller. The request from the microprocessor is generated according to a microprocessor clock. Then, the request is sampled according to a display controller clock. Next, the request from the microprocessor is acknowledged by the display controller to initiate an internal cycle of the display controller. Then, data associated with a read operation or a write operation is provided. Next, a request from the display controller to end the internal cycle is issued to the microprocessor. The request from the display controller is generated according to the display controller clock. Then, an acknowledgement from the microprocessor is received by the display controller. The acknowledgement is generated according to the microprocessor clock.
In still yet another embodiment, a method for performing a read operation or a write operation between a microprocessor and a display controller over a data bus is provided. The method initiates with operating a microprocessor at a first clock speed. Then, a display controller is operated at a second clock speed. Next, a handshaking routine is executed. The handshaking routine includes a request and an acknowledgement between the microprocessor and the display controller. The request is associated with a different clock speed than the acknowledgement. Then, a read operation or a write operation is initiated over the data bus upon completion of the handshaking routine, wherein performance of the read or the write operation is independent of a difference between the first clock speed and the second clock speed.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, and like reference numerals designate like structural elements.
An invention is described for an apparatus and method for providing a generic bus interface for a controller that is adapted to communicate with a variety of central processing units (CPU). It should be appreciated that the various signals processed through the bus interface are referred to herein as an abbreviation for the signal followed by the “#” symbol. Of course, other common designations in the art for signals include an abbreviation with an over line or an abbreviation followed by the letter “X”. Additionally, logic high values may be referred to as having a binary value of “1” while a logic low value may be referred to as having a binary value of “0.” It will be apparent, to one skilled in the art, in view of the following description, that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.
The embodiments of the present invention provide a generic bus interface for a display controller in communication with a CPU. In one embodiment, the configuration of the command signals provided to the generic bus interface enables communication with a variety of microprocessors and their associated native buses. As will be explained in more detail below, the command signals are configured to define a read or write operation to be performed as well as defining a location of valid data on the native bus. In another embodiment, the generic bus interface accommodates an asynchronous exchange of data. Here, the display controller and the CPU are controlled by different clocks having different clock speeds. Through the handshaking defined between the CPU and the display controller, previous limitations required due to the inability to accommodate all differences between the clock speeds, no longer apply.
The generic bus interface described herein, is capable of communicating with a variety of CPUs, particularly the CPUs in the embedded market, which include processors from HITACHI, MOTOROLA, INTEL, etc. As is well known, embedded systems define microprocessor based electronic systems that perform an application-specific set of functions. Embedded systems tend to be dedicated to sensing and responding to input. One skilled in the art will appreciate that the embedded systems exist in many industries, including automotive, communications, consumer and industrial. More specifically, embedded systems are used with compact portable handheld devices, such as personal digital assistants (PDA), mobile phones, pagers, web tablets, etc. These portable handheld devices do not require the same amount of computing power as a desktop or laptop computer because of their specific nature. Additionally, these devices consume less power than the desktop or laptop systems because of battery power limitations. Accordingly, devices incorporating embedded systems do not provide the same degree of functionality as desktop computer systems. While the embodiments described below are directed toward CPUs for handheld electronic devices, these embodiments are exemplary and not meant to be limiting. It will be apparent to one skilled in the art that the generic bus interface can be configured to communicate with CPUs for desktop and portable personal computers in addition to handheld devices.
In one embodiment, the generic bus interface supports a data width of 32 bits addressable over 21 bits of address space. Of course, the bus interface can support a data width over any suitable number of bits of address space. The bus interface is configured to accommodate the signals that are necessary to attach to most CPU interfaces through the command signals explained in more detail below. Little and big endian modes are both supported by the generic bus interface. One skilled in the art will appreciate that little and big endian modes describe the order in which a sequence of bytes are stored in memory. As described in more detail below, the embodiments of the bus interface include a bus interface configured to operate in a synchronous mode and a bus interface configured to operate in an asynchronous mode. In the synchronous mode, the bus cycle can be lengthened through the use of an external WAIT# control signal which can be set to active high or active low. The asynchronous generic bus interface is configured to be independent of the difference between the clock speed of the display controller and the clock speed of the CPU in communication with the display controller. In addition, the asynchronous bus interface includes circuitry for minimizing the occurrence of a metastable condition.
Still referring to
Still referring to
Continuing with
Additionally, each of the command signals of
Referring to
Parameter t1 of
Still referring to
Continuing with
For a write operation, with reference to
Still referring to
Still referring to
Still referring to
The CPU requests the cycle from the LCD controller by asserting CS# low. The LCD controller responds to the request with an acknowledge signal, i.e., WAIT#. It should be appreciated that the request and acknowledge signals are the two handshaking signals used to initiate a bus cycle. Furthermore, while the CPU issues the request according to the CPU clock, the LCD controller samples the request at the clock speed of the LCD controller. That is, the LCD controller is sampling the request on the rising edge of the LCD BCLK, which is independent of the BCLK for the CPU. Of course, the LCD controller can sample on the falling edge of the LCD BCLK also. Timing parameter t3 represents the time period between the LCD controller sampling CS# low and asserting WAIT# to acknowledge to the CPU that a sample is being requested. The acknowledge signal starts the bus cycle for the LCD controller. It will be apparent to one skilled in the art that t3 is variable depending on the speeds of the CPU and the LCD controller. The CPU then responds with a R/W# indicating a read or a write operation and ByteSel0#-ByteSel3# indicating the location of valid data on the data bus.
For a read cycle, with reference to
Still referring to
The method of
Still referring to
With the above embodiments in mind, it should be understood that the invention may employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Further, the manipulations performed are often referred to in terms, such as producing, identifying, determining, or comparing.
Any of the operations described herein that form part of the invention are useful machine operations. The invention also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purposes, or it may be a general purpose computer selectively activated or configured by a computer program stored in the computer. In particular, various general purpose machines may be used with computer programs written in accordance with the teachings herein, or it may be more convenient to construct a more specialized apparatus to perform the required operations.
The above described invention may be practiced with other computer system configurations including hand-held devices, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, main-frame computers and the like. Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent from the foregoing description that certain changes and modifications may be practiced within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.
Rai, Barinder Singh, Dyke, Phil Van
Patent | Priority | Assignee | Title |
Patent | Priority | Assignee | Title |
4766538, | Dec 11 1984 | Kabushiki Kaisha Toshiba | Microprocessor having variable data width |
5339395, | Sep 17 1992 | Delco Electronics Corporation | Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode |
5671433, | Sep 18 1992 | ST CLAIR INTELLECTUAL PROPERTY CONSULTANTS, INC | Mappable functions from single chip/multi-chip processors for computers |
5732250, | Sep 15 1994 | Intel Corporation | Multi-function microprocessor wait state mechanism using external control line |
5812798, | Jan 26 1996 | Freescale Semiconductor, Inc | Data processing system for accessing an external device and method therefore |
5854944, | May 09 1996 | SHENZHEN XINGUODU TECHNOLOGY CO , LTD | Method and apparatus for determining wait states on a per cycle basis in a data processing system |
5890196, | Mar 28 1996 | Apple Inc | Method and apparatus for performing page mode accesses |
5968164, | Feb 24 1995 | International Business Machines Corporation | Mixed-endian computing environment for a conventional bi-endian computer system |
6003120, | Dec 30 1993 | Intel Corporation | Method and apparatus for performing variable length processor write cycles |
6049844, | Sep 20 1994 | Renesas Electronics Corporation | Microprocessor having a PC card type interface |
6122690, | Apr 17 1998 | Mentor Graphics Corporation | On-chip bus architecture that is both processor independent and scalable |
7062588, | Mar 31 2000 | Intellectual Ventures I LLC | Data processing device accessing a memory in response to a request made by an external bus master |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Apr 25 2007 | Seiko Epson Corporation | (assignment on the face of the patent) | / |
Date | Maintenance Fee Events |
May 20 2010 | ASPN: Payor Number Assigned. |
Sep 26 2012 | M1552: Payment of Maintenance Fee, 8th Year, Large Entity. |
Dec 02 2016 | REM: Maintenance Fee Reminder Mailed. |
Apr 26 2017 | EXP: Patent Expired for Failure to Pay Maintenance Fees. |
Date | Maintenance Schedule |
Feb 10 2012 | 4 years fee payment window open |
Aug 10 2012 | 6 months grace period start (w surcharge) |
Feb 10 2013 | patent expiry (for year 4) |
Feb 10 2015 | 2 years to revive unintentionally abandoned end. (for year 4) |
Feb 10 2016 | 8 years fee payment window open |
Aug 10 2016 | 6 months grace period start (w surcharge) |
Feb 10 2017 | patent expiry (for year 8) |
Feb 10 2019 | 2 years to revive unintentionally abandoned end. (for year 8) |
Feb 10 2020 | 12 years fee payment window open |
Aug 10 2020 | 6 months grace period start (w surcharge) |
Feb 10 2021 | patent expiry (for year 12) |
Feb 10 2023 | 2 years to revive unintentionally abandoned end. (for year 12) |