Clock phase detecting circuit and clock regenerating circuit each arranged in receiving unit of multiplex radio equipment

Abstract

The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in a receiving unit of multiplex radio equipment. The receiving unit of the multiplex radio equipment includes an identifying circuit for identifying a signal obtained by demodulating a multilevel orthogonal modulation signal; a clock regenerating circuit for regenerating a signal identification clock for the identifying circuit to supply the clock to the identifying circuit; an equalizing circuit for subjecting the signal obtained by demodulating a multilevel orthogonal modulation signal to an equalizing process. A clock phase detecting unit detects the phase component of the signal identification clock based on signals input to or output from the equalizing circuit and then supplies the phase component to the clock regenerating circuit. The phase component of a signal identification clock can be certainly detected and accurately adjusted so that the signal identification clock can be regenerated with high accuracy.

Description

BACKGROUND OF THE INVENTION

1) Field of the Invention

The present invention relates to a clock phase detecting circuit and a clock regenerating circuit each arranged in the receiving unit in multiplex radio equipment.

Generally, the clock regenerating circuit which is used in the receiving unit of multiplex radio equipment is called a BTR (Bit Timing Recovery) circuit. The clock regenerating circuit usually regenerates a clock component based on a signal obtained by demodulating a multilevel orthogonal modulation signal obtained through PSK (Pulse Shift Keying) or QAM (Quadrature Amplitude Modulation) and then supplies it as an operation timing signal for an identifier (e.g. an A/D converter) that mainly identifies received data (signal).

The clock which is regenerated in the clock regenerating circuit must be agreed in phase with a demodulated signal level identifying timing (when the so-called eye-pattern is most opened). However, a change in trunk state due to temperature changes may cause a deviation in phase of a clock pulse.

Hence both a clock phase detecting circuit that can detect a phase deviation with high accuracy and a clock regenerating circuit that adjusts accurately a deviation in phase of the clock detected by the clock phase detecting circuit and then supplies signal identification clocks with high accuracy have been requested.

2) Description of the Related Art

FIG. 60 is a block diagram illustrating the configuration of a clock regenerating circuit arranged in the receiving unit of a general multiplex radio equipment. Referring to FIG. 60, numeral 71 represents an orthogonal detecting unit; 72 and 73 represent A/D converters; 74 represents a transversal equalizer; and 75 represents a clock regenerating circuit.

The orthogonal detecting unit 71 detects a signal (IF (intermediate frequency) signal) obtained by demodulating a multilevel orthogonal modulation signal due to PSK or QAM and then produces two kinds of baseband signals (an Ich signal and a Qch signal) with a different angle of 90° in phase from each other. As shown in FIG. 60, the orthogonal detecting unit 71 is formed of hybrids (H) 711 and 712, phase detectors 713 and 714, roll-off filters 715 and 716; and a local oscillating unit 717.

In the detecting unit 71, the hybrid 711 splits the IF signal input into two components and then sends respectively to the phase detectors 713 and 714. At this time, the local oscillating unit 717 supplies a carrier regenerating signal synchronized in phase with a carrier wave to the hybrid 712. The hybrid 712 splits the carrier regenerating signal into two signal waves with phases different from each other by 90°: one being output to the phase detector 713 and the other being output to the phase detector 714.

As a result, the phase detectors 713 and 714 receive base band signals (an Ich signal and a Qch signal) having phases different from each other by 90°. The A/D converter (identifying unit) 72 receives the Ich signal via the roll-off filter 715 to perform an A/C conversion (signal identification). The A/D converter (identifying unit) 73 receives the Qch signal via the roll-off filter 716 to perform an A/D conversion (signal identification). Thus digital demodulated signals with phases different from each other by 90° are obtained.

The A/D converter 72 converts the Ich signal from the orthogonal detecting unit 71 to a digital demodulated signal by A/D converting at a predetermined signal level. The A/D converter 73 converts the Qch signal from the orthogonal detecting unit 71 to a digital demodulated signal by A/D converting at a predetermined signal level. The transversal equalizer 74 equalizes each the digital demodulated signals from the A/D converters 72 and 73.

The clock regenerating circuit 75 regenerates A/D conversion clocks, of which the timing at which the 14
where “g” is the inclination of the Ich signal and “e” is a signal error of the Ich signal. Hence the multiplier 321 in the clock phase calculating unit 32 detects an A/D conversion clock phase shift “Δt” by multiplying the inclination “g” of the Ich signal by the signal error “e” of the Ich signal. Then the phase shift “Δt” can be supplied to the clock regenerating circuit 35 and then regenerated as an A/D conversion clock phase adjustment and control signal in the clock regenerating unit 29.

In the clock regenerating circuit 35, the IF signal to be detected by the orthogonal detecting unit 22 is processed desirably through the square detecting unit 291, the filter 292, and the PLL circuit 293 so that an A/D conversion timing signal is created to the A/D converters 23 and 24. The D/A converter 33 converts the phase shift “Δt” of an A/D conversion clock as described above from a digital signal to an analog signal and then the integrator 27 averages the analog signal. The phase shifter 28 receives the output of the integrator 27 as a phase adjustment and control signal to adjust the phase shift of the A/D conversion clock, thus sending it to the A/D converters 23 and 24.

Therefore, the A/D conversion clock to the A/D converters 23 and 24 to be regenerated in the clock regenerating circuit 35 can be always agreed to the optimum phase at which the opening portion of the eye pattern is opened maximumly. As a result, each of the A/D converters 23 and 24 can improve greatly the accuracy of the A/D conversion process.

As described above, the error detecting unit 31 detects the input signal to output signal error “e” of the transversal equalizer 25 while the inclination judging unit (signal inclination detecting unit) 30 detects the inclination “g” of the demodulated signal. Then the multiplier 321 in the clock phase calculating unit 32 multiplies the output of the error detecting unit 31 by the output of the inclination judging unit 30. Thus the phase shift (phase component) “Δt” of an A/D conversion clock can be obtained, whereby the phase shift of an A/D conversion clock can be surely detected.

Furthermore, the A/D conversion clock for the A/D converters (identifying units) 23 and 24 is obtained by means of the phase component detecting unit 26, the integrator 27, the phase shifter 28, and the clock regenerating unit 29 each used in common to the A/D converters (identifying units) 23 and 24. Hence in the receiving unit in the multiplex radio equipment wherein two kinds of orthogonal signals (an Ich signal and a Qch signal) are obtained by demodulating a multilevel orthogonal modulation signal such as 16 QAM, the phase shift of an A/D conversion clock can be detected and adjusted by a very-simplified configuration.

Since the integrator 27 can average the output (phase adjustment and control signal) of the phase component detecting unit 26, the accuracy of the phase adjustment and control signal to the phase shifter 28 can be increased, whereby the phase shifter 28 can perform accurately the phase adjusting process.

If the inclination “g” obtained by the inclination judging unit 30 and the signal error “e” obtained by the error detecting unit 31 are simply expressed only by polarity, the clock phase calculating unit 32 (refer to FIG. 8) may be formed of an EX-OR gate (exclusive OR element) 322 instead of the multiplier 321, as shown in FIG. 11. Hence the more simplified configuration can detect the phase shift (phase component) of an A/D conversion clock.

In the clock regenerating circuit 35, the phase component detecting unit 26 arranged on the Ich channel side detects the phase shift of an A/D conversion clock from the Ich signal. However, the phase component detecting unit 26 may be arranged on the Qch channel side to detect the phase shift of an A/D conversion clock based on the Qch signal. In the embodiments to be described later, the phase shift of an A/D conversion clock can be detected using either the Ich signal or Qch signal.

FIGS. 12 and 13 are block diagrams each illustrating another configuration of the clock regenerating circuit 35. In the clock regenerating circuit 35A shown in FIGS. 12 and 13, the clock regenerating unit 29 is used in common to identifying units (A/D converters) 23 and 24. The phase shifter 28A, the integrator 27A, and the phase component detecting unit 26A which correspond respectively to the phase shifter 28, the integrator 27, and the phase component detecting unit 26, described with FIGS. 7 and 9, are arranged to the identifying unit 23. The phase shifter 28B, the integrator 27B, and the phase component detecting unit 26B which correspond respectively to the phase shifter 28, the integrator 27, and the phase component detecting unit 26, described with FIGS. 7 and 9, are arranged to the identifying unit 24.

Each of the phase component detecting units 26A and 26B shown in FIG. 13 resembles structurally the phase component detecting unit 26A shown in FIG. 11. The clock phase calculating unit 32 is constituted as an EX-OR gate 322. The clock phase calculating unit 32 may be formed as the multiplier 321 shown in FIG. 7. In FIGS. 12 and 13, the same signs as those shown in FIGS. 7 and 9 represent same elements.

In the clock regenerating circuit 35A having the above-mentioned configuration, like the configuration shown in FIGS. 7 and 9, the phase component detecting unit 26A arranged corresponding to the channel (Ich) identifying unit 23 detects the phase shift of an A/D conversion clock based on an Ich signal while the phase component detecting unit 26B arranged corresponding to the channel (Qch) identifying unit 24 detects the phase shift of an A/D conversion clock based on a Qch signal. The integrator

In other words, where the phase of an A/D conversion clock shifts from the position of a signal point on the eye pattern in the above-mentioned process, bits lower than the signal bit (D1, D2) of a base band signal which is obtained by demodulating a multilevel orthogonal modulated signal called 16 QAM error bits (D3, D4, . . . ) shown in FIG. 45 increase as shown in FIG. 46. Hence the direction (phase shift Δt) in which the phase of an A/D conversion clock is adjusted is obtained by differentiating the curve between [phase error φ(t1), signal error e(t1)] at the time t1 and [phase error φ(t2), signal error e(t2)] at the time t2 on the clock phase to signal error curve shown in FIG. 46.

Thereafter the information (Δt) regarding the phase shift of an A/D conversion clock detected above is averaged by the integrator 27. Then the averaged information is supplied as a phase adjustment and control signal to the phase shifter 28 to adjust the phase shift of an A/D conversion clock regenerated by the clock regenerating unit 29.

Hence since the phase shifter 28 can adjust automatically and with higher accuracy the phase shift of an A/D conversion clock to the A/D converters 23 and 24, the accuracy of an A/D conversion process by the A/D converters 23 and 24 can be greatly improved.

The equalizer (transversal equalizer) 25 described in the first and second embodiments is arranged on the rear stage of each of the A/D converters 23 and 24, as shown in FIG. 44.

In the clock regenerating circuit 68 in this embodiment, if the phase differential information of the phase differential detecting unit 62 and the signal error information of the error differential detecting unit 63 are expressed only by polarities as described in the first embodiment, the clock phase calculating unit 64, as shown in FIGS. 47 and 48, can be formed as the EX-OR gate (exclusive OR element) 642 instead of the divider 641. Hence the phase shift (phase component) of an A/D conversion clock can be detected by a more-simplified configuration. In FIGS. 47 and 48, the same numerals as those in FIGS. 43 and 44 represent the same elements.

FIG. 49 is a block diagram illustrating another configuration of the clock regenerating circuit 68 shown in FIGS. 43 and 44. In the clock regenerating circuit 68A shown in FIG. 49, the clock regenerating unit 29 is arranged in common to the identifying units 23 and 24. Like the phase shifter 28, the integrator 27, and the phase component detecting unit 61 shown in FIGS. 43 and 44, the phase shifter 28A, the integrator 27A, and the phase component detecting unit 61A are arranged to the A/D converter 23 while the phase shifter 28B, the integrator 27B, and the phase component detecting unit 61B are arranged to the A/D converter 24.

In the clock regenerating circuit 68A shown in FIG. 49, as described with FIGS. 43 and 44, the phase component detecting unit 61A arranged to the identifying unit 23 detects the phase shift (phase component) of a signal identification clock (A/D conversion clock) to the identifying unit 23 based on phase difference information of a signal identification clock (A/D conversion clock) supplied to the identifying unit 23 and signal error differential information output from the identifying unit 23. The phase component detecting unit 61B arranged to the identifying unit 24 detects the phase shift (phase component) of a signal identification clock (A/D conversion clock) to the identifying unit 24 based on phase difference information of a signal identification clock (A/D conversion clock) supplied to the identifying unit 24 and signal error differential information output from the identifying unit 24.

The integrator 27A receives and averages information regarding the clock phase shift detected by the phase component detecting unit 61A. The integrator 27B receives and averages information regarding the clock phase shift detected by the phase component detecting unit 61B. Then each of the phase shifters 28A and 28B receives the averaged result as a phase adjustment and control signal to adjust the phase shift of a signal identification clock which is regenerated from the IF signal to be detected by the orthogonal detecting unit 22 by the clock regenerating unit 29 used in common to the identifying units 23 and 24.

Thus, the phase shifter 28A can adjust the clock phase shift to the identifying unit 23 and the phase shifter 28B can adjust the clock phase shift to the identifying unit 24. Hence the accuracy of the signal identifying process in the identifying units 23 and 24 can be greatly improved.

Like the first embodiment described with FIGS. 26 and 27, the clock regenerating circuit 68 (or 68A), as shown in FIG. 50, can include a PN pattern generating circuit (random pulse generating unit: a test signal generating unit) 47 and a selector (SEL: selecting unit) 46 to input the output of the SEL 46 to the phase shifter 28 via the integrator 27.

In this case, the PN pattern generating circuit 47 is formed of four flip-flop (FF) circuits 471 to 474 and an EX-OR gate 475. The PN pattern generating circuit 47 generates a test random pulse to set the phase shift of an A/D conversion clock by the phase component detecting unit 61 (or 61A, 61B) to the center value of a detection result. The SEL 46 outputs selectively the output of the phase component detecting unit 61 (or 61A, 61B) and the output of the PN pattern generating circuit 47 in response to a test/normal switching signal. In FIG. 49, the same numerals as those shown in FIG. 44 represent the same elements.

When the clock regenerating circuit 68 with the above-mentioned structure as shown in FIG. 50 is adjusted and tested, the adjustment signal is input to the SEL 46. Instead of the phase shift (phase component) of an A/D conversion clock to the A/D converters 23 and 24 to be detected by the phase component detecting unit 61 as described with FIGS. 43 to 46, the SEL 46 outputs selectively the random pulse (test signal) generated from the PN pattern generating circuit 47. Then the integrator 27 averages the selected output to supply the result as a phase adjustment and control signal for the phase shifter 28 to the phase shifter 28.

Hence the phase shifter 28 can adjust and test very easily the phase shift of an A/D conversion clock sent to the A/D converters 23 and 24.

(e) Fourth Embodiment of the Present Invention:

FIG. 51 is a block diagram illustrating the configuration of each of the clock phase detecting unit and the clock regenerating circuit arranged in multiplex radio equipment according to the fourth embodiment of the present invention. Referring to FIG. 51, numeral 22 represents an orthogonal detecting unit; 23 and 24 represent identifying units; and 61 represents a phase component detecting unit. These elements correspond to those shown in the third embodiment. Numeral 27′ represents an integrator and 28′ represents an oscillating unit. In this embodiment, the phase component detecting unit 61, the integrator 27′ and the oscillating unit 28′ provide the clock regenerating circuit 68′.

The orthogonal detecting unit 22, the identifying units 23 and 24, the integrator 27′ and the oscillating unit 28′ correspond to elements with the same numerals described in the second embodiment, respectively. The orthogonal detecting unit 22 outputs two kinds of signals including an Ich signal and a Qch signal which are different in phase (perpendicular to each other) by 90° from each other by detecting an IF band signal. As shown in FIG. 52, the orthogonal detecting unit 22 is formed of hybrid circuits (H) 221 and 222, phase detectors 223 and 224, roll-off filters 225 and 226, and a local oscillating unit 227. Each of the identifying units 23 and 24 is formed as an A/D converter that A/D-converts (identifies) the output of the orthogonal detecting unit 22 (a signal demodulated by the multilevel orthogonal modulation signal) at a predetermined level.

The integrator (loop filter unit) 27′ which integrates the output of the phase component detecting unit 61 (to be described later) is formed of a resistor (R) 271 and a capacitor (C) 272, as shown in FIG. 52. The resistor 271 and the capacitor 272 integrate the phase shift (phase component) information of an A/D conversion clock detected by the phase component detecting unit 61.

The oscillating unit (oscillating unit) 28′ receives the output of the integrator 27′ as a control input which adjusts the phase shift of an A/D conversion clock and then outputs a signal identification clock (A/D conversion clock) to the identifying units (A/D converters) 23 and 24.

The phase component detecting unit (clock phase detecting circuit (unit)) 61 detects the phase shift (phase component) of an A/D conversion clock in response to the phase difference information of an A/D conversion clock supplied to the A/D converters 23 and 24 and signal error differential information obtained by the A/D converter 23 and then supplies it to the integrator 27′ being a constituent element of the clock regenerating circuit 68′. The phase component detecting unit 61 is formed of a phase differential detecting unit 62, an error differential detecting unit 63, a clock phase calculating unit 64, flip-flop (FF) circuits 65 and 66.

The phase differential detecting unit 62 detects the phase difference information of an A/D conversion clock supplied to the A/D converters 23 and 24. The error differential detecting unit 63 detects the signal error differential information of an Ich signal obtained by the identifying unit 23. Each of the phase differential detecting unit 62 and the error differential detecting unit 63 is formed as a subtracter in this embodiment, as shown in FIG. 52. Each of the FF circuits 65 and 65′ delay its input signal by a predetermined amount and each of the FF circuits 66 and 66′ delay its input signal by a predetermined shift.

The clock phase calculating unit 64 calculates the output of the phase differential detecting unit 62 and the output of the error differential detecting unit 63 to detect the phase shift of an A/D conversion clock. In concrete, the clock phase calculating unit 64, which is formed of a divider (dividing unit) 641, subjects the output of the phase differential detecting unit 62 and the output of the error differential detecting unit 63 to a division process.

Referring to FIG. 52, numeral 67 represents a converting circuit that converts phase difference information of an A/D conversion clock supplied to the A/D converters 23 and 24 into a predetermined signal. The converting circuit 67 includes a counter 671 operating with high speed clocks (CLK). The amplifier 296 amplifies information regarding the phase shift of an A/D conversion clock detected by the phase component detecting unit 61 to a predetermined signal level. In this embodiment, the phase component detecting unit 61, the integrator 27, the phase shifter 28, and the clock regenerating unit 29 are used in common to the identifying units (A/D converters) 23 and 24.

In the clock regenerating circuit 68′ with the above-mentioned configuration, the converting circuit 67 converts the phase error of an A/D conversion clock to be supplied to the A/D converters 23 and 24 into a predetermined signal and then inputs the converted signal to the FF circuit 65′ in the phase component detecting unit 61. At the same time, the FF circuit 66′ receives the signal error (signal error information) of an Ich signal A/D converted by the A/D converter 23.

The FF circuits 65 and 65′ delays the converted signal by a predetermined shift to input to the subtracter 62. The FF circuits 66 and 66′ delays the signal error by a predetermined amount to input to the subtracter 63. Each of the subtracters 62 and 63 subjects its input to a subtraction process. The subtracter 62 obtains the phase difference information of an A/D conversion clock while the subtracter 63 obtains the signal error differential information of an Ich signal.

The divider 641 (clock phase calculating unit 64) 641 subjects the phase difference information and signal error differential information to an division process. As a result, the phase shift information of an A/D conversion clock can be obtained.

Thereafter, the phase shift information of the above-detected A/D conversion clock is not converted from the digital signal form to an analog signal form as described in the third embodiment, but integrated by the integrator 27′ as it is in a digital signal form. The result is amplified by the amplifier 296 to a predetermined signal level. Then the oscillating unit 28′ receives the amplified signal as a control signal to adjust the phase shift on an A/D conversion clock.

In other words, like the third embodiment, the clock regenerating circuit 68′ does not convert the phase shift information of an A/D conversion clock to the A/D converters 23 and 24 to be detected by the phase component detecting unit 61 from a digital signal to an analog signal to adjust the phase shift of an A/D conversion clock using the analog signal. Instead, the clock regenerating circuit 68′ outputs the phase shift information of an A/D conversion clock in a digital signal form as a control input to the oscillating unit 28′ and then adjusts the a/D conversion clock using the digital signal.

Consequently, even if the clock regenerating unit 29 and the phase shifter 28 are not arranged like the third embodiment, the very-simplified configuration can adjust automatically the phase shift of an A/D conversion clock to the A/D converters 23 and 24. Thus the A/D converters 23 and 24 can greatly improve the accuracy of an A/D conversion process.

In the clock phase calculating unit 64 in the phase component detecting unit 61 in this embodiment, if the phase differential information from the phase differential detecting unit 62 and the signal error information from the error differential detecting unit 63 are simply expressed with polarities, an EX-OR gate (exclusive OR element) 642, as shown in FIG. 53, can be arranged instead of the divider 641. The more-simplified configuration can detect the phase shift (phase component) of an A/D conversion clock. Other constituent elements correspond to those described with FIG. 52.

The clock regenerating circuit 68′, shown in FIGS. 52 and 53, can be constituted more simply by using the converting circuit 67′ formed as the A/D converter 672 as shown in FIG. 54, instead of the converting circuit 67.

Next, FIG. 55 is a block diagram showing another configuration of the clock regenerating circuit 68′ shown in FIGS. 51 to 54. The clock regenerating circuit 68A′ shown in FIG. 55 includes a composing unit 51A formed of a multiplier 511, in addition to the orthogonal detecting unit 22, the identifying units 23 and 24, the phase component detecting units (clock phase detecting units) 61A and 61B, the integrator (loop filter unit) 27′, and the oscillating unit 28′ corresponding to those shown in FIGS. 51 to 54.

In this case, the phase component detecting unit 61A is arranged corresponding to the A/D converter 23 and the phase component detecting unit 61B is arranged corresponding to the A/D converter 24. The oscillating unit 28′ and the integrator 27′ are used in common to the identifying units 23 and 24. The composing unit 51A is arranged to compose the output of the phase component detecting unit 61A with the output of the phase component detecting unit 61B. The output of the composing unit 51A is input to the integrator 27′.

In the clock regenerating circuits 68A′, the phase component detecting unit 61 corresponding to the A/D converter 23 detects the phase shift information of a signal identification clock for the A/D converter 23 and the phase component detecting unit 61 corresponding to the A/D converter 24 detects the phase shift information of a signal identification clock for the A/D converter 24. The multiplier 511 in the composing unit 51A multiplies the output from the phase component detecting unit 61A by the output of the phase component detecting unit 61B and then supplies the result as an input to the integrator 27′ and the oscillating unit 28′ used in common to the identifying units 61A and 61B.

Hence the phase shift of a signal identification clock supplied from the oscillating unit 28′ to the identifying units 23 and 24 can be adjusted independently and with higher accuracy to the identifying units 23 and 24. The composing unit 51A can be constituted in an analog circuit form or a digital circuit form. The detail configuration of each element is similar to that described with FIGS. 52 to 54. Hence the duplicate explanation will be omitted here.

FIG. 56 is a block diagram illustrating another configuration of the clock regenerating circuit 68′ shown in FIGS. 51 to 54. In the clock regenerating circuits 68′B shown in FIG. 56, the phase component detecting unit (clock phase detecting unit) 61A and the integrator (loop filter unit) 27A′ are arranged to the identifying unit 23, whereas the phase component detecting unit, the clock phase detecting unit 61B and the integrator (loop filter unit) 27B′ are arranged to the identifying unit 24. The oscillating unit (oscillating unit) 28B′ is used in common to the identifying units (A/D converters) 23 and 24. The identifying unit 23 is connected to the oscillating unit 28B′ via the phase shifter 28 similar to that described in the third embodiment. The output of the integrator 27A′ is supplied as a control input to the phase shifter 28 or the oscillating unit 28B′, whereas the output of the integrator 27B′ is supplied as a control input to the phase shifter 28 or the oscillating unit 28B′. Numeral 296 represents an amplifier which amplifies the phase shift information of a signal identification clock for the identifying units 23 and 24 detected by the phase component detecting unit 61B to a predetermined signal level.

In the clock regenerating circuit 68B′, like the third embodiment, the phase component detecting unit 61A detects information regarding the phase shift of a signal identification clock to the identifying unit 23 and the integrator 27A′ integrates the detected information. On the other hand, the phase component detecting unit 61B detects information regarding the phase shift of a signal identification clock to the identifying unit 24 and the integrator 27B′ integrates the detected information. Then the result is supplied as a control input to the phase shifter 28 or the oscillating unit 28B′.

The oscillating unit 28B′ adjusts automatically its oscillation frequency and the clock phase shift, based on information regarding the phase shift of a signal identification clock and supplies the result to the identifying unit 24. The phase shifter 28 adjusts the phase of a piece of the phase shift information supplied to the oscillating unit 28B′ and then supplies the result to the identifying unit 23.

As described above, according to the clock regenerating circuit 68A′, the phase component detecting unit 61A arranged corresponding to the identifying unit 23 detects the phase shift of a signal identification clock to the identifying unit 23 to supply the result as a control signal for the oscillator 28B′ or the phase shifter 28 to the oscillating unit 28B′ via the integrator 27A′ while the phase component detecting unit 61B arranged corresponding to the identifying unit 24 detects the phase shift of a signal identification clock to the identifying unit 24 to supply the result as a control signal for oscillator 28B′ or the phase shifter 28 to the oscillating unit 28B′ via the integrator 27B′. Hence the accuracy of the signal identifying process in the identifying units 23 and 24 can be further improved.

FIG. 57 is a block diagram illustrating another configuration of the clock regenerating circuit 68′ shown in FIGS. 51 to 54. The clock regenerating circuit 68C′ shown in FIG. 57 additionally includes another phase component detecting unit 52′. The integrator (loop filter unit) 27′ and the oscillating unit (oscillating unit) 28′, similar to those shown in FIGS. 51 to 54, are used in common to the identifying units 23 and 24. A composing unit 51B is arranged in the clock regenerating circuit 68° C.

Another phase component detecting unit (second clock phase detecting unit) 52′ is identical to another phase component detecting unit 52 shown in FIGS. 37 and 38 in the second embodiment. In this embodiment, information regarding the phase shift of a signal identification clock can be detected in a method different from that by the phase component detecting unit 61. The composing unit 51B composes the output of another phase component detecting unit 52′ with the output of the phase component detecting unit 52.

In such a manner, in the clock regenerating circuit 68C′, another phase component detecting unit 52 detects information regarding the phase shift of a signal information clock to the identifying units 23 and 24 in a method different from the phase component detecting unit 61. Then the multiplier 511 in the composing unit 51B multiplies (composes) the information regarding the signal identification clock by the information regarding the phase shift of a signal identification clock, based on the phase difference information and the signal error differential information detected by the phase component detecting unit 26 described in the third embodiment, and then supply the result to the integrator 27′.

The information regarding the phase shift of an A/D conversion clock (phase component information) can be output with higher accuracy to the oscillating unit 28′ which supplies signal identification clocks to the identifying units 23 and 24 via the integrator 27′. Hence the phase shift of a signal identification clock sent to the identifying units 23 and 24 can be adjusted automatically and with high accuracy so that the identifying units 23 and 24 can greatly improve the accuracy in the signal identifying (A/D conversion) process.

FIG. 58 is a block diagram illustrating another configuration of the clock regenerating circuit 68′ described with FIGS. 51 to 54. The clock regenerating circuit 68D′ shown in FIG. 58 includes another phase component detecting unit (second clock phase detecting unit) 52′ described with FIG. 57. The integrator (loop filter unit) 27′ and the oscillating unit (oscillating unit) 28′ similar to those shown in FIGS. 51 to 54 are used in common to the identifying units 23 and 24. The clock regenerating circuit 68D′ also includes a selecting unit 53′. The signal quality judging unit 54′ supplies a control signal to select the output from the selecting unit 53′. In concrete, the signal quality judging unit 54′ is formed as a frame synchronizing circuit that judges the signal quality through an error correction process as described with FIG. 40 and then outputs the frame synchronization signal as a control signal.

The selecting unit 53′ selectively outputs the output of the phase component detecting unit 61 and the output of another phase component detecting unit 52′ to the integrator 27′ according to the control signal (e.g. a frame synchronization signal) from the signal quality judging unit 54′.

In the clock regenerating circuit 68D′ with the above-mentioned configuration, another phase component detecting unit 52′ detects the phase shift of an A/D conversion clock to the A/D converters 23 and 24 in a method different from that of the phase component detecting unit 61. The selecting unit 53′ selectively inputs the information regarding the phase shift of an A/D conversion clock detected by another phase component detecting unit 52′ and the information regarding the phase shift of an A/D conversion clock detected by the phase component detecting unit 61 described in the first embodiment to the integrator 27′ according to the control signal from the signal quality judging unit 54′.

In this case, the information regarding the phase shift of an A/D conversion clock (phase component information) can be supplied with higher accuracy to the oscillating unit 28′ which supplies signal identification clocks to the identifying units 23 and 24 via the integrator 27′, the accuracy of the signal identification process in the identifying units 23 and 24 can be greatly improved by adjusting automatically and accurately the phase shift of a signal identification clock.

FIG. 59 is a block diagram illustrating another configuration of the clock regenerating circuit 68′ shown in FIGS. 51 to 54. The clock regenerating circuit 68E′ shown in FIG. 59 includes the selector (SEL: selecting unit) 46′ and the PN pattern generating circuit 47′, in addition to the phase component detecting unit 61, the oscillating unit 28′, the amplifier 296, and the integrator 27′ similar to those shown in FIG. 53. The selector 46′ corresponds to the selector (SEL) 46 shown in FIG. 49 in the third embodiment and the PN pattern generating circuit 47′ corresponds to the PN pattern generating circuit 47 shown in FIG. 49 in the third embodiment.

In brief, the clock regenerating circuit 68E′ is obtained by converting the clock regenerating circuit 68 in an analog circuit form described with FIG. 53 into a digital circuit form. In FIG. 59, the numerals as those shown in FIG. 50 represent like elements.

Thus the clock regenerating circuit 68E′ supplies selectively the test signal from the PN pattern generating circuit 47′ and the output from the phase component detecting unit 61 to the integrator (loop filter unit) 27′, according to a test (adjustment) / normal switching signal.

Therefore, the phase shift of an A/D conversion clock (signal identification clock) to the A/D converters (identifying units) 23 and 24 can be tested and adjusted very easily.

Claims

1. A clock phase detecting circuit arranged in a receiving unit of multiplex radio equipment, comprising:

an identifying circuit for identifying a signal at a predetermined identification level, said signal being obtained by demodulating a multilevel orthogonal modulated signal;

a clock regenerating circuit for regenerating a signal identification clock for said identifying circuit to supply said clock to said identifying circuit;

an equalizing circuit for subjecting said signal obtained by demodulating the multilevel orthogonal modulated signal to an equalizing process; and

a clock phase detecting unit for detecting a phase component of said signal identification clock based on errors between input and output signals of said equalizing circuit and then for supplying said phase component to said clock regenerating circuit;

wherein said clock phase detecting unit includes:

an error detecting unit for detecting a signal error between said input and output signals of said equalizing circuit: and

a clock phase calculating unit for detecting the phase component of said signal identification clock by calculating the detection outputs from said error detecting unit.

2. A clock phase detecting circuit arranged in a receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, comprising:

an identifying circuit for identifying a demodulated signal at a predetermined identification level, said demodulated signal being obtained by demodulating a multilevel orthogonal modulated signal;

a clock regenerating circuit for regenerating a signal identification clock for said identifying circuit to supply said signal identification clock to said identifying circuit;

an equalizing circuit for subjecting said demodulated signal obtained by demodulating the multilevel orthogonal modulated signal to an equalizing process; and

a clock phase detecting unit for detecting a phase component of said signal identification clock based on input and output signals of said equalizing circuit and then for supplying said phase component to said clock regenerating circuit;

wherein said clock phase detecting unit comprising:

an error detecting unit for detecting a signal error between said input and output signals of said equilizing equalizing circuit;

a signal inclination detecting unit for detecting the inclination of said demodulated signal; and

a clock phase calculating unit for operating the phase component of said signal identification clock by calculating based on respective outputs from said error detecting unit and said signal inclination detecting unit.

3. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 2, wherein said signal inclination detecting unit comprising:

a delaying unit for delaying the output from said identifying circuit; and

a comparing unit for comparing the output from said identifying circuit with the output from said delaying unit to detect the inclination of said demodulated signal.

4. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 2, wherein said identifying circuit is operated with high speed clocks; and wherein said signal inclination detecting unit comprising:

a delaying unit for delaying the output from said identifying circuit, said delaying unit being operated with said high speed clocks;

a latching unit for holding the output from said identifying circuit and the output from said delaying unit with clocks slower than said high speed clocks; and

a comparing unit for comparing the output of said identifying circuit held in said latching unit with the output from said delaying unit to detect the inclination of said demodulated signal.

5. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 2, wherein said identifying circuit comprises plural identifying units corresponding to the number of plural demodulated signals obtained by demodulating said multilevel orthogonal modulated signal; and wherein said signal inclination detecting unit includes a comparing unit that compares outputs of said plural identifying units with each other to detect the inclination of the demodulated signal when clocks with different predetermined phase shift between said plural identifying units are supplied to said plural identifying units.

6. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 2, wherein said clock phase calculating unit is formed as a multiplying unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to a multiplying calculating process.

7. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 2, wherein said clock phase calculating unit is formed as an exclusive OR calculating unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to an exclusive OR calculation process.

8. A clock phase detecting circuit arranged in a receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, comprising:

an identifying circuit for identifying a demodulated signal at a predetermined identification level, said demodulated signal being obtained by demodulating a multilevel orthogonal modulated signal;

a clock regenerating circuit for regenerating a signal identification clock for said identifying circuit to supply said signal identification clock to said identifying circuit;

an equalizing circuit for subjecting said demodulated signal obtained by demodulating the multilevel orthogonal modulated signal to an equalizing process; and

a clock phase detecting unit for detecting a phase component of said signal identification clock based on input and output signals of said equalizing circuit and then for supplying said phase component to said clock regenerating circuit;

wherein said clock phase detecting unit comprises:

an error detecting unit for detecting an the input signal to output signal error and output signals of said equilizing equalizing circuit;

a signal inclination detecting unit for detecting the inclination of said demodulated signal;

a clock phase calculating unit for detecting the phase component of said signal identification clock by calculating based on the respective outputs from said error detecting unit and said signal inclination detecting unit;

a specific signal judging unit for judging whether a specific signal exists; and

a gating unit for producting producing the phase component of said signal identification clock obtained by said clock phase calculating unit when said specific signal judging unit judges that said specific signal exists.

9. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 8, wherein said signal inclination detecting unit comprising:

a delaying unit for delaying the output from said identifying circuit; and

a comparing unit for comparing the output from said identifying circuit with the output from said delaying unit to detect the inclination of said demodulated signal.

10. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 8, wherein said identifying circuit is operated with high speed clocks; and wherein said signal inclination detecting unit comprising:

a delaying unit for delaying the output from said identifying circuit, said delaying unit being operated with said high speed clocks;

a latching unit for holding the output from said identifying circuit and the output from said delaying unit with clocks slower than said high speed clocks; and

a comparing unit for comparing the output of said identifying circuit held in said latching unit with the output from said delaying unit to detect the inclination of said demodulated signal.

11. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 8, wherein said identifying circuit comprises plural identifying units corresponding to the number of plural demodulated signals obtained by demodulating said multilevel orthogonal modulation signal; and wherein said signal inclination detecting unit includes a comparing unit that compares outputs of said plural identifying units with each other to detect the inclination of the demodulated signal when clocks with different predetermined phase amount between said plural identifying units are supplied to said plural identifying units.

12. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 8, wherein said clock phase calculating unit is formed as a multiplying unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to a multiplying calculating process.

13. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 8, wherein said clock phase calculating unit is formed as an exclusive OR calculating unit that subjects the output of said error detecting unit and the output of said signal inclination detecting unit to an exclusive OR calculation process.

14. The clock phase detecting circuit arranged in the receiving A receiver circuit arranged in a receiving unit of multiplex radio equipment, according to claim 8, wherein said specific signal judging unit includes plural signal judging units that judge plural kinds of specific signals, and further comprising a selecting unit arranged between said specific signal judging unit plural signal judging units and said gate gating unit, for selecting decision results from said plural signal judging units.