A semiconductor device with improved bond pads. The semiconductor device includes bond pads electrically connected to an active circuit in the device and openings formed in the bonding surface of the bond pads. The opening(s) may include recesses extending partially into the bonding surface or channels that extend entirely through the bond pads. Various shapes and configurations of the openings may be used, such as a pattern of channels radiating from the center of the bonding surface, a series of spaced apart rectangular channels arranged parallel to one another, an array of L shaped channels arranged around the center of the bonding surface, or an array of holes.
|
0. 17. An improved bond pad comprising:
a metal layer having a substantially planar surface, said metal layer electrically connected to an active circuit of a semiconductor device and having a plurality of openings extending partially into said metal layer,
wherein the openings comprise a pattern of radiating channels disposed about a center of the bond pad.
0. 1. A semiconductor device having an improved bond pad, the semiconductor device comprising:
a. a bond pad electrically connected to an active circuit in the semiconductor device;
b. a substantially flat bonding surface on the bond pad; and
c. an opening extending partially into the bonding surface.
0. 2. A semiconductor device according to
0. 3. A semiconductor device according to
4. A semiconductor device according to
a. a bond pad electrically connected to an active circuit in the semiconductor device;
b. a substantially flat bonding surface on the bond pad; and
c. a plurality of openings extending partially into the bonding surface and forming a pattern of radiating channels disposed about a center of the bonding surface.
0. 5. A semiconductor device according to
0. 6. A semiconductor device according to
0. 7. A semiconductor device according to
0. 8. A semiconductor device, which comprises:
a. an active circuit in the semiconductor device;
b. a wiring pattern overlying and in electrical contact with the active circuit;
c. bond pads formed as select areas on the wiring pattern; and
d. a plurality of openings extending partially into a substantially flat bonding surface of the bond pads.
0. 9. A semiconductor device according to
10. A semiconductor device according to
a. an active circuit in the semiconductor device;
b. a wiring pattern overlying and in electrical contact with the active circuit;
c. bond pads formed as select areas on the wiring pattern; and
d. a plurality of openings extending partially into a substantially flat bonding surface of the bond pads, wherein the openings comprise a pattern of radiating channels disposed about a center of the bonding surface.
0. 11. A semiconductor device according to
0. 12. A semiconductor device according to
0. 13. A semiconductor device according to
0. 14. A semiconductor device according to
0. 15. A semiconductor device according to
0. 16. A semiconductor device, comprising:
a. a layer of insulating material;
b. a substantially flat layer of conductive material overlying the layer of insulating material;
c. bond pads formed as select areas on a surface of the layer of conductive material; and
d. at least one opening extending partially into the bond pads.
|
The invention relates to semiconductor devices having bond pads for connection to an external circuit and, more particularly, to an improved bond pad having openings in the bonding surface of the bond pad.
Many semiconductor devices utilize bond pads as the terminals for electrically connecting active circuits in the device to an external circuit. The bond pads are select areas of the interconnect wiring pattern left exposed after formation of the passivation layer which covers the semiconductor die. The active circuits in the die are connected to the interconnect wiring and accessed through the bond pads. Thin wires are bonded to the bond pads. These bond wires electrically connect the bond pads to metal leads which, after the die/lead assembly has been enclosed within a sealed package, are inserted into or otherwise attached to a printed circuit board.
During the wire bonding process, a heat block heats the die and the leads to a temperature of about 150° C. to 350° C. The end of the bond wire is heated by an electrical discharge or a hydrogen torch to a molten state, thus forming a ball of molten metal on the end of the bond wire. The molten ball is pressed by a bonding capillary tool against the heated bond pad, sometimes in combination with ultrasonic vibration, to alloy the metallic elements of the wire and the metal bond pad and thereby bond the wire to the pad. The bonding capillary tool is then moved to a bonding site on the appropriate lead. The wire is pressed against the heated lead to bond the wire to the lead. The bond wire is then tensioned and sheared. The process is repeated for each bond pad on the die.
The bonding surface of conventional bond pads is substantially flat. The present invention is directed in general to an improved bond pad and, more specifically, to a bond pad having openings formed in the bonding surface of the bond pad. It is believed that forming openings in the bonding surface of the bond pad may, in some instances, improve the strength of the wire bond.
Accordingly, it is one object of the invention to improve the strength of the bond between the bond wire and the bond pad formed during the fabrication of semiconductor devices.
It is another object of the invention to increase the surface area of the bond pad without also increasing the size of the bond pad.
According to the present invention, these and other objects are achieved by a semiconductor device that includes a bond pad electrically connected to an active circuit in the semiconductor device and at least one opening formed in the bonding surface of the bond pad. The opening(s) may include recesses extending partially into the bonding surface or channels that extend entirely through the bond pad. Various shapes and configurations of the openings may be used and tailored to specific device requirements. For example, the openings may be a pattern of rectangular channels disposed about the center of the bonding surface or an array of holes.
Additional objects, advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention.
Preferably, openings 22 extend through bond pads 14, as shown in FIG. 1. Alternatively, openings 22 may be recesses that extend only partially into bonding surface 24, as shown in FIG. 3. Openings 22 comprise a series rectangular channels arranged parallel to one another as shown in FIG. 1. Other shapes and configurations may also be used and tailored to specific device requirements. For example, openings 22 may comprise a pattern of radiating channels disposed about the center of bonding surface 24 as illustrated in
The openings are believed to promote a more robust bond by increasing the surface area available for bonding, but without increasing the size of the bond pad. In addition, it is believed that the sidewalls of openings 22 collapse during the bonding process, thereby further increasing bond strength.
The formation of semiconductor device 10 will now be described with reference to
Referring now to
Referring to
There has been shown and described a semiconductor device having an improved bond pad wherein openings are formed in the bond pad to help create a more robust bond between the bond pad and an electrode. The particular embodiments shown in the drawings and described herein are for purposes of example and should not be construed to limit the invention as set forth in the appended claims.
Patent | Priority | Assignee | Title |
7964967, | Nov 23 2004 | ULTRATECH, INC | High surface area aluminum bond pad for through-wafer connections to an electronic package |
Patent | Priority | Assignee | Title |
5053850, | Mar 14 1988 | Motorola, Inc. | Bonding pad for semiconductor devices |
5248903, | Sep 18 1992 | Bell Semiconductor, LLC | Composite bond pads for semiconductor devices |
5373111, | Nov 19 1993 | Delphi Technologies Inc | Bond pad having a patterned bonding surface |
5703408, | Apr 10 1995 | ALPHA AND OMEGA SEMICONDUCTOR, LTD | Bonding pad structure and method thereof |
JP35553441, | |||
JP357039548, | |||
JP357040943, | |||
JP359035437, | |||
JP362001249, | |||
JP401179434, | |||
JP402180020, | |||
JP402187045, | |||
JP403153049, | |||
JP403242938, | |||
JP404074446, | |||
JP63161634, | |||
JP637135, |
Executed on | Assignor | Assignee | Conveyance | Frame | Reel | Doc |
Nov 11 1999 | Micron Technology, Inc. | (assignment on the face of the patent) | / | |||
Apr 26 2016 | Micron Technology, Inc | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | SECURITY INTEREST SEE DOCUMENT FOR DETAILS | 038669 | /0001 | |
Apr 26 2016 | Micron Technology, Inc | MORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENT | PATENT SECURITY AGREEMENT | 038954 | /0001 | |
Apr 26 2016 | Micron Technology, Inc | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001 ASSIGNOR S HEREBY CONFIRMS THE SECURITY INTEREST | 043079 | /0001 | |
Jun 29 2018 | U S BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT | Micron Technology, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 047243 | /0001 | |
Jul 31 2019 | MORGAN STANLEY SENIOR FUNDING, INC , AS COLLATERAL AGENT | Micron Technology, Inc | RELEASE BY SECURED PARTY SEE DOCUMENT FOR DETAILS | 050937 | /0001 |
Date | Maintenance Fee Events |
Jun 18 2009 | ASPN: Payor Number Assigned. |
Date | Maintenance Schedule |
Jul 07 2012 | 4 years fee payment window open |
Jan 07 2013 | 6 months grace period start (w surcharge) |
Jul 07 2013 | patent expiry (for year 4) |
Jul 07 2015 | 2 years to revive unintentionally abandoned end. (for year 4) |
Jul 07 2016 | 8 years fee payment window open |
Jan 07 2017 | 6 months grace period start (w surcharge) |
Jul 07 2017 | patent expiry (for year 8) |
Jul 07 2019 | 2 years to revive unintentionally abandoned end. (for year 8) |
Jul 07 2020 | 12 years fee payment window open |
Jan 07 2021 | 6 months grace period start (w surcharge) |
Jul 07 2021 | patent expiry (for year 12) |
Jul 07 2023 | 2 years to revive unintentionally abandoned end. (for year 12) |