Semiconductor chip with redistribution metal layer

Abstract

A new method is provided for the creation of Input/Output connection points to a semiconductor device package. An extension is applied to the conventional I/O connect points of a semiconductor device, allowing the original I/O point location to be relocated to a new point of I/O interconnect that may be in the vicinity of the original point of I/O interconnect but can also be located at a distance from this original point of I/O interconnect. layers of passivation and polyimide are provided for proper creation and protection of the extended and relocated I/O pads. wire bonding is used to further interconnect the relocated I/O pads.

Description

or , aluminum/copper alloys, Ti, Ta, W, or Mo, or a combination of these materials. This metal can be deposited by methods of electroplating, electroless plating, and the like. This cold metal deposition can for instance be a deposition of Al or copper at approximately 200 degrees C. Copper can further be deposited by electroplating or electroless-plating.

FIG. 5 shows a cross section of a re-routed I/O pad whereby the layer of polyimide, that is layer 36 of FIG. 4, has not been provided for protection of the relocated I/O pad 40. This can serve as an intermediary step and can result in cost savings or increased ease of manufacturing logistics in routing the chips through the manufacturing process. The preferred method of the invention to connect the relocated point 40 of I/O with surrounding circuitry is the use of bond wires (not shown in FIG. 5).

A number of salient points that relate to the process of the invention are the following:

• • in packaging semiconductor devices, the same package can be used for all devices that have an identical pattern of relocated I/O points of interconnect. By therefore customizing the creation of the relocated I/O pads to a particular semiconductor device, this device can now be mounted in a standardized package using the relocated I/O pads as points of interconnect,
  • the process of the invention uses a relatively thick layer of dielectric (layer 34, FIGS. 4 and 5) that overlays the original I/O pad and combines this relativity thick layer of dielectric with the used of relatively wide interconnect lines to create the relocated I/O pads. This approach allows for processes of the invention that can be performed using more cost effective processing equipment in addition to using a processing environment that needs to be less strictly environmentally controlled. Both of these factors make the process of the invention cost effective,
  • the process of the invention of I/O pad relocation can be performed after a passivation layer (layer 32 of FIGS. 4 and 5) has been deposited over the surface of the to be relocated I/O pad and before this layer of passivation is patterned for the contact opening to this I/O pad. The device can, because of this, remain in storage for a relatively long period of time, which provides for improved logistics control of the manufacturing process, and
  • the relocated I/O pads have been created on the surface of thick, soft material. Wirebonding operations to the relocated I/O pads can therefore be performed without incurring potential damage to underlying devices and structures.

It is clear from the above that the process of the invention in not limited to the examples that have been shown above. The process of the invention lends itself to using soft and thick layers of dielectric material while wide strips of metal can be used for purposes of re-routing the I/O pads. This rerouting enables the easy connection of the I/O pads to different format packages. In addition, the wire bonding pads can be located on the upper surface of a thick layer of material such as polyimide, thereby avoiding potential damage to underlying devices and structures during the process of wire bonding.

Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.

Claims

1. A method of I/O pad relocation that provides a universal I/O pad interface allowing use of a standardized package for packaging of semiconductor devices, the relocated I/O pads being created on the surface of a thick, soft dielectric material such as polyimide, whereby the relocated I/O pads are wide metal pads, comprising the steps of:

providing a semiconductor surface whereby said semiconductor surface has been provided with points of electrical contact therein;

creating a base layer of SiO₂ over said semiconductor surface;

depositing a first layer of conductive material over said semiconductor surface;

patterning and etching said first layer of conductive material, creating conductive pads that align with said points of electrical contact provided in said semiconductor surface, providing a conductive interface between said points of electrical contact provided in said semiconductor surface and said patterned and etched second layer of conductive material;

patterning and etching said base layer of SiO₂ as an extension of said patterning and etching said first layer of conductive material, using a pattern for this patterning of said base layer that is identical to a pattern used for etching said first layer of conductive material thereby removing said base layer from said semiconductor surface except where said base layer underlies said patterned first layer of conductive material;

attaching at least one bond wire to said conductive pads for further interconnects;

depositing a layer of passivation over said semiconductor surface, including said points of electrical contact;

patterning and etching said layer of passivation, creating openings in said layer of passivation to said points of electrical contact provided in said semiconductor surface;

depositing a first layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom over said layer of passivation, including said openings created in said layer of passivation;

patterning and etching said first layer of dielectric, creating openings in said first layer of dielectric that align with said openings in said layer of passivation;

depositing a second layer of conductive material over the surface of said first layer of dielectric, including said openings in said first layer of dielectric;

patterning and etching said second layer of conductive material, creating a pattern of conductive material that is wide and that serves as a bond pad; and

providing a wire bond connection to said bond pad for further interconnect.

2. The method of claim 1 wherein said first layer of dielectric is cured after said patterning and etching said first layer of dielectric.

3. The method of claim 1 wherein said second layer of conductive material comprises doped polysilicon.

4. The method of claim 1 wherein said second layer of conductive material comprises an element selected from a group comprising Al, Ti, Ta, W, Mo, Cu or a combination of these materials.

5. The method of claim 1 wherein said second layer of conductive material is selected from a group comprising silicate, a salicide, poly silicon, amorphous silicon or any other semiconductor compatible conductive layer.

6. The method of claim 1 with additional steps to be performed after said step of patterning and etching said second layer of conductive material, comprising:

depositing a second layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom over the surface of said first layer of dielectric, including said patterned second layer of conduction material;

patterning and etching said second layer of dielectric thereby creating openings that align with said patterned and etched second layer of conductive material, exposing the surface of said second layer of conductive material; and

providing a wire bond connection to said exposed surface of said second layer of conductive material for further interconnect.

7. The method of claim 6 wherein said second layer of dielectric is cured after said patterning and etching said first layer of dielectric.

8. The method of claim 1 wherein said patterning and etching said second layer of conductive material is creating a pattern of conductive material, said pattern of conductive material comprising conductive elements whereby each conductive element of said pattern of conductive material connects with at least one of said points of electrical contact provided in said semiconductor surface by means of at least one bond wire.

9. The method of claim 1 wherein said first layer of conductive material comprises doped polysilicon.

10. The method of claim 1 wherein said first layer of conductive material comprises an element selected from a group comprising Al, Ti, Ta, W, Mo, Cu or a combination of these materials.

11. The method of claim 1 wherein said first layer of conductive material is selected from a group comprising silicate, a salicide, poly silicon, amorphous silicon or any other semiconductor compatible conductive layer.

12. A method of I/O pad relocation that provides a universal I/O pad interface allowing use of a standardized package for packaging of semiconductor devices, the relocated I/O pads being created on the surface of a thick, soft dielectric material such as polyimide, whereby the relocated I/O pads are wide metal pads, said method comprising the steps of:

providing a semiconductor surface whereby said semiconductor surface has been provided with points of electrical contact therein;

creating base layer of SiO₂ over said semiconductor surface;

depositing a first layer of conductive material over said semiconductor surface;

patterning and etching said first layer of conductive material, creating a first pattern of conductive pads that align with said points of electrical contact provided in said semiconductor surface;

patterning and etching said base layer of SiO₂ as an extension of said patterning and etching said first layer of conductive material, using a pattern for this patterning of said base layer that is identical to a pattern used for etching said first layer of conductive material thereby removing said base layer from said semiconductor surface except where said base layer underlies said patterned first layer of conductive material;

depositing a layer of passivation over said semiconductor surface, including said first pattern of conductive pads;

patterning and etching said layer of passivation, creating openings to said first pattern of conductive pads;

depositing a first layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom over said layer of passivation, including said openings created in said layer of passivation;

patterning and etching said first layer of dielectric, creating openings in said first layer of dielectric that align with said openings in said layer of passivation;

depositing a second layer of conductive material over the surface of said first layer of dielectric, including said openings in said first layer of dielectric; and

patterning and etching said second layer of conductive material, creating a second pattern of conductive pads that align with said first pattern of conductive pads, creating a pattern of conductive material that is wide and that serves as bond pad;

providing at least one bond wire to said bond pad for further interconnect.

13. The method of claim 12 wherein said first layer of dielectric is cured after said patterning and etching said first layer of dielectric.

14. The method of claim 12 wherein said first or second layer of conductive material comprises doped polysilicon.

15. The method of claim 12 wherein said first or second layer of conductive material comprises an element selected from a group comprising Al, Ti, Ta, W, Mo, Cu or a combination of these materials.

16. The method of claim 12 wherein said first or second layer of conductive material is selected from a group comprising silicate, a salicide, poly silicon, amorphous silicon or any other semiconductor compatible conductive layer.

17. The method of claim 12 with additional steps to be performed after said step of patterning and etching said second layer of conductive material, comprising:

depositing a second layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom over the surface of said first layer of dielectric, including said patterned second layer of conductive material;

patterning and etching said second layer of dielectric thereby creating openings in said second layer of dielectric that align with said patterned and etched second layer of conductive material, exposing the surface of said second layer of conductive material; and

attaching at least one bond wire to said exposed surface of said conductive material for further interconnect.

18. The method of claim 17 wherein said second layer of dielectric is cured after said patterning and etching said first layer of dielectric.

19. The method of claim 12 wherein said patterning and etching said second layer of conductive material is creating a second pattern of conductive material, said second pattern of conductive material comprising conductive elements whereby at least one conductive element of said second pattern of conductive material connects with at least one of said points of electrical contact provided by said first pattern of conductive pads.

20. A structure for I/O pad relocation that provides a universal I/O pad interface allowing use of a standardized package for packaging of semiconductor devices, the relocated I/O pads being located on the surface of a thick, soft dielectric material such as polyimide, whereby the relocated I/O pads are wide metal pads, said structure comprising:

a semiconductor surface whereby said semiconductor surface has been provided with points of electrical contact therein;

a base layer of SiO₂ created over said semiconductor surface;

a patterned and etched first layer of conductive material deposited over said semiconductor surface;

conductive pads that align with said points of electrical contact provided in said semiconductor surface, created by patterning and etching said first layer of conductive material, providing a conductive interface between said points of electrical contact provided in said semiconductor surface and said patterned and etched second layer of conductive material;

said base layer of SiO₂ having been patterned and etched as an extension of said patterning and etching said first layer of conductive material, using a pattern for this patterning of said base layer that is identical to a pattern used for etching said first layer of conductive material thereby removing said base layer from said semiconductor surface except where said base layer underlies said patterned first layer of conductive material;

a layer of passivation deposited over said semiconductor surface, including said points of electrical contact;

openings in said layer of passivation to said points of electrical contact provided in said semiconductor surface, said openings created by patterning and etching said layer of passivation;

a first layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom deposited over said layer of passivation, including said openings created in said layer of passivation;

openings in said first layer of dielectric that align with said openings in said layer of passivation, created by patterning and etching said first layer of dielectric;

a second layer of conductive material deposited over the surface of said first layer of dielectric, including said openings in said first layer of dielectric;

a pattern of interconnect lines and contact pads created by patterning and etching said second layer of conductive material; and

at least one bond wire connected to said contact pads for further interconnect.

21. The structure of claim 20 wherein said first layer of dielectric is cured after said patterning and etching said first layer of dielectric.

22. The structure of claim 21 wherein said second layer of conductive material comprises doped polysilicon.

23. The structure of claim 20 wherein said second layer of conductive material comprises an element selected from a group comprising Al, Ti, Ta, W, Mo, Cu or a combination of these materials.

24. The structure of claim 20 wherein said second layer of conductive material is selected from a group comprising silicate, a salicide, poly silicon, amorphous silicon or any other semiconductor compatible conductive layer.

25. The structure of claim 20 with additional structures provided after said step of patterning and etching said second layer of conductive material, comprising:

a second layer of dielectric comprising polyimide or photosensitive polyimide deposited to a thickness between about 5,000 and 10,000 Angstrom deposited over the surface of said first layer of dielectric, including said patterned second layer of conductive material; and

openings that align with said patterned and etched second layer of conductive material, created by patterning and etching said second layer of dielectric, exposing the surface of said second layer of conductive material; and

at least one bond wire connected to said exposed surface of said second layer of conductive material.

26. The structure of claim 25 wherein said second layer of dielectric is cured after said patterning and etching said first layer of dielectric.

27. The structure of claim 20 wherein said patterning and etching said second layer of conductive material is creating a pattern of conductive material said pattern of conductive material comprising conductive elements whereby each conductive elements of said pattern of conductive material connects with at least one of said points of electrical contact provided in said semiconductor surface.

28. The structure of claim 20 wherein said first layer of conductive material comprises doped polysilicon.

29. The structure of claim 20 wherein said first layer of conductive material comprises an element selected from a group comprising Al, Ti, Ta, W, Mo, Cu or a combination of these materials.

30. The structure of claim 20 wherein said first layer of conductive material is selected from a group comprising silicate, a salicide, poly silicon, amorphous silicon or any other semiconductor compatible conductive layer.

31. A chip package comprising:

a semiconductor chip having a first edge and a second edge opposite to each other, comprising:

a passivation layer;

a first contact pad exposed by an opening in said passivation layer, wherein the minimum distance between said first edge and said first contact pad is small than that between said second edge and said first contact pad;

a second contact pad connected to a top surface of said first contact pad, wherein the minimum distance between said first edge and said second contact pad is greater than that between said second edge and said second contact pad;

a third contact pad; and

a wirebonded wire connecting said second and third contact pads across said second edge.

32. The chip package of claim 31, wherein said semiconductor chip comprises a polymer layer between said second contact pad and said passivation layer.

33. The chip package of claim 32, wherein said polymer layer comprises polyimide.

34. The chip package of claim 32, wherein said polymer layer is further on said top surface, an opening in said polymer layer exposing said top surface, and said second contact pad being connected to said top surface through said opening in said polymer layer.

35. The chip package of claim 32, wherein said polymer layer has a thickness of greater than 5 μm.

36. The chip package of claim 31, wherein said second contact pad comprises copper (Cu).

37. The chip package of claim 31, wherein said second contact pad comprises aluminum (Al).

38. The chip package of claim 31, wherein said second contact pad comprises an electroplated metal.

39. The chip package of claim 31, wherein said second contact pad comprises titanium (Ti).

40. The chip package of claim 31, wherein said semiconductor chip further comprises a polymer layer over said passivation layer, an opening in said polymer layer exposing said second contact pad.

41. The chip package of claim 40, wherein said polymer layer comprises polyimide.

42. The chip package of claim 31, wherein said passivation layer comprises a topmost inorganic insulating layer of said semiconductor chip.

43. The chip package of claim 31, wherein said passivation layer comprises a topmost nitride layer of said semiconductor chip.