A probe card which can help to enhance the productivity of semiconductor integrated circuits manufacturing and to reduce the manufacturing cost thereof, and a method of probe-testing semiconductor integrated circuits by using the probe card. The probe card is designed to test semiconductor integrated circuits formed on a semiconductor wafer and arranged in rows and columns. It has groups of probe needles provided to contact semiconductor integrated circuits arranged in two columns and at least two rows. The card receives a test signal from a test device and supplies the test signal simultaneously to these semiconductor integrated circuits arranged in two columns and at least tow rows, through the groups of probe needles. It receives response signals simultaneously from the semiconductor integrated circuits through the groups of probe needles and then supplies the response signals to the tester.
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0. 17. A method of testing semiconductor integrated circuit formed in a semiconductor wafer, the method comprising:
coupling a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;
concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
concurrently supplying a plurality of test signals and power supply voltages through the plurality of probe needles on the probe card to the external terminals on each of the plurality of semiconductor integrated circuit chips in at least two columns and at least two rows from the independent external tester;
concurrently receiving independent data output signals from each of the plurality of semiconductor integrated circuit chips in at least two columns and at least two rows by the independent external tester through the external terminals, the probe needles and the probe contacts; and
concurrently comparing electrical characteristics of the plurality of independent data output signals of each of plurality of semiconductor integrated circuit chips by the independent external tester.
0. 6. A method of testing semiconductor integrated circuit chips, the method comprising:
coupling each of a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and each of the plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;
concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and
concurrently comparing electrical characteristics of the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.
0. 12. A method of testing semiconductor integrated circuit chips, the method comprising:
coupling each of a plurality of probe contact terminals on at least one probe card to an independent external tester, the probe card having a plurality of probe needles and each of the plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows;
concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and
concurrently comparing electrical characteristics of the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.
0. 11. A method of testing semiconductor integrated circuit chips, the method comprising:
coupling a plurality of probe contact terminals on a probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips, the plurality of probe needles being arranged on the probe card in at least two columns and at least two rows, the plurality of probe needles corresponding to those of the plurality of external terminals;
concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and
concurrently comparing the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.
0. 16. A method of testing semiconductor integrated circuit chips, the method comprising:
coupling a plurality of probe contact terminals on at least one probe card to an independent external tester, the probe card having a plurality of probe needles and a plurality of probe contact terminals arranged thereon, wherein the probe contact terminals are direct connected to the probe needles by mechanical wirings;
preparing a semiconductor wafer having a plurality of semiconductor integrated circuit chips arranged thereon in at least two columns and at least two rows, each of the plurality of semiconductor integrated circuit chips having a plurality of external terminals;
coupling the plurality of probe needles on the probe card to the plurality of external terminals of each of the plurality of semiconductor integrated circuit chips, the plurality of probe needles being arranged on the probe card in at least two columns and at least two rows, the plurality of probe needles corresponding to those of the plurality of external terminals;
concurrently receiving a plurality of independent test signals and independent power supply for the probe card by each of the plurality of probe contact terminals from the independent external tester;
concurrently supplying the plurality of independent test signals and the independent power supply through the plurality of probe needles on the probe card to each of the plurality of semiconductor integrated circuit chips from the probe card;
concurrently receiving a plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips in response to the plurality of independent test signals and independent power supply through the plurality of probe needles on the probe card by the probe card;
concurrently receiving the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips through the plurality of probe contact terminals on the probe card by the independent external tester; and
concurrently comparing the plurality of independent data output signals of each of the plurality of semiconductor integrated circuit chips by the independent external tester.
0. 1. A probe card for use in probing test of semiconductor integrated circuits arranged on a semiconductor wafer in rows and columns, comprising:
a card substrate;
groups of probe needles, said groups arranged on said card substrate in two columns and at least two rows, to contact connection terminals of semiconductor integrated circuits which are arranged in two columns and at least two rows, and
groups of signal lines, each group of signal lines provided for one group of probe needles, each signal line provided for supplying a test signal from a tester to one probe needle and a response signal from the probe needle to the tester,
wherein a test signal supplied from said tester is supplied from said probe needles to the semiconductor integrated circuits arranged in two columns and at least two rows at the same time through said groups of probe needles, and response signals generated by the semiconductor integrated circuits arranged in two columns and at least two rows are simultaneously supplied to the tester through said groups of probe needles.
0. 2. The probe card according to
0. 3. The probe card according to
0. 4. The probe card according to
0. 5. The probe card according to
0. 7. The method according to
0. 8. The method according to
0. 9. The method according to
0. 10. The method according to
0. 13. The method according to
0. 14. The method according to
0. 15. The method according to
preparing at least one test station; and
attaching a plurality of probe cards to the at least one test station.
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fellows follows that the differences in resistance and capacitance among the wires is proportionally similar to the conventional card 5. Hence, the skew difference among the wires, which impairs the accuracy of probing test, disabling the tester to determine the true characteristic or ability of each chip tested is similar to the conventional card 5. Since the probe card 15 has a small diameter, it warps but very little, exerting but a very little stress on the wires provided on or in the substrate 20 and scarcely altering the electrical characteristics of the wires. In addition, since the wires are short, the crosstalk among the wires is small.
In view of these advantages, the probe card 15 can serve to enhance the productivity production of semiconductor integrated circuits and also to reduce the manufacturing cost of semiconductor integrated circuits.
When the probe card 15 was used, testing chips 3a to 3h arranged in four rows and two columns, six of the chips were found to be flawless, as can be seen from FIG. 5B. Only one of the chips was found to be defective, though it was actually flawless, as can be understood from FIG. 5B. It should be noted that the eight chips tested by using the probe card 15 were respectively identical in characteristics to those eight chips tested by using the conventional probe card 5′.
Namely, some of the flawless chips which were regarded as defective when tested by using the conventional probe card 5′ were correctly found to flawless when tested by using the probe card 15 according to the invention. In other words, the probe card 15 serves to test chips with high accuracy, thus saving flawless chips which would have been discarded as defective if the conventional probe card 5′ had been used. As a result, the probe card 15 serves to decrease the manufacturing cost of semiconductor integrated circuits.
A probe card 15 according to the second embodiment will be described, with reference to
As shown in
Thus the four groups 19a to 19d of probe needles to contact the chips 3a to 3d, groups 21a to 21d of probe contacts, and groups 37a to 37d of wires are arranged in the right half 33R of the substrate. The remaining four groups 19e to 19h of probe needles to contact the chips 3e to 3h, groups 21e to 21h of probe contacts, and groups 37e to 37h of wires are arranged in the right left half 33L of the substrate.
Arranged as shown in
Another probe card 15 according to the third embodiment of this invention will be described, with reference to
As illustrated in
Since the wires 37 of each type are provided on one layer, not together with the wires of any other type, the crosstalk among the wires 37 is far less than in the case all wires are arranged densely on one and the same layer. The probe card 15 according to the third embodiment can, therefore, help to achieve high-accuracy probing test. It has eight groups of probe needles and can serve to test eight chips at the same time.
The third embodiment can be used in combination with the probe card according to the second embodiment.
Methods of probe-testing semiconductor integrated circuits by using the probe card according to the invention will be described as the fourth, fifth and sixth embodiments.
As shown in
With this method, the more test stations are installed, the more chips can be tested at the same time with high accuracy. Namely, L×M chips can be tested at a time, where L is the number of chips that can be simultaneously tested by using one probe card, and M is the number of test stations installed.
In the instance shown in
As illustrated in
Still further, the number of chips tested simultaneously at one test station increases since two or more probe cards 15 are attached to one test station. Therefore, the facility cost for testing one chip is low. Having only one test station, the prober probing system shown in
As may be understood from
In the sixth embodiment, two test stations 43-1 and 43-2 are provided for one tester 41, and two probe cards are attached to each test station. To be more specific, probe cards 15-1 and 15-2 are attached to the first test station 43-1, and probe cards 15-3 and 15-4 to the second test station 43-2. Two semiconductor wafers 1—1 and 1-2 are simultaneously tested at the test stations 43-1 and 43-2, respectively, by using the four probe cards 15-1 to 15-4.
The probe-testing method according to the sixth embodiment can test L×M×N chips at the same time, where L is the number of chips one probe card can test at a time, M is the number of test station provided, and N is the number of probe cards attached to one test station. The sixth embodiment can serve to test many chips simultaneously with high accuracy as does the fourth embodiment, and can achieve good cost performance as does the fifth embodiment.
A semiconductor IC chips chip which can be easily tested by using a probe card which is according to the seventh embodiment of the invention will now be described.
Like the first to third embodiments, this probe card is designed to test IC chips arranged in two columns and at least two rows, at the same time, to determine whether the chips are flawless or defective. The probe card comprises a substrate having a rectangular through hole. It is desirable that some of the probe needles be arranged along one long side of the hole to contact the pads of the chips provided on a semiconductor wafer and forming one column and that the other probe needles be arranged along the other long side of the hole to contact the pads of chips provided on the wafer and forming a next column. If the probe needles are thus arranged, the wires provided on or in the substrate can be made shortest as has been explained in conjunction with the second embodiment.
A semiconductor IC chip should have pads arranged in a column to be tested by using the a probe card according to the invention, which has groups of probe needles arranged in the specific manner described above.
It is easy to bring the probe needles of one group 19 provided on the probe card into contact with the pads 31 because the pads 31 are arranged in a column. Even if identical chips on the semiconductor wafer are arranged in two columns as shown in
Alternatively, the pads 31 may be arranged in staggered fashion as is illustrated in FIG. 12.
A probe card 15 according to the eighth embodiment of this invention will be described, with reference to
As shown in
Designed to test chips arranged in eight rows, the probe card 15 inevitably have has a larger diameter D than the first embodiment (FIG. 3). Hence, it may have the same problems as does the conventional probe card 5′ (FIG. 2). Nevertheless, the eighth embodiment will be practically useful since the probe card technology is well expected to advance to simultaneously test 16 chips arranged in eight rows and two columns, with accuracy as high as in the case eight chips arranged in four rows and two columns are tested at the same time. Needless to say, the eighth embodiment has a smaller diameter than a conventional probe card which is designed to test 16 chips arranged in a single column. The eighth embodiment (
As can be understood from the eighth embodiment, the present invention is not limited to probe cards which are designed to test eight chips arranged in four rows and two columns. Rather, the invention can provide probe cards which serve to test more chips at a time, arranged in more rows and two columns.
A probe card according to the ninth embodiment of the present invention will be described, with reference to
As shown in
A probe card according to the tenth embodiment of the invention will be described, with reference to
In the probe cards 15 according to the invention, which are shown in
As has been described, the present invention can provide a probe card which can help to enhance the productivity of semiconductor integrated circuits and to reduce the manufacturing cost thereof, and can also provide a method of probe-testing semiconductor integrated circuits by using the probe card.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Patent | Priority | Assignee | Title |
11536770, | Sep 28 2018 | CHANGXIN MEMORY TECHNOLOGIES, INC.; CHANGXIN MEMORY TECHNOLOGIES, INC | Chip test method, apparatus, device, and system |
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