A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.

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Patent
   RE41187
Priority
Jun 11 2002
Filed
Mar 13 2008
Issued
Mar 30 2010
Expiry
Jan 24 2023
Inventors
Cooke, Lau…
Assg.orig
OC Applica…
Assg.curr
American P…
Entity
Large
Referenced by
0
References
22
Maint.:
EXPIRED
EXAMPLE 12
Procedure 3
SUMMARY
1. A method of testing an integrated circuit (ic) using test vectors containing a multiplicity of care inputs that are applied to at least one scan-chain of said ic, at least one said test vector containing a number of care inputs that is less than a total length of said test vector, wherein a last one of said care inputs occurs prior to a last position of said at least one test vector, each test vector having a corresponding predetermined expected test responses containing a multiplicity of care outputs, said method comprising, for each of said test vectors:
a. applying said test vector by applying serial data and clocking at least one said scan-chain only until all bits of said at least one said scan-chain that correspond to care inputs of said test vector have been set to values in accordance with said care inputs of said test vector;
b. operating said ic to capture at least one bit of a response of said ic to said test vector into at least one scan chain of said ic;
c. reading out at least some bits of said response of said ic to said test vector from said at least one scan-chain of said ic; and
d. comparing the read out bits of said response of said ic to said test vector to bits of said predetermined expected test response corresponding to said test vector to determine a pass or fail status corresponding to said test vector,
wherein said care output values are read out of a multiplicity of scan positions of said at least one scan-chain of said ic on successive clocks until all said care output values of said predetermined expected test response corresponding to said test vector in said at least one scan chain of said ic are read out.
8. A method of testing an integrated circuit (ic) using test vectors containing a multiplicity of care inputs that are applied to at least one scan-chain of said ic, each test vector having a corresponding predetermined expected test responses containing a multiplicity of care outputs, said method comprising, for each of said test vectors, the steps of:
applying said test vector by applying serial data and clocking at least one said scan chain only until all bits of said at least one said scan chain that correspond to care inputs of said test vector have been set to values in accordance with said care inputs of said test vector, wherein said step of applying serial data includes the step of inserting serial data into a multiplicity of scan positions within said at least one said scan-chain, and, wherein said step of inserting serial data into a multiplicity of scan positions is performed for each of said multiplicity of scan positions by applying a combination of a next bit value of said serial data and a present value of a scan bit previous to the scan position;
operating said ic to capture at least one bit of a response of said ic to said test vector into at least one scan chain of said ic;
reading out at least some bits of said response of said ic to said test vector from said at least one scan-chain of said ic; and
comparing the read out bits of said response of said ic to said test vector to bits of said predetermined expected test response corresponding to said test vector to determine a pass or fail status corresponding to said test vector, wherein at least one value of said care inputs for at least one of said test vectors is set by using at least one captured response to a prior test vector.
2. A method of testing an ic as in claim 1, wherein a function of at least a subset of said multiplicity of said scan positions is used to read out said care output values on each clock.
3. A method of testing an ic as in claim 2, wherein said function is comprised of at least one of one or more direct connections and check-sums.
4. A method of testing an ic as in claim 3, wherein said at least one of one or more direct connections and check-sums are connected to one or more multi-input-signature-registers.
5. A method of testing an ic as in claim 1, wherein the step of reading out at least some bits of said response of said ic to said test vector occurs until all values of said care outputs have been read, and wherein the step of reading out at least some bits of said response of said ic to said test vector also comprises simultaneously applying a subsequent test vector.
6. A method of testing an ic as in claim 5, wherein, in the case of more than one scan chain, each of said scan-chains is independently clocked until all of its said care-outputs from the predetermined expected test response corresponding to the current response of said ic to said test vector have been read out and all of its said care inputs for the subsequent test vector have been set in accordance with said subsequent test vector.
7. A method of testing an ic as in claim 6, wherein each scan-chain's clock is independently enabled and disabled by a function, wherein the function, for each scan-chain, comprises a combination of a common clock, a common enable and the values of each of the respective scan-chain's test vectors.
9. A method of testing an ic as in claim 8, wherein said step of applying a combination includes the step of applying an exclusive-OR function to said next bit value of said serial data and said present value of a scan bit position previous to the scan position.
10. A method of testing an ic as in claim 8, wherein, for the case in which there are multiple scan-chains, said ic includes a multiplicity of scan-chain clocks, and wherein the method further comprises the step of:
enabling each of said scan-chain clocks by changing a state of the inputs to each of said scan-chains.

Where the values are valid if not_valid=0.
Now as the new values shift into the first sub-string they are also Exclusive-Ored with the shifted bits from the previous pattern in all the subsequent sub-strings, so that given x0-x3 are the new shifted values, the values would be as shown in Table 9 below:

TABLE 9
x0 x1 x2 x3
x0is0 x1is1 x2is2 x3is3
x0is4 x1is5 x2is6 x3is7
x0is8 x1is9 x2isa x3isb

Where “|” is an Exclusive Or operation. Now x0 through x3 can be selected such that the Exclusive-Or operation of the new x value with the existing previous scan value must be equal to the required value. In other words, the x values must be as defined in Table 10 below:

TABLE 10
x0 = r0 x1 = r1 x2 = r2 x3 = r3
x0 = r4is0 x1 = r5is1 x2 = r6is2 x3 = r7is3
x0 = r8is4 x1 = r9is5 x2 = rais6 x3 = rbis7
x0 = rcis8 x1 = rdis9 x2 = reisa x3 = rfisb

But for all the required values in the first row, substitution of x0-x3 with r0-r3 can be made, so to determine if x0-x3 can be set to values to meet the test's required values, each column of expressions in Table 11 below must be true:

TABLE 11
r4 = r0is0 r5 = r1is1 r6 = r2is2 r7 = r3is3
r8 = r0is4 r9 = r1is5 ra = r2is6 rb = r3is7
rc = r0is8 rd = r1is9 re = r2isa rf = r3isb

As we shift new values beyond the first sub-string into the second sub-string, the values are as shown in Table 12 below:

TABLE 12
x0 x1 x2 x3
x4|x0 x5|x1 x6|x2 x7|x3
x4|x0is0 x5|x1is1 x6|x2is2 x7|x3is3
x4|x0is4 x5|x1is5 x6|x2is6 x7|x3is7

Now x0-x3 can be set to r0-r3, and x4-x7 can be substituted with r4-r7 so the remaining requirements reduce to the expressions in Table 13 below:

TABLE 13
r8 = r4is0 r9 = r5is1 ra = r6is2 rb = r7is3
rc = r4is4 rd = r5is5 re = r6is6 rf = r7is7

And, similarly for shifting values into three sub-strings, the expressions in Table 14 must be met:

TABLE 14
rc = r8is0 rd = r9is1 re = rais2 rf = rbis3

This process continues in this fashion until all required values are met.

Now given S(*,*) are the previous pattern's output values and R(*,*) are the required “care-input” values, the flowchart in FIG. 23 will find the number of shifts to meet the required values, step 2200 in the flowchart in FIG. 22.

It should be noted that the procedure represented in FIG. 23 does not produce a pattern, it merely determines the minimum number of shifts of a pattern to meet the required values. The specific new values to shift in are a function of the actual required values, which can be calculated in a manner similar but extended from this procedure. Furthermore, the flowchart in FIG. 23 does not take into consideration the number of shifts necessary to capture the required outputs, which was shown in Example 1e. This is easily added by initially shifting until all the faults in the fault lists on the outputs of the previous pattern have been shifted into tap points, and then beginning with that shift number other than zero.

The Flowchart in FIG. 24 is extended from the approach taken in FIG. 23 to produce the actual pattern. Again we start with the requirements in Table 8 and the operation in equation [1]. For each shift into the first sub-string, the shifted in “x” value must be determined by the first cell with a required bit in the column of the “x” value. The rest of the required bits in that column are checked against the assignment of the first value. For example the required “care inputs” were:

0**1 **10 0**0 **01

EXAMPLE 12

Then after shifting in 4 bits x0-x3 are assigned 0**1 and the values shifted in are:

TABLE 15
x0 x1 x2 x3
x0is4 x1is5 x2is6 x3is7
x0is8 x1is9 x2isa x3isb
x0isc x1isd x2ise x3isf

Which can be converted into the assignments shown in Table 16 below:

TABLE 16
x0 = r0 x1 = * x2 = r6is6 x3 = r3

The checking is then done by assigning the r values and verifying the following are true:

TABLE 17
1 = 1is6is6 0 = 1is7
0 = 0is8 0 = 1isb
0 = 1is6ise 0 = 1isf

This process continues through the second row as follows:
After shifting in 4 more bits, x4-x7 are assigned * *10 and the values shifted in are:

TABLE 18
x0 x1 x2 x3
x4|x0 x5|x1 x6|x2 x7|x3
x4|x0is8 x5|x1is9 x6|x2isa x7|x3isb
x4|x0isc x5|x1isd x6|x2ise x7|x3isf

Which can be converted into the assignments shown in Table 19 below:

TABLE 19
x0 = r0 x1 = * x2 = xr(is6 x3 = r3
x4 = r8is8|x0 x5 = * x6 = r6|x2 x7 = r7|x3

Where the value “(|s6)” only applies if s6 still exists (i.e., less than 7 shifts occurred). The checking is then done by assigning the r values and verifying the following are true:

TABLE 20
0 = 0is8|0|0|s8 0 = 0|1|1|sb
0 = 1|1|se 1 = 0|1|1|sf

This continues row by row until all created values have been verified good.

Considering the assignment of x2 occurs later than the first row because the first row does not contain a required value, code to assign the value to an x variable should begin from the highest row, reassigning it until no lower level required values exist. The flowchart to create the proper values is shown in FIG. 24.

In the flowchart in FIG. 24, the x values are calculated in the variable value and put back into S(*.*). The check variable is used to calculate the actual exclusive or values in the string to compare with the required “care input” values.

While the algorithm described in FIG. 24 produces correct results for designs with equal length sub-strings, if, as suggested in step 3) in procedure 1 or 4) of procedure 2 described above, some other technique is used, which results in sub-strings of unequal length the algorithm will not work. Under these conditions for each test do the following:

  • a) evaluate the variables in each of the “care input” locations and compare the resulting values to the corresponding “care input”. If they all match skip to step i).
  • b) move all output values to the next higher location in the string, i.e. Si→Si+1
  • c) insert a new variable xi in the first position of the output values and set it unknown
  • d) insert a new variable xj in the first position of each subsequent sub-string of the output values and set it to xi|existing contents
  • e) evaluate the variables in each of the “care input” locations and compare the resulting values to the corresponding “care input”. If they all match skip to step i).
  • f) set an unknown variable in equation at a “care input” location with the least unknowns to a state necessary to match the “care input” value.
  • g) Repeat steps e), f) and g) until no variables are left to set
  • h) increment the shift count and repeat steps b) through g).
  • i) output the values of the xi variables, if they are unknown set them to 0

Procedure 3

Procedure 3 above correctly evaluates the equations created by the shift and exclusive or operations in the scan string, regardless of the size of each sub-string, but may require more computation than the algorithm described in FIG. 24, which can preferably be used for strings with equal length sub-strings.

Multiple Scan Strings

A common technique in the industry to reduce the number of tester cycles needed to perform serial scan-in of the target device is to break the scan-strings into multiple scan-strings with separate scan-in and scan-outs as shown in FIG. 12. FIG. 12 shows a common clock signal line 1200, and all three scan strings 1201 are scanned in parallel. It is desirable to balance the parallel strings so they are of equal length. Scan In values for the shorter chains need to be padded with arbitrary values so that all strings finish scan-in simultaneously. A similar architecture can be used with the present invention as illustrated in FIG. 13. When multiple variable clocked strings exist within a design, it is advantageous to separate the scan clocking of the separate scan strings so they can be started and stopped individually. This is because the separate strings may require different numbers of shift cycles clocks in order to set up the next test pattern in them. Requiring all scan chains to start and stop shifting at the same time may increase the number of clock cycles needed to set up the test patterns simultaneously in all of the scan chains. This could be accomplished using separate clock lines 1300 as shown in FIG. 13, but this causes an increase in the number of clock pins needed.

In a preferred embodiment of the present invention, illustrated in FIG. 14, individual scan string clock lines 1400 are created from a single clock line 1401 by enabling 1402 it with a combination of a single control line 1403, readily available in most scan test methods, and the scan-in data lines 1405. FIG. 14 shows the clock enable control logic 1406 for each scan string represented as a black box. FIG. 15 shows an example design for the clock enable logic 1406. This logic consists of two memory elements 1500, 1501, clocked by opposite phases of a clock signal on the clock line 1401 and feedback logic which takes the scan in data on line 1405 and the common control signal on line 1403 to create a clock enable output signal on line 1504. Other combinations of logic may be created to serve the same purpose.

The control signal on line 1403 can come from a primary pin, from a Tap controller, or other suitable control logic, which issues the control signal value prior to the beginning of each scan sequence, and maintains that value throughout the scan operations. The control signal is set to the opposite value at any other time, such as to capture the test results or during normal system operation. As such, the control signal is readily available in most systems that implement scan where a SCAN_ENABLE signal may be used to select either serial scan or normal capture operation of the system flip-flops.

The clock enable control circuit 1406 shown in detail in FIG. 15, uses preferably a rising-edge clocked flip-flop 1500 and preferably a negative-edge clock enabled latch 1501 that operate on the common clock signal on line 1401. After initialization with the control signal on line 1403 set to logic “0”, the flip-flop 1500 is set to “1” and the latch 1501 is set to “1”. This allows the AND gates 1402 in FIG. 14 to pass clock pulses from lines 1401 through to scan clock lines 1400 and reach the scan-chains A, B and C. On the first rising-edge of clock pulse on line 1401, after the control signal on line 1403 becomes set to “1”, the Scan In signal on line 1405, which is gated by the positive polarity output from the flip-flop 1500 and the control signal line 1403, is loaded into flip-flop 1500. On the following falling-edge of clock pulse on line 1401 the value in the flip-flop 1500 is inverted through NAND gate 1504 and is transferred into latch 1501. Since the latch's positive polarity output forms an enable signal on line 1503 that controls the AND gates 1402 to pass or block clocks pulses on lines 1400 to the scan-chains. The scan-chain clocks are turned on if the Scan In lines 1405 have values set to “0”, and blocked otherwise. On the first clock cycle after enabling the control signal on line 1403, only the string(s) with the highest number of shift clocks required for setup of their test vectors shall have its (their) Scan In input set to “0”, so that the scan strings have their clock(s) enabled on the next clock cycle. All the other Scan In inputs are set to “1”, successively setting the Scan In inputs to “0” one cycle before their clocks need to be enabled. Once enabled, the clock(s) for the scan string(s) remain enabled even if the Scan In signal lines 1405 are set to “1”, until the first rising-edge of a clock pulse on line 1401 after the control signal on line 1403 has become de-asserted (i.e., set to “0”) again. In this manner, the Scan In signal on line 1403 for each scan-chain can be used to delay the starting of that chain's clocks by keeping the Scan In signal at logic “1”. This allows scan-chains that require smaller number of shift cycles to set up their test vectors to remain unaffected while the global scan clock signal on line 1401 is active, allowing other scan chains to start their shift operations. For each scan-chain, its Scan In signal line 1405 should be set to “0” on the cycle before its scan operations are to be started.

FIG. 16 shows signal waveform diagrams of the operations for the exemplary scan strings of FIGS. 14 and 15. The waveform 1603 represents the clock signals on the clock lines 1401; the waveform 1605 represents the signals on the control signal line 1403; the waveform 1606-1608 represent the data signals on the Data In lines 1405, for the scan chains A, B and C respectively. Below each Data In waveform 1606-1608 is a corresponding waveform for the enable control signal on the line 1503 from the corresponding clock enable control logic 1406. In the first clock cycle, labeled 0, and starting at the dotted line 1600, the control signal 1605 transitions low and the Scan In values 1606-1608 are set to their last clocked in values. This resets the set-reset logic, of the clock enable control 1406, which turns off all the clock enable signals on the falling edge of the clock signal 1605. In the next clock cycle 1, the start of which is denoted by the dotted line 1601, the Scan In data waveform 1606 for string A goes low, which sets its clock enable for the next clock cycle. Thereafter the Scan In data 1606 for string A is 10101010. In clock cycle 1 Scan In data waveform 1607 for string B and Scan In data waveform 1608 for string C are set to “1”, which insures that their clocks remain disabled. On clockcycle 2, the start of which is denoted by the dotted line 1602, the Scan In data waveform 1607 for string B goes low, enabling it's clock on the next cycle and thereafter scans in 0110010. Finally, on clock cycle 4, the start of which is denoted by the dotted line 1604, the Scan In data waveform 1608 for string C goes low, also enabling its clock and thereafter scans in the values 10010. After the front edge of the scan clock cycle 9, the start of which is denoted by the dotted line 1609, the control signal 1605 again goes low, after which all the Scan In values go to their test input state, to clock the scanned pattern on clock cycle 10, the start of which is denoted by the dotted line 1610. As many cycles of this non-scan state can occur as necessary before the next pattern begins. It should be noted that all signal waveforms 1605,1606,1607, and 1608 can transition anywhere within the clock cycle, but are shown in the second half of the clock cycle, which is typically where they would transition.

The described logic requires 1 additional clock cycle for the whole test set to prime the clock enable control logic 1406, and one additional clock cycle per test to enable the first scan string clock, but does not require separate scan clocks for the individual scan chains. It requires very little logic, it meets scan test design rules, and it is easily extended to as many strings as needed. A key is to enable the clock signals of each scan string separately and to successively enable, rather than successively disable the clock signals to get the desired bits scanned in. Furthermore, if the control logic 1406 is also scanned, it must be done on separate scan strings from the scan strings it controls.

Pseudo Random Patterns

In yet another embodiment, as shown in FIG. 17, a Pseudo Random Pattern Generator (PRPG) 1700 may be added in front of the multiple variable clocked scan strings to generate random patterns. While this does not reduce the test time, it can significantly reduce the volume of the test data required to test the integrated circuit. An example of a PRPG, controlled by an Rpon signal on line 1701 can be seen in more detail in FIG. 18. The unique feature of this PRPG is the use of the clock enable signals on lines 1800 to select between the scan data inputs on lines 1801 and the random patterns, if the Rpon signal on line 1701 is set high. When the Rpon signal on line 1701 is low, the scan data input lines 1801 are always selected. When the Rpon signal is high the enable signals on lines 1800 from the clock enable control logic 1406 in FIG. 14, select the scan data input signals on lines 1801 which in-turn keep the enable signals on lines 1800 low until each scan data input on the lines 1405 transition low, as was described with respect to FIG. 16.

Notwithstanding the embodiments and methods above, it is contemplated that the present invention may be used with any or all of the existing scan based methods and test techniques, including scan test compression, BIST, hierarchical scan structures, and any other traditional scan techniques either referred to in this patent, and other patents or papers readily available to the industry. In all such cases it is expected that the testing time would be reduced, by the addition of these techniques.

SUMMARY

Using existing scan test design, and by inserting Exclusive-Or gates periodically within the scan strings such that the scanned data is Exclusive-Ored with a selection of the input data, shift clocking need only proceed until the required inputs match the shifted values. Frequent taps from the scan strings into check-sums and/or signature registers serve to limit the required number of shifts necessary to capture the required “care output” values. These combined techniques significantly reduce the required number of shift clocks per pattern as compared to shift clocks required in prior art scan test techniques, thus significantly reducing the test time.

Further test time reductions obtained by breaking the scan strings into multiple commonly clocked scan strings with separate inputs. Variable scan clocking can be performed by including described scan clock control logic which enables scanning on each string to match each strings clocking requirements, without the need for additional pins.

INVENTORS:

Cooke, Laurence H.

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