Method and system for displaying an analog image by a digital display device

Abstract

A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

Description

RELATED APPLICATIONS

The present application is related to co-pending U.S. Patent Application entitled, “A Method and Apparatus for Upscaling an Image”, Filed Concurrently with the present application, Serial Number UNASSIGNED, Attorney Docket Number: PRDN-0001, and is incorporated in its entirety herewith.

The present application is also related to and is a continuation of application Ser. No. 08/803,824 filed Feb. 24, 1997, now U.S. Pat. No. 5,796,392, entitled “Method and Apparatus for Clock Recovery in a Digital Display Unit.”

where Trclk represents the clock period of reference clock and Th represents the horizontal period (time between two successive Hsync pulses).
Pnom=era_htotal*Qdto/Hor_Rcount   (2)
Here, Qdto is DTO module, (i.e., 2**n, where n is the number of bits in DTO). It should be noted that Pnom isn't dependent on locking scheme. That is, the clock signal can be locked on HSYNC, VSYNC, or the like.

Positive slope (Charging) parameter for phase correction loop is derived from Pnom. It is also independent of the locking scheme. Kpdp controls damping of phase correction loop. For optimal tracking it may be set to 3 or 3.
Pdpd=Pnom/Kpdp   (3)

Negative slope parameter (discharging) is derived from Ppdp. NPDP is usually close to Ppdp if loop is unlocked and several times smaller (8 . . . 16) if loop is locked (to minimize phase jumps).
Npdp=Ppdp/Knpdp   (4)
Knpdp=2 . . . 16

Frequency correction parameter is dependent on locking scheme. It means amount of frequency adjustment per one Rclk phase tracking error.

If the FBACK signal is locked on HSYNC pulses as a time reference
Fdp=Pnom/(Kfdp*Vdiv*Hor_Rcount)   (5a)

If FBACK signal is locked in Vsync pulses as a time reference
Fdp=Pnom/(Kfdp*Vtotal*Hor_Rcount)   (5b)

Here Vdiv is vertical Hsync divider (1 . . . n). If Vdiv is 1, every Hsync is used for comparison. If Vdiv is 2, every other Hsync is used, etc. Vtotal is number of lines in the source frame if VSYNC locking is used.

7. Analog Filter 320

As noted above, analog filter 320 is designed to preserve the fundamental frequency generated by DTO while eliminating the other frequencies. Analog filter 320 can be implemented using active or passive filters or using a phase-locked loop as is well-known in the art. An example embodiment of analog filter 320 is illustrated with reference to FIG. 5.

Analog filter 320 is conventional and includes a DAC reconstruction filter 510. Schmidt trigger 520 slices the sine-wave in a known way to convert the sine-wave into digital signal (two level quantization). The PLL loop comprising PFD 530, charge pump 540, loop filter 550, VCO 560, and divider 580 is designed to eliminate all the undesirable frequencies, while preserving the fundamental frequency. The value of N in divider 580 is kept relatively small (at or below 8). VCO 560 may be designed to generate sampling clock signal, which can be used to sample the analog signal data. Dividers 570 and 580 may be used to shift the Vco frequency into the operating range of Vco 560.

Thus, the output of analog filter 320 includes filtered signal with well-suppressed spurious spectral components.

16. Conclusion

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A circuit for use in a digital display unit of a computer system, and circuit for generating a plurality of pixel data elements from an analog image data received by said digital display unit, said digital display unit further receiving a time reference signal associated with said analog image data, said time reference signal having a high frequency, said circuit comprising:

an analog-to-digital converter (ADC) for receiving said analog image data, said ADC sampling said analog image data using a sampling clock to generate a plurality of pixel data elements corresponding to said plurality of pixels, wherein said sampling clock has a sampling frequency equal to said high frequency;

a clock generator circuit comprising a phase-locked loop (PLL) circuit for generating said sampling clock, wherein said sampling clock is synchronized with said time reference signal with a jitter of less than a few nano-seconds, said PLL comprising:

a discrete time oscillator (DTO) for receiving a digital input and generating a signal representative of said sampling clock with a frequency determined by said digital input; and

a digital circuit for receiving said time reference signal and a feedback signal, wherein said feedback signal is generated by dividing said sampling clock, said digital circuit generating said digital input according to the difference of the phases of said time reference signal and said feedback signal, said digital input causing said DTO to generate said signal synchronized with said time reference signal, said digital circuit comprising:

a frequency correction logic for adjusting the phase of said sampling clock according to the long-term drifts in the frequency of said time reference signal; and

a phase correction logic for adjusting the phase of said sampling clock according to the phase difference in said feedback signal and said time reference signal,

wherein said frequency correction logic and said phase correction logic are implemented as two separate control loops,

wherein a panel interface included in said digital display unit can generate display signals for a display screen based on said plurality of pixel data elements.

2. The circuit of claim 1, wherein said clock generator circuit further comprises an analog filter to eliminate any undesirable frequencies from said signal representative of said sampling clock to generate said sampling clock.

3. The circuit of claim 1, further comprising a phase and frequency detector for determining the difference of phase between said feedback signal and said time reference signal.

4. The circuit of claim 3, further comprising a charge/discharge control logic for determining the amount of phase correction to be made based on the determination of said difference of phase.

5. The circuit of claim 1, wherein said analog image data and said time reference signal are received on two separate signal paths.

6. The circuit of claim 5, wherein said reference clock comprises a binary signal.

7. The circuit of claim 1, wherein said digital circuit distributes phase error between said feedback signal and said reference signal during a comparison cycle by changing the phase of individual clock pulses in said sampling clock.

8. The circuit of claim 1, wherein said frequency correction logic generates a multi-bit number, wherein said multi-bit number is representative of the amount of phase advance of said sampling clock generated by said DTO during a DTO clock period, and wherein said multi-bit representation enables said PLL to reach said sampling frequency within a short duration.

9. The circuit of claim 1, wherein said frequency correction logic comprises:

a first multiplexor accepting as input Pnom and Fdp values, wherein Pnom represents an expected frequency of said sampling clock and Fdp represents the correction due to the long-term frequency drifts;

a flip-flop for storing a value representative of the phase correction corresponding to the frequency correction logic;

an adder for adding or subtracting the output of said first multiplexor from the value stored in said flip-flop, wherein the output of said adder is stored in said flip-flop; and

a frequency correction control coupled to said flip-flop and said adder, wherein said frequency correction control causes said flip-flop to be set to Pnom at the beginning of a phase acquisition phase, and wherein said frequency correction control causes said adder to add or subtract Fdp depending on whether the sampling clock is early or late in comparison to said time reference.

10. The circuit of claim 1, further comprising:

a phase and frequency detector for determining the difference of phase between said feedback signal and said time reference signal, wherein said phase and frequency detector asserts an EARLY signal a number of clock pulses proportionate to the difference of phase by which said feedback signal is earlier than said time reference signal and a or a LATE signal a number of pulses proportionate to the difference of phase by which said feedback signal is later than said time reference signal; and

a charge/discharge control logic implemented using digital components, said charge/discharge control logic including a phase integrator, said charge/discharge control logic charging said phase integrator according to the number of pulses said EARLY signal or said LATE signal is asserted, said charge/discharge logic discharging over a longer period of time than the charging period so as to spread the difference in phase over a comparison cycle, wherein the phase of said sampling clock is corrected during the discharging period.

11. The circuit of claim 10, further comprising a sign and zero crossing detector for correcting any over-correction performed by said charge/discharge logic during said discharging period.

12. A memory efficient display controller for upscaling a source image at a first resolution to a destination image at a second resolution, comprising:

an interface arranged to receive source image pixel data in accordance with a first clock;

a line buffer having a size in accordance with a first resolution scan line length arranged to receive the source image pixel data at the first clock and store the received source image pixel data therein; and

an interpolator coupled to the line buffer and arranged to form the destination image using selected stored source image pixel data read from said line buffer in accordance with a second clock.

13. A display controller as recited in claim 12, wherein said interpolator comprises:

a vertical interpolator unit arranged convert a first resolution number of scan lines to a second resolution number of scan lines; and

a horizontal interpolator unit coupled to the vertical interpolator unit arranged to convert each of the second resolution number of scan lines each having the first resolution scan line length to a second resolution scan line length.

14. A display controller as recited in claim 13, wherein the interpolator further comprises:

a second line buffer coupled to the vertical interpolator and the line buffer for storing only a previous scan line.

15. A display controller as recited in claim 14, further comprising:

a third line buffer for storing a current scan line used with the previous scan line by the vertical interpolator to convert the first resolution number of scan lines to the second resolution number of scan lines.

16. A display controller as recited in claim 13, wherein the line buffer is a single port memory type line buffer or wherein the line buffer is a dual ported memory type line buffer.

17. A display controller as recited in claim 16, wherein when the line buffer is the single port SDRAM, then the line buffer further comprises a first bank and a second bank each having a size in accordance with the first resolution scan line length.

18. A display controller as recited in claim 17, wherein when pixel data corresponding to a source image scan line is received in the first bank, then pixel data corresponding to another source image scan line can be concurrently read from the second bank as many times as required.

19. A display controller as recited in claim 16, wherein when said line buffer comprises the dual-ported memory, the data is read from a port that is different from a port that receives the source image pixel data.

20. A display controller as recited in claim 12, wherein the second clock is locked to said first clock in a proportion.

21. A display controller as recited in claim 20, wherein the proportion is equal to (Htotal.sub.−src.time.Vtotal.sub.−src)/(Htotal.sub.−dst.times.Vtotal.sub.−dst), wherein Htotal.sub.−src and Htotal.sub.−dst represent the total number of pixels in each source scan line and each destination scan line respectively, and Vtotal.sub.−src and Vtotal-sub.−dst represent the total number of lines in the source image and the destination image, respectively.

22. The display controller of claim 21, wherein the source image pixel data is received using an externally generated first clock that is locked to said first clock.

23. The display controller of claim 12, wherein said source image has a source image aspect ratio and said destination image has a destination image aspect ratio that can be not equal to said source aspect ratio.

24. The display controller of claim 12, wherein when said source image is an analog source image then the first clock is provided to a sampling circuit coupled to the interface that samples the analog source image at a sampling frequency such that each scan line in said source image is sampled a number of times equal to a number of pixels in each scan line in the destination image.

25. A display controller as recited in claim 12, wherein an overrun condition in the line buffer is avoided by commencing writing the source image pixel data in a particular portion of the line buffer after the reading of the stored pixel data has commenced in that same portion of the line buffer.

26. A display controller as recited in claim 12 further comprising:

an incomplete interpolated scan line suppressor unit coupled to the interpolator unit arranged to suppress a last incomplete scan line after the horizontal interpolation based upon a truncated vertical scaling factor (VSF).

27. A display controller as recited in claim 26, wherein the truncated VSF is derived by truncating a fractional portion of VSF where VSF is equal to the ratio Vsize.sub.−src/Vsize.sub.−dst.

28. The display controller of claim 12, wherein said display controller is coupled to a display unit.

29. A display controller as recited in claim 28, wherein said display unit comprises an fixed array monitor selected from a group comprising: an LCD monitor and a plasma monitor.

30. A display controller as recited in claim 29, wherein display unit is part of a television system.

31. A display controller as recited in claim 12, wherein the first resolution corresponds to VGA and wherein the second resolution corresponds to a resolution selected from a group comprising: XGA, SXGA, UXGA, WQSXGA, and QSXGA.

32. A display controller as recited in claim 12, wherein the display controller is formed as a single integrated circuit.

33. A memory efficient method for upscaling a source image at a first resolution to a destination image at a second resolution, comprising:

receiving source image pixel data in accordance with a first clock;

receiving the source image pixel data a line buffer having a size in accordance with the first resolution at the first clock;

storing the received source image pixel data in the line buffer;

reading selected stored image pixel data from the line buffer at a second clock; and

forming the destination image using the selected stored source image pixel data.

34. A method as recited in claim 33, wherein the forming the destination image comprises:

converting a first resolution number of scan lines to a second resolution number of scan lines; and

converting each of the second resolution number of scan lines each having a first resolution scan line length to a second resolution scan line length.

35. A method as recited in claim 34, wherein the converting the first resolution number of scan lines to the second resolution number of scan line is based upon using a current scan line and a previous scan line.

36. A method as recited in claim 33, wherein the line buffer is a single port memory type line buffer or wherein the line buffer is a dual ported memory type line buffer.

37. A method as recited in claim 36, wherein when the line buffer is the single port SDRAM, then the line buffer further comprises a first bank and a second bank each having a size in accordance with the first resolution scan line length.

38. A method as recited in claim 37, wherein when the pixel data corresponding to a source image scan line is received in the first bank, then pixel data corresponding to another source image scan line can be concurrently read from the second bank as many times as required.

39. A method as recited in claim 36, wherein when said line buffer comprises the dual-ported memory, the data is read from a port that is different from a port that receives the source image pixel data.

40. A method as recited in claim 33, further comprising:

locking the second clock to the first clock in a proportion.

41. A method as recited in claim 40, wherein the proportion is equal to (Htotal.sub.−src.times.Vtotal.sub.−src)/(Htotal.sub.−dst.times.Vtotal.sub.−dst), wherein Htotal.sub.−src and Htotal.sub.−dst represent the total number of pixels in each source scan line and each destination scan line respectively, and Vtotal.sub.−src and Vtotal.sub.−dst represent the total number of lines in the source image and the destination image, respectively.

42. A method as recited in claim 33, wherein the source image pixel data is received using an externally generated first clock.

43. A method as recited in claim 33, wherein said source image has a source image aspect ratio and said destination image has a destination image aspect ratio that can be not equal to said source aspect ratio.

44. A method as recited in claim 33, wherein when said source image is an analog source image then the first clock is provided to a sampling circuit coupled to the interface that samples the analog source image at a sampling frequency such that each scan line in said source image is sampled a number of times equal to a number of pixels in each scan line in the destination image.

45. A method as recited in claim 33, further comprising:

commencing writing the source image pixel data in a particular portion of the line buffer after the reading of the stored pixel data has commenced in that same portion of the line buffer thereby avoiding an overrun condition in the line buffer.

46. A method as recited in claim 34 further comprising:

suppressing a last incomplete scan line based upon a truncated vertical scaling factor (VSF).

47. A method as recited in claim 46, wherein the truncated VSF is derived by truncating a fractional portion of VSF where VSF is equal to the ratio Vsize.sub.−src/Vsize.sub.−dst.

48. A method as recited in claim 33, wherein said display controller is coupled to a display unit.

49. A method as recited in claim 48, wherein the display unit comprises an fixed array monitor selected from a group comprising: an LCD monitor and a plasma monitor.

50. A method as recited in claim 49, wherein the display unit is part of a television system.

51. A method as recited in claim 33, wherein the first resolution corresponds to VGA and wherein the second resolution corresponds to a resolution selected from a group comprising: XGA, SXGA, UXGA, WQSXGA, and QSXGA.

52. A method as recited in claim 33, wherein the display controller is formed as a single integrated circuit.

53. Computer program product for memory efficient upscaling of a source image at a first resolution to a destination image at a second resolution, comprising:

computer code for receiving source image pixel data in accordance with a first clock;

computer code for receiving the source image pixel data a line buffer having a size in accordance with the first resolution at the first clock;

computer code for storing the received source image pixel data in the line buffer;

computer code for reading selected stored image pixel data from the line buffer at a second clock;

computer code for forming the destination image using the selected stored source image pixel data; and

computer readable medium for storing the computer code.

54. Computer program product as recited in claim 53, wherein the forming the destination image comprises:

computer code for converting a first resolution number of scan lines to a second resolution number of scan lines; and

computer code for converting each of the second resolution number of scan lines each having a first resolution scan line length to a second resolution scan line length.

55. Computer program product as recited in claim 54, wherein the converting the first resolution number of scan lines to the second resolution number of scan line is based upon using a current scan line and a previous scan line.

56. Computer program product as recited in claim 53, wherein the line buffer is a single port memory type line buffer or wherein the line buffer is a dual ported memory type line buffer.

57. Computer program product as recited in claim 56, wherein when the line buffer is the single port SDRAM, then the line buffer further comprises a first bank and a second bank each having a size in accordance with the first resolution scan line length.

58. Computer program product as recited in claim 57, wherein when pixel data corresponding to a source image scan line is received in the first bank, then pixel data corresponding to another source image scan line can be concurrently read from the second bank as many times as required.

59. Computer program product as recited in claim 56, wherein when said line buffer comprises the dual-ported memory, the data is read from a port that is different from a port that receives the source image pixel data.

60. Computer program product as recited in claim 53, further comprising:

computer code for locking the second clock to the first clock in a proportion.

61. Computer program product as recited in claim 60, wherein the proportion is equal to (Htotal.sub.−src.times.Vtotal.sub.−src)/(Htotal.sub.−dst.times.Vtotal.sub.−dst), wherein Htotal.sub.−src and Htotal.sub.−dst represent the total number of pixels in each source scan line and each destination scan line respectively, and Vtotal.sub.−src and Vtotal.sub.−dst represent the total number of lines in the source image and the destination image, respectively.

62. Computer program product as recited in claim 53, wherein the source image pixel data is received using an externally generated first clock.

63. Computer program product as recited in claim 53, wherein said source image has a source image aspect ratio and said destination image has a destination image aspect ratio that can be not equal to said source aspect ratio.

64. Computer program product as recited in claim 53, wherein when said source image is an analog source image then the first clock is provided to a sampling circuit coupled to the interface that samples the analog source image at a sampling frequency such that each scan line in said source image is sampled a number of times equal to a number of pixels in each scan line in the destination image.

65. Computer program product as recited in claim 53, further comprising:

computer code for commencing writing the source image pixel data in a particular portion of the line buffer after the reading of the stored pixel data has commenced in that same portion of the line buffer thereby avoiding an overrun condition in the line buffer.

66. Computer program product as recited in claim 54, further comprising:

computer code for suppressing a last incomplete scan line based upon a truncated vertical scaling factor (VSF).

67. Computer program product as recited in claim 66, wherein the truncated VSF is derived by truncating a fractional portion of VSF where VSF is equal to the ratio Vsize.sub.−src/Vsize.sub.−dst.

68. Computer program product as recited in claim 53, wherein said display controller is coupled to a display unit.

69. Computer program product as recited in claim 68, wherein the display unit comprises an fixed array monitor selected from a group comprising: an LCD monitor and a plasma monitor.

70. Computer program product as recited in claim 69, wherein the display unit is part of a television system.

71. Computer program product as recited in claim 53, wherein the first resolution corresponds to VGA and wherein the second resolution corresponds to a resolution selected from a group comprising: XGA, SXGA, UXGA, WQSXGA, and QSXGA.

72. Computer program product as recited in claim 53, wherein the display controller is formed as a single integrated circuit.

73. A memory efficient upscaler for upscaling a source image to a destination image having more pixels than the source image, comprising:

a source interface arranged to receive source image pixels;

a line buffer arranged to receive and store pixels from the source interface; and

a display interface arranged to receive pixels from the line buffer and provide the destination image without using a frame buffer.

74. A method for generating a plurality of image pixel data elements for display on a display screen, comprising:

receiving source image pixels from a source image;

generating a plurality of pixel data elements by sampling said source image pixels;

receiving and storing pixel data elements at a line buffer;

receiving pixel data elements from the line buffer;

providing the plurality of image pixel elements for display without using a frame buffer; and

displaying a destination image having more pixels than does the source image using the provided plurality of image pixel elements.