A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.
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0. 73. A memory efficient upscaler for upscaling a source image to a destination image having more pixels than the source image, comprising:
a source interface arranged to receive source image pixels;
a line buffer arranged to receive and store pixels from the source interface; and
a display interface arranged to receive pixels from the line buffer and provide the destination image without using a frame buffer.
0. 33. A memory efficient method for upscaling a source image at a first resolution to a destination image at a second resolution, comprising:
receiving source image pixel data in accordance with a first clock;
receiving the source image pixel data a line buffer having a size in accordance with the first resolution at the first clock;
storing the received source image pixel data in the line buffer;
reading selected stored image pixel data from the line buffer at a second clock; and
forming the destination image using the selected stored source image pixel data.
0. 74. A method for generating a plurality of image pixel data elements for display on a display screen, comprising:
receiving source image pixels from a source image;
generating a plurality of pixel data elements by sampling said source image pixels;
receiving and storing pixel data elements at a line buffer;
receiving pixel data elements from the line buffer;
providing the plurality of image pixel elements for display without using a frame buffer; and
displaying a destination image having more pixels than does the source image using the provided plurality of image pixel elements.
0. 12. A memory efficient display controller for upscaling a source image at a first resolution to a destination image at a second resolution, comprising:
an interface arranged to receive source image pixel data in accordance with a first clock;
a line buffer having a size in accordance with a first resolution scan line length arranged to receive the source image pixel data at the first clock and store the received source image pixel data therein; and
an interpolator coupled to the line buffer and arranged to form the destination image using selected stored source image pixel data read from said line buffer in accordance with a second clock.
0. 53. Computer program product for memory efficient upscaling of a source image at a first resolution to a destination image at a second resolution, comprising:
computer code for receiving source image pixel data in accordance with a first clock;
computer code for receiving the source image pixel data a line buffer having a size in accordance with the first resolution at the first clock;
computer code for storing the received source image pixel data in the line buffer;
computer code for reading selected stored image pixel data from the line buffer at a second clock;
computer code for forming the destination image using the selected stored source image pixel data; and
computer readable medium for storing the computer code.
0. 1. A circuit for use in a digital display unit of a computer system, and circuit for generating a plurality of pixel data elements from an analog image data received by said digital display unit, said digital display unit further receiving a time reference signal associated with said analog image data, said time reference signal having a high frequency, said circuit comprising:
an analog-to-digital converter (ADC) for receiving said analog image data, said ADC sampling said analog image data using a sampling clock to generate a plurality of pixel data elements corresponding to said plurality of pixels, wherein said sampling clock has a sampling frequency equal to said high frequency;
a clock generator circuit comprising a phase-locked loop (PLL) circuit for generating said sampling clock, wherein said sampling clock is synchronized with said time reference signal with a jitter of less than a few nano-seconds, said PLL comprising:
a discrete time oscillator (DTO) for receiving a digital input and generating a signal representative of said sampling clock with a frequency determined by said digital input; and
a digital circuit for receiving said time reference signal and a feedback signal, wherein said feedback signal is generated by dividing said sampling clock, said digital circuit generating said digital input according to the difference of the phases of said time reference signal and said feedback signal, said digital input causing said DTO to generate said signal synchronized with said time reference signal, said digital circuit comprising:
a frequency correction logic for adjusting the phase of said sampling clock according to the long-term drifts in the frequency of said time reference signal; and
a phase correction logic for adjusting the phase of said sampling clock according to the phase difference in said feedback signal and said time reference signal,
wherein said frequency correction logic and said phase correction logic are implemented as two separate control loops,
wherein a panel interface included in said digital display unit can generate display signals for a display screen based on said plurality of pixel data elements.
0. 2. The circuit of
0. 3. The circuit of
0. 4. The circuit of
0. 5. The circuit of
0. 6. The circuit of
0. 7. The circuit of
0. 8. The circuit of
0. 9. The circuit of
a first multiplexor accepting as input Pnom and Fdp values, wherein Pnom represents an expected frequency of said sampling clock and Fdp represents the correction due to the long-term frequency drifts;
a flip-flop for storing a value representative of the phase correction corresponding to the frequency correction logic;
an adder for adding or subtracting the output of said first multiplexor from the value stored in said flip-flop, wherein the output of said adder is stored in said flip-flop; and
a frequency correction control coupled to said flip-flop and said adder, wherein said frequency correction control causes said flip-flop to be set to Pnom at the beginning of a phase acquisition phase, and wherein said frequency correction control causes said adder to add or subtract Fdp depending on whether the sampling clock is early or late in comparison to said time reference.
0. 10. The circuit of
a phase and frequency detector for determining the difference of phase between said feedback signal and said time reference signal, wherein said phase and frequency detector asserts an EARLY signal a number of clock pulses proportionate to the difference of phase by which said feedback signal is earlier than said time reference signal and a or a LATE signal a number of pulses proportionate to the difference of phase by which said feedback signal is later than said time reference signal; and
a charge/discharge control logic implemented using digital components, said charge/discharge control logic including a phase integrator, said charge/discharge control logic charging said phase integrator according to the number of pulses said EARLY signal or said LATE signal is asserted, said charge/discharge logic discharging over a longer period of time than the charging period so as to spread the difference in phase over a comparison cycle, wherein the phase of said sampling clock is corrected during the discharging period.
0. 11. The circuit of
0. 13. A display controller as recited in
a vertical interpolator unit arranged convert a first resolution number of scan lines to a second resolution number of scan lines; and
a horizontal interpolator unit coupled to the vertical interpolator unit arranged to convert each of the second resolution number of scan lines each having the first resolution scan line length to a second resolution scan line length.
0. 14. A display controller as recited in
a second line buffer coupled to the vertical interpolator and the line buffer for storing only a previous scan line.
0. 15. A display controller as recited in
a third line buffer for storing a current scan line used with the previous scan line by the vertical interpolator to convert the first resolution number of scan lines to the second resolution number of scan lines.
0. 16. A display controller as recited in
0. 17. A display controller as recited in
0. 18. A display controller as recited in
0. 19. A display controller as recited in
0. 20. A display controller as recited in
0. 21. A display controller as recited in
0. 22. The display controller of
0. 23. The display controller of
0. 24. The display controller of
0. 25. A display controller as recited in
0. 26. A display controller as recited in
an incomplete interpolated scan line suppressor unit coupled to the interpolator unit arranged to suppress a last incomplete scan line after the horizontal interpolation based upon a truncated vertical scaling factor (VSF).
0. 27. A display controller as recited in
0. 28. The display controller of
0. 29. A display controller as recited in
0. 30. A display controller as recited in
0. 31. A display controller as recited in
0. 32. A display controller as recited in
0. 34. A method as recited in
converting a first resolution number of scan lines to a second resolution number of scan lines; and
converting each of the second resolution number of scan lines each having a first resolution scan line length to a second resolution scan line length.
0. 35. A method as recited in
0. 36. A method as recited in
0. 37. A method as recited in
0. 38. A method as recited in
0. 39. A method as recited in
0. 40. A method as recited in
locking the second clock to the first clock in a proportion.
0. 41. A method as recited in
0. 42. A method as recited in
0. 43. A method as recited in
0. 44. A method as recited in
0. 45. A method as recited in
commencing writing the source image pixel data in a particular portion of the line buffer after the reading of the stored pixel data has commenced in that same portion of the line buffer thereby avoiding an overrun condition in the line buffer.
0. 46. A method as recited in
suppressing a last incomplete scan line based upon a truncated vertical scaling factor (VSF).
0. 47. A method as recited in
0. 48. A method as recited in
0. 49. A method as recited in
0. 50. A method as recited in
0. 51. A method as recited in
0. 52. A method as recited in
0. 54. Computer program product as recited in
computer code for converting a first resolution number of scan lines to a second resolution number of scan lines; and
computer code for converting each of the second resolution number of scan lines each having a first resolution scan line length to a second resolution scan line length.
0. 55. Computer program product as recited in
0. 56. Computer program product as recited in
0. 57. Computer program product as recited in
0. 58. Computer program product as recited in
0. 59. Computer program product as recited in
0. 60. Computer program product as recited in
computer code for locking the second clock to the first clock in a proportion.
0. 61. Computer program product as recited in
0. 62. Computer program product as recited in
0. 63. Computer program product as recited in
0. 64. Computer program product as recited in
0. 65. Computer program product as recited in
computer code for commencing writing the source image pixel data in a particular portion of the line buffer after the reading of the stored pixel data has commenced in that same portion of the line buffer thereby avoiding an overrun condition in the line buffer.
0. 66. Computer program product as recited in
computer code for suppressing a last incomplete scan line based upon a truncated vertical scaling factor (VSF).
0. 67. Computer program product as recited in
0. 68. Computer program product as recited in
0. 69. Computer program product as recited in
0. 70. Computer program product as recited in
0. 71. Computer program product as recited in
0. 72. Computer program product as recited in
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The present application is related to co-pending U.S. Patent Application entitled, “A Method and Apparatus for Upscaling an Image”, Filed Concurrently with the present application, Serial Number UNASSIGNED, Attorney Docket Number: PRDN-0001, and is incorporated in its entirety herewith.
The present application is also related to and is a continuation of application Ser. No. 08/803,824 filed Feb. 24, 1997, now U.S. Pat. No. 5,796,392, entitled “Method and Apparatus for Clock Recovery in a Digital Display Unit.”
Positive slope (Charging) parameter for phase correction loop is derived from Pnom. It is also independent of the locking scheme. Kpdp controls damping of phase correction loop. For optimal tracking it may be set to 3 or 3.
Pdpd=Pnom/Kpdp (3)
Negative slope parameter (discharging) is derived from Ppdp. NPDP is usually close to Ppdp if loop is unlocked and several times smaller (8 . . . 16) if loop is locked (to minimize phase jumps).
Npdp=Ppdp/Knpdp (4)
Knpdp=2 . . . 16
Frequency correction parameter is dependent on locking scheme. It means amount of frequency adjustment per one Rclk phase tracking error.
If the FBACK signal is locked on HSYNC pulses as a time reference
Fdp=Pnom/(Kfdp*Vdiv*Hor_Rcount) (5a)
If FBACK signal is locked in Vsync pulses as a time reference
Fdp=Pnom/(Kfdp*Vtotal*Hor_Rcount) (5b)
Here Vdiv is vertical Hsync divider (1 . . . n). If Vdiv is 1, every Hsync is used for comparison. If Vdiv is 2, every other Hsync is used, etc. Vtotal is number of lines in the source frame if VSYNC locking is used.
7. Analog Filter 320
As noted above, analog filter 320 is designed to preserve the fundamental frequency generated by DTO while eliminating the other frequencies. Analog filter 320 can be implemented using active or passive filters or using a phase-locked loop as is well-known in the art. An example embodiment of analog filter 320 is illustrated with reference to FIG. 5.
Analog filter 320 is conventional and includes a DAC reconstruction filter 510. Schmidt trigger 520 slices the sine-wave in a known way to convert the sine-wave into digital signal (two level quantization). The PLL loop comprising PFD 530, charge pump 540, loop filter 550, VCO 560, and divider 580 is designed to eliminate all the undesirable frequencies, while preserving the fundamental frequency. The value of N in divider 580 is kept relatively small (at or below 8). VCO 560 may be designed to generate sampling clock signal, which can be used to sample the analog signal data. Dividers 570 and 580 may be used to shift the Vco frequency into the operating range of Vco 560.
Thus, the output of analog filter 320 includes filtered signal with well-suppressed spurious spectral components.
16. Conclusion
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
Patent | Priority | Assignee | Title |
RE42615, | Feb 24 1997 | Genesis Microchip (Delaware) Inc. | Method and system for displaying an analog image by a digital display device |
Patent | Priority | Assignee | Title |
4018990, | Feb 13 1975 | Technology Licensing Corporation | Digital video synchronizer |
4346407, | Jun 16 1980 | Lockheed Martin Corporation | Apparatus for synchronization of a source of computer controlled video to another video source |
4432009, | Mar 24 1981 | RCA Corporation | Video pre-filtering in phantom raster generating apparatus |
4462024, | Mar 24 1981 | RCA Corporation | Memory scanning address generator |
4488170, | |||
4527145, | Sep 15 1981 | Siemens Aktiengesellschaft | Method and apparatus for the digital control of the phase of the system clock of a digital signal processing system |
4554582, | Aug 31 1983 | RCA Corporation; RCA CORPORATION, A DE CORP | Apparatus for synchronizing a source of computer controlled video to another video source |
4590602, | Aug 18 1983 | INRANGE DEVELOPMENT CORPORATION | Wide range clock recovery circuit |
4616259, | Apr 27 1984 | General Electric Company | Instant phase correction in a phase-locked loop |
4686560, | May 30 1986 | RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP OF DE | Phase locked loop system including analog and digital components |
4694327, | Mar 28 1986 | RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP OF DE | Digital phase locked loop stabilization circuitry using a secondary digital phase locked loop |
4700217, | Aug 05 1986 | RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP OF DE | Chrominance signal phase locked loop system for use in a digital television receiver having a line-locked clock signal |
4703340, | May 02 1986 | RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP OF DE | Frequency division multiplexed analog to digital converter |
4720745, | Jun 22 1983 | Z Microsystems Visualization Technologies, LLC | Method and apparatus for enhancing video displays |
4802009, | Jul 13 1987 | RCA LICENSING CORPORATION, TWO INDEPENDENCE WAY, PRINCETON, NJ 08540, A CORP OF DE | Digitally controlled phase locked loop system |
4893319, | Dec 19 1988 | Planar Systems, Inc. | Clock regeneration circuit employing digital phase locked loop |
4906941, | May 25 1988 | Kabushiki Kaisha Toshiba | Digital phase locked loop circuit |
5005079, | Mar 16 1989 | Sanyo Electric Co., Ltd. | Automatic frequency control circuit |
5010403, | Apr 12 1990 | Tektronix, Inc. | Measurement of timebase jitter for component video |
5027212, | Dec 06 1989 | VideoLogic Limited | Computer based video/graphics display system |
5029017, | Oct 08 1986 | Konishiroku Photo Industry Co., Ltd. | Image processing apparatus capable of enlarging/reducing apparatus |
5086295, | Jan 12 1988 | Apparatus for increasing color and spatial resolutions of a raster graphics system | |
5101197, | Aug 17 1988 | Straight Signals LLC | Electronic transparency method and apparatus |
5184091, | Jun 04 1991 | LG Electronics Inc | Circuit for phase locking an oscillator within any one of a plurality of frequency ranges |
5185603, | Jul 13 1990 | INNOVISION INC , DBA INNOVISION LABS | Apparatus for synchronizing computer and video images to be simultaneously displayed on a monitor and method for performing same |
5202669, | Aug 24 1982 | Sharp Kabushiki Kaisha | Display control device for superimposing data with a broadcast signal on a television screen |
5227882, | Sep 29 1990 | Sharp Kabushiki Kaisha | Video display apparatus including display device having fixed two-dimensional pixel arrangement |
5276515, | Sep 26 1991 | Hitachi Maxell, Ltd | Compatible wide aspect ratio receiver with spatial filtering for variable zoom |
5280345, | Apr 04 1991 | Matsushita Electric Industrial Co., Ltd. | Jitter correction circuit for reducing jitter components of a luminance signal in video information compression |
5331346, | Oct 07 1992 | Matsushita Electric Corporation of America | Approximating sample rate conversion system |
5335018, | Nov 25 1991 | U.S. Philips Corporation | Digital phase-locked loop |
5335295, | May 08 1991 | International Business Machines Corporation | System and method for scaling a digital image |
5349385, | Aug 06 1992 | FLORIDA ATLANTIC UNIVERSITY RESEARCH CORP | Adaptive scan converter |
5359366, | Dec 27 1991 | Victor Company of Japan, Ltd. | Time base correction apparatus |
5369376, | Nov 29 1991 | STANDARD MICROSYSTEMS CORP | Programmable phase locked loop circuit and method of programming same |
5406308, | Feb 01 1993 | NLT TECHNOLOGIES, LTD | Apparatus for driving liquid crystal display panel for different size images |
5410357, | Apr 12 1993 | The United States of America as represented by the Secretary of the Navy | Scan converter and method |
5455628, | Sep 16 1992 | Imagination Technologies Limited | Converter to convert a computer graphics signal to an interlaced video signal |
5459766, | Apr 05 1993 | U S PHILIPS CORPORATION | Digital phase-locked loop |
5469223, | Oct 13 1993 | CREATIVE TECHNOLOGY LTD | Shared line buffer architecture for a video processing circuit |
5497202, | Mar 11 1994 | SAMSUNG ELECTRONICS CO , LTD | Automatic digital frequency control circuit |
5515108, | Aug 18 1993 | SAMSUNG ELECTRONICS CO , LTD | Digital automatic frequency control method and circuit therefor |
5528305, | Sep 08 1993 | SAMSUNG ELECTRONICS CO , LTD | Method for reducing empty sides of a wide screen and an apparatus thereof |
5528307, | Jul 18 1991 | Canon Kabushiki Kaisha | Clock generator |
5534934, | Jun 18 1993 | MAXELL, LTD | Television receiver capable of enlarging and compressing image |
5534936, | Feb 17 1994 | Goldstar Co., Ltd. | Apparatus for reducing flickers of encoder when digitally converting video signals from non-interlaced to interlaced format |
5535018, | Oct 15 1991 | Canon Kabushiki Kaisha | Information processing apparatus |
5539473, | Mar 31 1994 | HTC Corporation | Dot clock generation with minimal clock skew |
5574406, | Apr 20 1993 | RCA Thomson Licensing Corporation | Phase lock loop with error measurement and correction in alternate periods |
5574572, | Sep 07 1994 | INTERSIL AMERICAS LLC | Video scaling method and device |
5587742, | Aug 25 1995 | Panasonic Corporation of North America | Flexible parallel processing architecture for video resizing |
5594467, | Dec 06 1989 | Imagination Technologies Limited | Computer based display system allowing mixing and windowing of graphics and video |
5600347, | Dec 30 1993 | International Business Machines Corporation | Horizontal image expansion system for flat panel displays |
5623311, | Oct 28 1994 | Panasonic Corporation of North America | MPEG video decoder having a high bandwidth memory |
5638131, | Mar 10 1993 | THE BANK OF NEW YORK TRUST COMPANY, N A | Method to synchronize video modulation using a constant time base |
5646696, | Dec 23 1992 | Intel Corporation | Continuously changing image scaling performed by incremented pixel interpolation |
5703618, | Nov 22 1995 | S3 GRAPHICS CO , LTD | Method and apparatus for upscaling video images when pixel data used for upscaling a source video image are unavailable |
5710573, | May 04 1995 | Winbond Electronics Corp. | Scaled video output overlaid onto a computer graphics output |
5719633, | Dec 20 1994 | Matsushita Electric Industrial Co., Ltd. | Video signal format conversion apparatus using simplified shifting and processing control |
5739808, | Oct 28 1994 | Canon Kabushiki Kaisha | Display control method and apparatus |
5781241, | Nov 08 1996 | Chrontel, Inc | Apparatus and method to convert computer graphics signals to television video signals with vertical and horizontal scaling requiring no frame buffers |
5790096, | Sep 03 1996 | LG Electronics Inc | Automated flat panel display control system for accomodating broad range of video types and formats |
5790614, | Jun 09 1993 | ALCATEL NETWORK SYSTEMS, INC | Synchronized clock using a non-pullable reference oscillator |
5796392, | Feb 24 1997 | GENESIS MICROCHIP DELAWARE INC | Method and apparatus for clock recovery in a digital display unit |
5838381, | Dec 25 1995 | Hitachi Maxell, Ltd | Image display apparatus capable of displaying personal computer signals and television signal by conversion into a signal of a higher number of pixels |
5841430, | Jan 30 1992 | ICL Personal Systems OY | Digital video display having analog interface with clock and video signals synchronized to reduce image flicker |
5874937, | Oct 20 1995 | Seiko Epson Corporation | Method and apparatus for scaling up and down a video image |
5909205, | Nov 30 1995 | Hitachi Maxell, Ltd | Liquid crystal display control device |
5914753, | Nov 08 1996 | Chrontel, Inc. | Apparatus and method to convert computer graphics signals to television video signals with vertical and horizontal scaling requiring no frame buffers |
5926174, | May 29 1995 | Canon Kabushiki Kaisha | Display apparatus capable of image display for video signals of plural kinds |
5940061, | Sep 22 1995 | Kabushiki Kaisha Toshiba | Liquid-crystal display |
5953074, | Nov 18 1996 | Sage, Inc. | Video adapter circuit for detection of analog video scanning formats |
6002446, | Feb 24 1997 | GENESIS MICROCHIP DELAWARE INC | Method and apparatus for upscaling an image |
6002810, | Apr 14 1995 | PANASONIC LIQUID CRYSTAL DISPLAY CO , LTD | Resolution conversion system and method |
6037925, | Apr 17 1996 | SAMSUNG ELECTRONICS CO , LTD , A CORP OF KOREA | Video signal converting apparatus and a display device having the same |
6046737, | Feb 14 1996 | Fujitsu Limited | Display device with a display mode identification function and a display mode identification method |
6067071, | Jun 27 1996 | SMART ASIC, INC ; SMARTASIC TECHNOLOGY, INC | Method and apparatus for expanding graphics images for LCD panels |
6078317, | Oct 12 1994 | Canon Kabushiki Kaisha | Display device, and display control method and apparatus therefor |
6078361, | Nov 18 1996 | Sage, Inc | Video adapter circuit for conversion of an analog video signal to a digital display image |
6115020, | Mar 29 1996 | Sharp Kabushiki Kaisha | Liquid crystal display device and display method of the same |
6121947, | Nov 30 1995 | Hitachi Maxell, Ltd | Liquid crystal display Control device |
6144355, | Oct 16 1995 | JAPAN DISPLAY CENTRAL INC | Display device including a phase adjuster |
6195079, | Nov 18 1996 | Sage, Inc. | On-screen user interface for a video adapter circuit |
6215467, | Apr 27 1995 | Canon Kabushiki Kaisha | Display control apparatus and method and display apparatus |
6219023, | Jul 05 1996 | SAMSUNG ELECTRONICS CO , LTD , A CORPORATION OF THE REPUBLIC OF KOREA | Video signal converting apparatus with display mode conversion and a display device having the same |
6310602, | Sep 30 1993 | Hitachi Maxell, Ltd | Liquid crystal display system capable of reducing and enlarging resolution of input display data |
6310618, | Nov 13 1998 | WZ TECHNOLOGY INC | Clock generation for sampling analong video |
6320574, | Feb 24 1997 | GENESIS MICROCHIP DELAWARE INC | Circuit and method for generating pixel data elements from analog image data and associated synchronization signals |
EP299724, | |||
EP405523, | |||
EP479508, | |||
EP609843, | |||
EP502600, | |||
EP56137736, | |||
EP615222, | |||
JP10161635, | |||
JP1169492, | |||
JP2033271, | |||
JP2302173, | |||
JP4138494, | |||
JP5083534, | |||
JP5150219, | |||
JP522277, | |||
JP6030247, | |||
JP61103369, | |||
JP6205256, | |||
JP62146066, | |||
JP6274611, | |||
JP63008983, | |||
JP6314522, | |||
JP63188276, | |||
JP7135592, | |||
JP7334141, | |||
JP8172353, | |||
JP8340254, | |||
JP9247574, | |||
WO8905065, |
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